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Searched refs:SDEIMR (Results 1 – 3 of 3) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Di915_irq.c183 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~bit); in ibx_set_fifo_underrun_reporting()
185 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | bit); in ibx_set_fifo_underrun_reporting()
187 POSTING_READ(SDEIMR); in ibx_set_fifo_underrun_reporting()
204 I915_WRITE(SDEIMR, I915_READ(SDEIMR) & ~SDE_ERROR_CPT); in cpt_set_fifo_underrun_reporting()
206 I915_WRITE(SDEIMR, I915_READ(SDEIMR) | SDE_ERROR_CPT); in cpt_set_fifo_underrun_reporting()
209 POSTING_READ(SDEIMR); in cpt_set_fifo_underrun_reporting()
2533 I915_WRITE(SDEIMR, 0xffffffff); in ibx_irq_preinstall()
2632 u32 mask = ~I915_READ(SDEIMR); in ibx_hpd_irq_setup()
2647 I915_WRITE(SDEIMR, ~mask); in ibx_hpd_irq_setup()
2681 I915_WRITE(SDEIMR, ~mask); in ibx_irq_postinstall()
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H A Di915_reg.h3967 #define SDEIMR 0xc4004 macro
/gfx-drm/usr/src/cmd/mdb/i915/
H A Di915.c1518 ret = i915_read(dev_priv, (uintptr_t)SDEIMR, &val); in i915_interrupt_info()