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Searched refs:REG_WR (Results 1 – 25 of 39) sorted by relevance

12

/illumos-gate/usr/src/uts/common/io/bnx/570x/driver/common/lmdev/
H A Dbnx_hw_reset.c382 REG_WR( in alloc_bad_rbuf_5706_a0_wa()
735 REG_WR( in lm_chip_reset()
964 REG_WR( in l4_reset_setup()
972 REG_WR( in l4_reset_setup()
980 REG_WR( in l4_reset_setup()
1683 REG_WR( in init_hc()
1688 REG_WR( in init_hc()
1693 REG_WR( in init_hc()
1698 REG_WR( in init_hc()
1703 REG_WR( in init_hc()
[all …]
H A Dbnx_hw_misc.c40 REG_WR(pdev, emac.emac_mac_match[addr_idx*2], val); in lm_set_mac_addr()
44 REG_WR(pdev, emac.emac_mac_match[addr_idx*2+1], val); in lm_set_mac_addr()
71 REG_WR(pdev, pci_config.pcicfg_reg_window_address, offset); in lm_reg_rd_ind()
100 REG_WR(pdev, pci_config.pcicfg_reg_window, val); in lm_reg_wr_ind()
137 REG_WR(pdev, context.ctx_ctx_data, val); in lm_ctx_wr()
156 REG_WR(pdev, context.ctx_data_adr, offset); in lm_ctx_wr()
157 REG_WR(pdev, context.ctx_data, val); in lm_ctx_wr()
213 REG_WR(pdev, context.ctx_data_adr, offset); in lm_ctx_rd()
282 REG_WR(pdev, hc.hc_config, val); in lm_enable_int()
313 REG_WR(pdev, pci.pci_grc_window_addr, grc_win_base); in lm_reg_rd_blk()
[all …]
H A Dbnx_hw_nvram.c367 REG_WR( in enable_nvram_access()
391 REG_WR( in disable_nvram_access()
593 REG_WR(pdev, nvm.nvm_write, val); in nvram_write_dword()
647 REG_WR(pdev, nvm.nvm_cfg3, 0x57848353); in find_atmel_size()
648 REG_WR(pdev, nvm.nvm_read, 0); in find_atmel_size()
662 REG_WR(pdev, nvm.nvm_cfg3, orig); in find_atmel_size()
724 REG_WR(pdev, nvm.nvm_write, 0); in find_stm_size()
729 REG_WR(pdev, nvm.nvm_write, bit); in find_stm_size()
734 REG_WR(pdev, nvm.nvm_write, 0); in find_stm_size()
748 REG_WR(pdev, nvm.nvm_write, 0); in find_stm_size()
[all …]
H A Dbnx_lm_main.c3610 REG_WR( in init_nwuf_5709()
3622 REG_WR( in init_nwuf_5709()
3690 REG_WR( in init_nwuf_5709()
3983 REG_WR(pdev, emac.emac_mode, val); in set_d0_power_state()
4056 REG_WR( in set_d3_power_state()
4092 REG_WR( in set_d3_power_state()
4145 REG_WR( in set_d3_power_state()
4151 REG_WR( in set_d3_power_state()
4159 REG_WR( in set_d3_power_state()
4369 REG_WR( in lm_get_interrupt_status()
[all …]
H A Dbnx_hw_phy.c53 REG_WR(pdev, emac.emac_mdio_mode, tmp); in lm_mwrite()
65 REG_WR(pdev, emac.emac_mdio_comm, tmp); in lm_mwrite()
95 REG_WR(pdev, emac.emac_mdio_mode, tmp); in lm_mwrite()
137 REG_WR(pdev, emac.emac_mdio_comm, val); in lm_mread()
632 REG_WR(pdev, emac.emac_mode, val); in init_utp()
1187 REG_WR(pdev, emac.emac_mode, val); in init_5708_serdes()
1555 REG_WR(pdev, emac.emac_mode, val); in init_5709_serdes()
1770 REG_WR(pdev, emac.emac_mode, val); in init_5706_serdes()
3010 REG_WR(pdev, emac.emac_mode, val); in init_mac_link()
3955 REG_WR( in lm_service_phy_int()
[all …]
H A Dbnx_hw_cpu.c123 REG_WR(pdev, rv2p.rv2p_instr_high, *rv2p_code); in load_rv2p_fw()
125 REG_WR(pdev, rv2p.rv2p_instr_low, *rv2p_code); in load_rv2p_fw()
131 REG_WR(pdev, rv2p.rv2p_proc1_addr_cmd, val); in load_rv2p_fw()
136 REG_WR(pdev, rv2p.rv2p_proc2_addr_cmd, val); in load_rv2p_fw()
143 REG_WR(pdev, rv2p.rv2p_command, RV2P_COMMAND_PROC1_RESET); in load_rv2p_fw()
147 REG_WR(pdev, rv2p.rv2p_command, RV2P_COMMAND_PROC2_RESET); in load_rv2p_fw()
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_hw_init_reset.c2542 REG_WR(pdev, in lm_ncsi_fcoe_cap_to_scratchpad()
2651 REG_WR(pdev, offset, val ) ; in init_aeu_port()
2661 REG_WR(pdev, offset, val); in init_aeu_port()
3283 REG_WR(pdev,SRC_REG_SOFT_RST,1); in init_src_common()
3298 REG_WR(pdev,SRC_REG_SOFT_RST,0); in init_src_common()
3634 REG_WR(pdev,0x2814,0xffffffff); in init_pxpcs_common()
3635 REG_WR(pdev,0x3820,0xffffffff); in init_pxpcs_common()
3654 REG_WR(pdev,0x2114,0xffffffff); in init_pxpcs_func()
3655 REG_WR(pdev,0x2120,0xffffffff); in init_pxpcs_func()
3805 REG_WR(pdev,CFC_REG_DEBUG0,0x1); in prs_brb_mem_setup()
[all …]
H A Dlm_hw_attn.c144 REG_WR(pdev,PXP_REG_PXP_INT_MASK_0,0); in enable_blocks_attention()
159 REG_WR(pdev,QM_REG_QM_INT_MASK ,0); in enable_blocks_attention()
160 REG_WR(pdev,TM_REG_TM_INT_MASK ,0); in enable_blocks_attention()
163 REG_WR(pdev,XCM_REG_XCM_INT_MASK ,0); in enable_blocks_attention()
168 REG_WR(pdev,UCM_REG_UCM_INT_MASK ,0); in enable_blocks_attention()
174 REG_WR(pdev,CCM_REG_CCM_INT_MASK ,0); in enable_blocks_attention()
189 REG_WR(pdev,TCM_REG_TCM_INT_MASK ,0); in enable_blocks_attention()
192 REG_WR(pdev,CDU_REG_CDU_INT_MASK ,0); in enable_blocks_attention()
441 REG_WR(pdev, offset, val ); in disable_blocks_attention()
1069 REG_WR(pdev, offset, val ) ; in lm_spio5_attn_everest_processing()
[all …]
H A Dlm_er.c94 REG_WR(pdev, MISC_REG_AEU_GENERAL_MASK, val); in lm_er_disable_close_the_gate()
116 REG_WR(pdev, IGU_REG_BLOCK_CONFIGURATION, val); in lm_er_set_234_gates()
129 REG_WR(pdev, PXP2_REG_RD_START_INIT, 0); in lm_er_pxp_prep()
130 REG_WR(pdev, PXP2_REG_RQ_RBC_DONE, 0); in lm_er_pxp_prep()
323 REG_WR(pdev, MISC_REG_UNPREPARED, 0); in lm_er_process_kill()
375 REG_WR(pdev, MISC_REG_AEU_GENERAL_ATTN_20 , 0); in lm_er_process_kill()
448 REG_WR(pdev, MISC_REG_AEU_GENERAL_ATTN_20 , 1); in lm_er_notify_other_path()
482 REG_WR(pdev, MISC_REG_AEU_ENABLE2_NIG_0, val); in lm_er_config_close_the_g8()
486 REG_WR(pdev, MISC_REG_AEU_ENABLE2_PXP_0, val); in lm_er_config_close_the_g8()
491 REG_WR(pdev, MISC_REG_AEU_ENABLE4_NIG_0, val); in lm_er_config_close_the_g8()
[all …]
H A Dlm_nvram.c69 REG_WR(pdev, MCP_REG_MCPR_NVM_SW_ARB, (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port_num )); in acquire_nvram_lock()
117 REG_WR(pdev, MCP_REG_MCPR_NVM_SW_ARB, (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port_num)); in release_nvram_lock()
155 REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
198 REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE);
294 REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); in nvram_read_dword()
297 REG_WR(pdev, MCP_REG_MCPR_NVM_ADDR, offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE); in nvram_read_dword()
300 REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); in nvram_read_dword()
362 REG_WR(pdev, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); in nvram_write_dword()
365 REG_WR(pdev, MCP_REG_MCPR_NVM_WRITE, val); in nvram_write_dword()
368 REG_WR(pdev, MCP_REG_MCPR_NVM_ADDR, offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE); in nvram_write_dword()
[all …]
H A Dlm_hw_access.c394 REG_WR(pdev,MISC_REG_SPIO_INT, val ) ; in lm_setup_fan_failure_detection()
399 REG_WR(pdev,MISC_REG_SPIO_EVENT_EN, val ) ; in lm_setup_fan_failure_detection()
584 REG_WR(pdev, MISC_REG_GPIO, gpio_reg); in lm_gpio_write()
648 REG_WR(pdev, MISC_REG_GPIO, gpio_reg); in lm_gpio_mult_write()
715 REG_WR(pdev, MISC_REG_GPIO_INT, gpio_reg); in lm_gpio_int_write()
776 REG_WR(pdev, MISC_REG_SPIO, reg_val); in lm_spio_read()
842 REG_WR(pdev, MISC_REG_SPIO, reg_val); in lm_spio_write()
1449 REG_WR(pdev, reg_offset, enable_mac); in lm_set_mac_in_nig()
1580 REG_WR(pdev, hw_lock_cntr_reg, resource_bit); in lm_hw_unlock_ex()
1914 REG_WR(pdev,DRV_DUMP_TSTORM_WAITP_ADDRESS,1); in lm_set_waitp()
[all …]
H A Dlm_power.c129 REG_WR( pdev, reg_len, val ) ; in init_nwuf_57710()
132 REG_WR( pdev, reg_crc, val ) ; in init_nwuf_57710()
255 REG_WR( pdev, offset, nwuf_reg_value ) ; in lm_set_d3_nwuf()
277 REG_WR( pdev, offset, nwuf_reg_value ) ; in lm_set_d3_nwuf()
321 REG_WR(pdev, emac_base+ offset , b_enable_mpkt ? val:0); in lm_set_d3_mpkt()
326 REG_WR(pdev, emac_base+ offset, b_enable_mpkt ? val:0); in lm_set_d3_mpkt()
379 REG_WR(pdev, emac.emac_mode, val); in set_d0_power_state()
383 REG_WR(pdev, rpm.rpm_config, val); in set_d0_power_state()
485 REG_WR(pdev, pcicfg_device_control_offset, pf0_pcie_status_control); in lm_pcie_state_restore_for_d0()
H A Dlm_sb.c947 REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl.ctrl_data); in lm_int_igu_ack_sb()
981 REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl.ctrl_data); in lm_int_igu_sb_cleanup()
1002 REG_WR(pdev, IGU_REG_COMMAND_REG_CTRL, cmd_ctrl.ctrl_data); in lm_int_igu_sb_cleanup()
1149 REG_WR(pdev, HC_REG_INT_MASK + PORT_ID(pdev)*4, 0x1FFFF); in lm_enable_hc_int()
1152 REG_WR(pdev, reg_name, val); in lm_enable_hc_int()
1224 REG_WR(pdev, IGU_REG_PF_CONFIGURATION, val); in lm_enable_igu_int()
1246 REG_WR(pdev, IGU_REG_TRAILING_EDGE_LATCH, val); in lm_enable_igu_int()
1247 REG_WR(pdev, IGU_REG_LEADING_EDGE_LATCH, val); in lm_enable_igu_int()
1286 REG_WR(pdev, HC_REG_INT_MASK + PORT_ID(pdev)*4, 0); in lm_disable_hc_int()
1292 REG_WR(pdev, reg_name, val); in lm_disable_hc_int()
[all …]
H A Dlm_phy.c82 REG_WR(cb, reg_addr, val); in elink_cb_reg_write()
249 REG_WR(pdev,NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 1); in lm_mwrite()
258 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE,tmp); in lm_mwrite()
267 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_COMM,tmp); in lm_mwrite()
298 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE,tmp); in lm_mwrite()
300 REG_WR(pdev,NIG_REG_XGXS0_CTRL_MD_ST + in lm_mwrite()
323 REG_WR(pdev,NIG_REG_XGXS0_CTRL_MD_ST + port*0x18, 1); in lm_mread()
332 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE,val); in lm_mread()
341 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_COMM,val); in lm_mread()
375 REG_WR(pdev,emac_base+EMAC_REG_EMAC_MDIO_MODE,val); in lm_mread()
[all …]
H A Dlm_mcp.c151 REG_WR(pdev, shmem + validity_offset, 0); in lm_reset_mcp_prep()
240 REG_WR(pdev, MISC_REG_DRIVER_CONTROL_15 + 4, 0xffffffff); in lm_reset_mcp()
246 REG_WR(pdev, GRCBASE_MISC+ MISC_REGISTERS_RESET_REG_2_CLEAR, in lm_reset_mcp()
253 REG_WR(pdev, MISC_REG_DRIVER_CONTROL_15, 0xffffffff); in lm_reset_mcp()
284 REG_WR(pdev, GRCBASE_MCP + 0x9c, val_wr); in acquire_split_alr()
326 REG_WR(pdev, GRCBASE_MCP + 0x9c, val); in release_split_alr()
H A Dlm_pf.c381 REG_WR(pf_dev, IGU_REG_PCI_VF_MSIX_EN, 0);
382 REG_WR(pf_dev, IGU_REG_PCI_VF_MSIX_FUNC_MASK, 0);
383 REG_WR(pf_dev, PGLUE_B_REG_INTERNAL_VFID_ENABLE, 0);
389 REG_WR(pf_dev, 0x24d8, 1<<29);
391 REG_WR(pf_dev, PGLUE_B_REG_SR_IOV_DISABLED_REQUEST_CLR ,(1<<ABS_FUNC_ID(pf_dev)));
973 REG_WR(PFDEV(pdev), IGU_REG_MAPPING_MEMORY + 4*igu_sb_idx, 0); in lm_pf_clear_vf_igu_blocks()
989 REG_WR(PFDEV(pdev), IGU_REG_MAPPING_MEMORY + 4*igu_sb_idx, 0); in lm_pf_release_vf_igu_block()
1013 REG_WR(PFDEV(pdev), IGU_REG_MAPPING_MEMORY + 4*igu_sb_idx, value); in lm_pf_acquire_vf_igu_block()
1181 …REG_WR(PFDEV(pdev), CSEM_REG_FAST_MEMORY + CSTORM_BYTE_COUNTER_OFFSET(LM_FW_VF_DHC_QZONE_ID(vf_inf… in lm_pf_update_vf_ndsb()
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/ecore/
H A Decore_init_ops.h43 REG_WR(pdev, addr + i*4, data[i]); in ecore_init_str_wr()
275 REG_WR(pdev, addr, op->write.val); in ecore_init_block()
520 REG_WR(pdev, read_arb_addr[i].add, in ecore_init_pxp_arb()
522 REG_WR(pdev, read_arb_addr[i].ubound, in ecore_init_pxp_arb()
530 REG_WR(pdev, write_arb_addr[i].l, in ecore_init_pxp_arb()
533 REG_WR(pdev, write_arb_addr[i].add, in ecore_init_pxp_arb()
541 REG_WR(pdev, write_arb_addr[i].l, in ecore_init_pxp_arb()
545 REG_WR(pdev, write_arb_addr[i].add, in ecore_init_pxp_arb()
595 REG_WR(pdev, PXP2_REG_WR_HC_MPS, val); in ecore_init_pxp_arb()
600 REG_WR(pdev, PXP2_REG_WR_QM_MPS, val); in ecore_init_pxp_arb()
[all …]
H A Decore_init.h210 REG_WR(pdev, mcp_attn_ctl_regs[i].addr, reg_val); in ecore_set_mcp_parity()
234 REG_WR(pdev, ecore_blocks_parity_data[i].mask_addr, in ecore_disable_blocks_parity()
259 REG_WR(pdev, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in ecore_clear_blocks_parity()
260 REG_WR(pdev, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in ecore_clear_blocks_parity()
261 REG_WR(pdev, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in ecore_clear_blocks_parity()
262 REG_WR(pdev, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); in ecore_clear_blocks_parity()
292 REG_WR(pdev, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780); in ecore_clear_blocks_parity()
303 REG_WR(pdev, ecore_blocks_parity_data[i].mask_addr, in ecore_enable_blocks_parity()
H A Decore_common.h51 REG_WR(pdev, addr + (i * 4), data[i]); in __storm_memset_struct()
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/basic_vf/
H A Dlm_vf.c182 REG_WR(pf_dev, IGU_REG_PCI_VF_MSIX_EN, 0); in lm_vf_dis()
190 REG_WR(pf_dev, 0x24d8, 1<<29); in lm_vf_dis()
459 REG_WR(PFDEV(pdev), PBF_REG_DISABLE_VF,0); in lm_vf_enable_vf()
522 REG_WR(PFDEV(pdev), IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); in lm_vf_enable_igu_int()
523 REG_WR(PFDEV(pdev), IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); in lm_vf_enable_igu_int()
524 REG_WR(PFDEV(pdev), IGU_REG_SB_MASK_LSB, 0); in lm_vf_enable_igu_int()
525 REG_WR(PFDEV(pdev), IGU_REG_SB_MASK_MSB, 0); in lm_vf_enable_igu_int()
526 REG_WR(PFDEV(pdev), IGU_REG_PBA_STATUS_LSB, 0); in lm_vf_enable_igu_int()
527 REG_WR(PFDEV(pdev), IGU_REG_PBA_STATUS_MSB, 0); in lm_vf_enable_igu_int()
542 REG_WR(PFDEV(pdev), IGU_REG_VF_CONFIGURATION, val); in lm_vf_enable_igu_int()
[all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/common/
H A Dbnxe_clc.c351 REG_WR(cb, reg, val); in elink_bits_en()
360 REG_WR(cb, reg, val); in elink_bits_dis()
389 REG_WR(cb, params->lfa_base + in elink_check_lfa()
7511 REG_WR(cb, addr, val); in elink_chng_link_count()
13989 REG_WR(cb, GRCBASE_MISC + in elink_avoid_link_flap()
13993 REG_WR(cb, GRCBASE_MISC + in elink_avoid_link_flap()
14020 REG_WR(cb, params->lfa_base + in elink_avoid_link_flap()
14043 REG_WR(cb, params->lfa_base + in elink_cannot_avoid_link_flap()
14047 REG_WR(cb, params->lfa_base + in elink_cannot_avoid_link_flap()
14051 REG_WR(cb, params->lfa_base + in elink_cannot_avoid_link_flap()
[all …]
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/fw/
H A Dbnxe_fw_funcs.c66 REG_WR(pdev, ECORE_Q_VOQ_REG_ADDR(pf_q_num), new_cos); in ecore_map_q_cos()
71 REG_WR(pdev, reg_addr, reg_bit_map & (~q_bit_map)); in ecore_map_q_cos()
76 REG_WR(pdev, reg_addr, reg_bit_map | q_bit_map); in ecore_map_q_cos()
87 REG_WR(pdev, reg_addr, reg_bit_map); in ecore_map_q_cos()
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/vf/channel_vf/
H A Dlm_vf.c219 REG_WR(PFDEV(pdev), reg, val); in lm_pf_vf_fill_init_vf_response()
558 REG_WR(PFDEV(pdev), reg, val); in lm_pf_vf_fill_close_vf_response()
2941 REG_WR(PFDEV(pdev), IGU_REG_SB_MASK_LSB, 0); in lm_pf_enable_vf_igu_int()
2942 REG_WR(PFDEV(pdev), IGU_REG_SB_MASK_MSB, 0); in lm_pf_enable_vf_igu_int()
2943 REG_WR(PFDEV(pdev), IGU_REG_PBA_STATUS_LSB, 0); in lm_pf_enable_vf_igu_int()
2944 REG_WR(PFDEV(pdev), IGU_REG_PBA_STATUS_MSB, 0); in lm_pf_enable_vf_igu_int()
2959 REG_WR(PFDEV(pdev), IGU_REG_VF_CONFIGURATION, val); in lm_pf_enable_vf_igu_int()
2996 REG_WR(PFDEV(pdev), IGU_REG_VF_CONFIGURATION, val); in lm_pf_disable_vf_igu_int()
3025 REG_WR(PFDEV(pdev), PBF_REG_DISABLE_VF,0); in lm_pf_enable_vf()
3088 REG_WR(PFDEV(pdev), PBF_REG_DISABLE_VF,1); in lm_pf_disable_vf()
[all …]
/illumos-gate/usr/src/uts/common/io/bnx/
H A Dbnxint.c212 REG_WR(lmdevice, pci_config.pcicfg_int_ack_cmd, in bnx_intr_1lvl()
231 REG_WR(lmdevice, pci_config.pcicfg_int_ack_cmd, value32); in bnx_intr_1lvl()
/illumos-gate/usr/src/uts/common/io/qede/579xx/drivers/ecore/
H A Decore_hw.c200 REG_WR(p_hwfn, in ecore_ptt_set_win()
273 REG_WR(p_hwfn, bar_addr, val); in ecore_wr()
395 REG_WR(p_hwfn, in ecore_fid_pretend()
411 REG_WR(p_hwfn, in ecore_port_pretend()
428 REG_WR(p_hwfn, in ecore_port_unpretend()

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