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Searched refs:PIPE_VBLANK_INTERRUPT_STATUS (Results 1 – 3 of 3) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Di915_irq.c958 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS) in valleyview_irq_handler()
3034 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS && in i8xx_irq_handler()
3038 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS && in i8xx_irq_handler()
3227 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS && in i915_irq_handler()
H A Di915_reg.h3047 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) macro
H A Dintel_display.c780 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); in intel_wait_for_vblank()
784 PIPE_VBLANK_INTERRUPT_STATUS, in intel_wait_for_vblank()