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Searched refs:PIPE_CONTROL_QW_WRITE (Results 1 – 2 of 2) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Dintel_ringbuffer.c205 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); in intel_emit_post_sync_nonzero_flush()
252 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL; in gen6_render_ring_flush()
345 flags |= PIPE_CONTROL_QW_WRITE; in gen7_render_ring_flush()
736 intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \
762 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | in pc_render_add_request()
780 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | in pc_render_add_request()
H A Di915_reg.h404 #define PIPE_CONTROL_QW_WRITE (1<<14) macro