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Searched refs:PIPE_CONTROL_CONST_CACHE_INVALIDATE (Results 1 – 2 of 2) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Dintel_ringbuffer.c247 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; in gen6_render_ring_flush()
340 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; in gen7_render_ring_flush()
H A Di915_reg.h413 #define PIPE_CONTROL_CONST_CACHE_INVALIDATE (1<<3) macro