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Searched refs:PIPE_B (Results 1 – 6 of 6) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Dintel_pm.c1388 if (g4x_compute_wm0(dev, PIPE_B, in valleyview_update_wm()
1392 enabled |= 1 << PIPE_B; in valleyview_update_wm()
1444 if (g4x_compute_wm0(dev, PIPE_B, in g4x_update_wm()
1448 enabled |= 1 << PIPE_B; in g4x_update_wm()
1815 if (g4x_compute_wm0(dev, PIPE_B, in ironlake_update_wm()
1826 enabled |= 1 << PIPE_B; in ironlake_update_wm()
1900 if (g4x_compute_wm0(dev, PIPE_B, in sandybridge_update_wm()
1911 enabled |= 1 << PIPE_B; in sandybridge_update_wm()
2003 if (g4x_compute_wm0(dev, PIPE_B, in ivybridge_update_wm()
2014 enabled |= 1 << PIPE_B; in ivybridge_update_wm()
[all …]
H A Di915_ums.c226 i915_save_palette(dev, PIPE_B); in i915_save_display_reg()
474 i915_restore_palette(dev, PIPE_B); in i915_restore_display_reg()
H A Dintel_ddi.c811 case PIPE_B: in intel_ddi_enable_transcoder_func()
925 *pipe = PIPE_B; in intel_ddi_get_hw_state()
H A Dintel_display.c1042 panel_pipe = PIPE_B; in assert_panel_unlocked()
2273 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); in ivb_modeset_global_resources()
2285 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); in ivb_modeset_global_resources()
3950 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); in ironlake_check_fdi_lanes()
3977 case PIPE_B: in ironlake_check_fdi_lanes()
4733 (pipe == PIPE_B || pipe == PIPE_C)) in intel_set_pipe_timings()
4973 if (crtc->pipe != PIPE_B) in i9xx_get_pfit_config()
5563 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); in cpt_enable_fdi_bc_bifurcation()
5580 case PIPE_B: in ivybridge_update_fdi_bc_bifurcation()
6015 trans_edp_pipe = PIPE_B; in haswell_get_pipe_config()
H A Di915_irq.c1062 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false)) in ivb_err_int_handler()
1312 if (intel_set_cpu_fifo_underrun_reporting(dev, PIPE_B, false)) in ironlake_irq_handler()
H A Di915_drv.h56 PIPE_B, enumerator