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Searched refs:PIPECONF_ENABLE (Results 1 – 6 of 6) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Dintel_overlay.c831 … (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE) in check_overlay_possible_on_crtc()
H A Dintel_sprite.c658 if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE)) { in intel_update_plane()
H A Dintel_display.c1068 cur_state = !!(val & PIPECONF_ENABLE); in assert_pipe()
1649 if (val & PIPECONF_ENABLE) in intel_enable_pipe()
1652 I915_WRITE(reg, val | PIPECONF_ENABLE); in intel_enable_pipe()
1689 if ((val & PIPECONF_ENABLE) == 0) in intel_disable_pipe()
1692 I915_WRITE(reg, val & ~PIPECONF_ENABLE); in intel_disable_pipe()
4998 if (!(tmp & PIPECONF_ENABLE)) in i9xx_get_pipe_config()
5888 if (!(tmp & PIPECONF_ENABLE)) in ironlake_get_pipe_config()
6031 if (!(tmp & PIPECONF_ENABLE)) in haswell_get_pipe_config()
H A Dintel_tv.c1108 I915_WRITE(pipeconf_reg, pipeconf & ~PIPECONF_ENABLE); in intel_tv_mode_set()
H A Di915_reg.h2971 #define PIPECONF_ENABLE (1UL<<31) /* OSOL_i915 */ macro
H A Di915_irq.c367 return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; in i915_pipe_enabled()