Home
last modified time | relevance | path

Searched refs:PIPEA_PP_STATUS (Results 1 – 2 of 2) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Dintel_dp.c226 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS; in ironlake_edp_have_panel_power()
250 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS; in intel_dp_check_edp()
924 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS; in ironlake_wait_panel_status()
1004 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS; in ironlake_edp_panel_vdd_on()
1034 pp_stat_reg = IS_VALLEYVIEW(dev) ? PIPEA_PP_STATUS : PCH_PP_STATUS; in ironlake_panel_vdd_off_sync()
H A Di915_reg.h4392 #define PIPEA_PP_STATUS (VLV_DISPLAY_BASE + 0x61200) macro
4404 #define VLV_PIPE_PP_STATUS(pipe) _PIPE(pipe, PIPEA_PP_STATUS, PIPEB_PP_STATUS)