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Searched refs:PCH_DPLL_SEL (Results 1 – 2 of 2) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Dintel_display.c2955 temp = I915_READ(PCH_DPLL_SEL); in ironlake_pch_enable()
2962 I915_WRITE(PCH_DPLL_SEL, temp); in ironlake_pch_enable()
3441 temp = I915_READ(PCH_DPLL_SEL); in ironlake_crtc_disable()
3443 I915_WRITE(PCH_DPLL_SEL, temp); in ironlake_crtc_disable()
5910 tmp = I915_READ(PCH_DPLL_SEL); in ironlake_get_pipe_config()
H A Di915_reg.h4073 #define PCH_DPLL_SEL 0xc7000 macro