/illumos-gate/usr/src/uts/common/io/nxge/ |
H A D | nxge_zcp.c | 81 NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT0_REG, 0); in nxge_zcp_init() 84 NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT1_REG, 0); in nxge_zcp_init() 87 NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT2_REG, 0); in nxge_zcp_init() 90 NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT3_REG, 0); in nxge_zcp_init() 244 NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT0_REG, 0); in nxge_zcp_handle_sys_errors() 247 NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT1_REG, 0); in nxge_zcp_handle_sys_errors() 250 NXGE_REG_WR64(handle, ZCP_CFIFO_ECC_PORT2_REG, 0); in nxge_zcp_handle_sys_errors() 289 NXGE_REG_WR64(nxgep->npi_handle, in nxge_zcp_inject_err() 297 NXGE_REG_WR64(nxgep->npi_handle, in nxge_zcp_inject_err() 305 NXGE_REG_WR64(nxgep->npi_handle, in nxge_zcp_inject_err() [all …]
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H A D | nxge_txc.c | 564 NXGE_REG_WR64(nxgep->npi_handle, TXC_INT_STAT_DBG_REG, in nxge_txc_inject_err()
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H A D | nxge_rxdma.c | 1827 NXGE_REG_WR64(handle, in nxge_rx_intr() 1889 NXGE_REG_WR64(handle, in nxge_rx_intr() 1909 NXGE_REG_WR64(handle, in nxge_rx_intr() 2831 NXGE_REG_WR64(handle, in nxge_disable_poll() 4850 NXGE_REG_WR64(nxgep->npi_handle, in nxge_rxdma_inject_err()
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H A D | nxge_intr.c | 1100 NXGE_REG_WR64(nxge->npi_handle, offset, mgm.value); in nxge_hio_ldgimgn()
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/illumos-gate/usr/src/uts/common/io/nxge/npi/ |
H A D | npi_zcp.c | 73 NXGE_REG_WR64(handle, ZCP_CONFIG_REG, val); in npi_zcp_config() 99 NXGE_REG_WR64(handle, ZCP_CONFIG_REG, val); in npi_zcp_config() 134 NXGE_REG_WR64(handle, ZCP_INT_MASK_REG, val); in npi_zcp_iconfig() 147 NXGE_REG_WR64(handle, ZCP_INT_MASK_REG, val); in npi_zcp_iconfig() 178 NXGE_REG_WR64(handle, ZCP_INT_STAT_REG, val); in npi_zcp_clear_istatus() 201 NXGE_REG_WR64(handle, ZCP_CONFIG_REG, val); in npi_zcp_set_dma_thresh() 264 NXGE_REG_WR64(handle, ZCP_DST4_RE_CTL_REG, val); in npi_zcp_set_dst_region() 267 NXGE_REG_WR64(handle, ZCP_DST8_RE_CTL_REG, val); in npi_zcp_set_dst_region() 660 NXGE_REG_WR64(handle, offset, cfifo_reg.value); in npi_zcp_rest_cfifo_port() 672 NXGE_REG_WR64(handle, offset, cfifo_reg.value); in npi_zcp_rest_cfifo_all() [all …]
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H A D | npi_vir.c | 303 NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); in npi_dev_func_sr_init() 305 NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); in npi_dev_func_sr_init() 362 NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); in npi_dev_func_sr_lock_enter() 474 NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); in npi_dev_func_sr_funcid_get() 508 NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); in npi_dev_func_sr_sr_raw_get() 548 NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); in npi_dev_func_sr_sr_get() 590 NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); in npi_dev_func_sr_sr_get_set_clear() 620 NXGE_REG_WR64(handle, DEV_FUNC_SR_REG, sr.value); in npi_dev_func_sr_sr_set_only() 798 NXGE_REG_WR64(handle, DMA_BIND_REG + in npi_fzc_dma_bind_set() 1509 NXGE_REG_WR64(handle, SYS_ERR_MASK_REG, mask); in npi_fzc_sys_err_mask_set() [all …]
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H A D | npi_rxdma.c | 353 NXGE_REG_WR64(handle, offset, page_hdl.value); in npi_rxdma_cfg_logical_page_handle() 519 NXGE_REG_WR64(handle, offset, cfg.value); in npi_rxdma_cfg_default_port_rdc() 883 NXGE_REG_WR64(handle, offset, cnt->value); in npi_rxdma_red_discard_stat_get() 928 NXGE_REG_WR64(handle, offset, cnt.value); in npi_rxdma_red_discard_oflow_clear() 1208 NXGE_REG_WR64(handle, d0_offset, d0.value); in npi_rxdma_rdmc_memory_io() 1209 NXGE_REG_WR64(handle, d1_offset, d1.value); in npi_rxdma_rdmc_memory_io() 1210 NXGE_REG_WR64(handle, d2_offset, d2.value); in npi_rxdma_rdmc_memory_io() 1211 NXGE_REG_WR64(handle, d3_offset, d3.value); in npi_rxdma_rdmc_memory_io() 1212 NXGE_REG_WR64(handle, d4_offset, d4.value); in npi_rxdma_rdmc_memory_io() 1305 NXGE_REG_WR64(handle, offset, md_reg.value); in npi_rxdma_cfg_32bitmode_enable() [all …]
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H A D | npi_txc.c | 399 NXGE_REG_WR64(handle, TXC_CONTROL_REG, in npi_txc_control() 435 NXGE_REG_WR64(handle, TXC_CONTROL_REG, val | cntl.value); in npi_txc_global_enable() 462 NXGE_REG_WR64(handle, TXC_CONTROL_REG, val | cntl.value); in npi_txc_global_disable() 483 NXGE_REG_WR64(handle, TXC_PORT_CTL_REG, TXC_PORT_CNTL_CLEAR); in npi_txc_control_clear() 504 NXGE_REG_WR64(handle, TXC_TRAINING_REG, (uint64_t)vector); in npi_txc_training_set() 556 NXGE_REG_WR64(handle, TXC_CONTROL_REG, val | (1 << port)); in npi_txc_port_enable() 583 NXGE_REG_WR64(handle, TXC_CONTROL_REG, (val & ~(1 << port))); in npi_txc_port_disable() 731 NXGE_REG_WR64(handle, TXC_MAX_REORDER_REG, val); in npi_txc_reorder_set() 1034 NXGE_REG_WR64(handle, TXC_INT_STAT_REG, istatus); in npi_txc_global_istatus_clear() 1063 NXGE_REG_WR64(handle, TXC_INT_MASK_REG, val); in npi_txc_global_imask_set()
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H A D | npi_mac.h | 278 NXGE_REG_WR64(handle, XMAC_REG_ADDR((portn), (reg)), (val)) 284 NXGE_REG_WR64(handle, BMAC_REG_ADDR((portn), (reg)), (val)) 290 NXGE_REG_WR64(handle, PCS_REG_ADDR((portn), (reg)), (val)) 296 NXGE_REG_WR64(handle, XPCS_ADDR((portn), (reg)), (val)) 302 NXGE_REG_WR64(handle, MIF_ADDR((reg)), (val)) 328 NXGE_REG_WR64(handle, ESR_ADDR((reg)), (val))
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H A D | npi_espc.c | 35 NXGE_REG_WR64(handle, ESPC_REG_ADDR(ESPC_PIO_EN_REG), 0x1); in npi_espc_pio_enable() 42 NXGE_REG_WR64(handle, ESPC_REG_ADDR(ESPC_PIO_EN_REG), 0); in npi_espc_pio_disable() 64 NXGE_REG_WR64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG), val); in npi_espc_eeprom_entry() 76 NXGE_REG_WR64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG), val); in npi_espc_eeprom_entry() 90 NXGE_REG_WR64(handle, ESPC_REG_ADDR(ESPC_PIO_STATUS_REG), val); in npi_espc_eeprom_entry()
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H A D | npi_txc.h | 70 NXGE_REG_WR64(handle, \ 78 NXGE_REG_WR64(handle, \
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H A D | npi_txdma.c | 262 NXGE_REG_WR64(handle, TX_ADDR_MD_REG, mode32.value); in npi_txdma_mode32_set() 1610 NXGE_REG_WR64(handle, offset, 0); in npi_txdma_desc_set_zero() 1826 NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, 0); in npi_txdma_inj_par_error_clear() 1838 NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, inj.value); in npi_txdma_inj_par_error_set() 1851 NXGE_REG_WR64(handle, TDMC_INJ_PAR_ERR_REG, inj.value); in npi_txdma_inj_par_error_update() 1876 NXGE_REG_WR64(handle, TDMC_DBG_SEL_REG, dbg.value); in npi_txdma_dbg_sel_set() 1889 NXGE_REG_WR64(handle, TDMC_TRAINING_REG, vec.value); in npi_txdma_training_vector_set()
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H A D | npi_ipp.h | 126 NXGE_REG_WR64(handle, IPP_REG_ADDR(portn, reg), val);\
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H A D | npi_txdma.h | 136 NXGE_REG_WR64(handle, NXGE_TXLOG_OFFSET(reg, channel), data)
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/illumos-gate/usr/src/uts/common/sys/nxge/ |
H A D | nxge_common_impl.h | 335 #define NXGE_REG_WR64(handle, offset, val) {\ macro 345 #define NXGE_REG_WR64(handle, offset, val) {\ macro 350 #define NXGE_REG_WR64(handle, offset, val) {\ macro
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H A D | nxge_fflp_hw.h | 1096 NXGE_REG_WR64((handle), (offset), (value))
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