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Searched refs:MI_SEMAPHORE_SYNC_RVE (Results 1 – 2 of 2) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Dintel_ringbuffer.c1794 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE; in intel_init_render_ring_buffer()
H A Di915_reg.h357 #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */ macro