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Searched refs:MI_FLUSH (Results 1 – 4 of 4) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Dintel_ringbuffer.c66 cmd = MI_FLUSH; in gen2_render_ring_flush()
121 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; in gen4_render_ring_flush()
998 intel_ring_emit(ring, MI_FLUSH); in bsd_ring_flush()
1182 intel_ring_emit(ring, MI_FLUSH); in i830_dispatch_execbuffer()
H A Di915_dma.c533 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP); in i915_dispatch_batchbuffer()
564 OUT_RING(MI_FLUSH | MI_READ_FLUSH); in i915_dispatch_flip()
H A Di915_reg.h278 #define MI_FLUSH MI_INSTR(0x04, 0) macro
H A Dintel_pm.c3725 intel_ring_emit(ring, MI_FLUSH); in ironlake_enable_rc6()