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Searched refs:MAX_TAD_DRAM_RULE (Results 1 – 3 of 3) sorted by relevance

/illumos-gate/usr/src/uts/intel/io/intel_nhm/
H A Dmem_addr.h61 extern tad_t tad[MAX_CPU_NODES][MAX_TAD_DRAM_RULE];
63 [MAX_TAD_DRAM_RULE];
65 [MAX_TAD_DRAM_RULE];
H A Dmem_addr.c43 tad_t tad[MAX_CPU_NODES][MAX_TAD_DRAM_RULE];
45 [MAX_TAD_DRAM_RULE];
47 [MAX_TAD_DRAM_RULE];
196 for (i = 0; i < MAX_TAD_DRAM_RULE; i++) { in address_to_channel()
297 for (i = 0; i < MAX_TAD_DRAM_RULE; i++) { in channel_addr_to_dimm()
430 for (i = 0; i < MAX_TAD_DRAM_RULE && found == 0; i++) { in dimm_to_addr()
473 for (i = 0; i < MAX_TAD_DRAM_RULE; i++) { in dimm_to_addr()
947 for (j = 0; j < MAX_TAD_DRAM_RULE; j++) { in mem_reg_init()
972 for (k = 0; k < MAX_TAD_DRAM_RULE; k++) { in mem_reg_init()
H A Dintel_nhm.h253 #define MAX_TAD_DRAM_RULE 8 macro