1 /*
2  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
3  * Use is subject to license terms.
4  */
5 
6 #ifndef AMD8111S_HW_H
7 #define	AMD8111S_HW_H
8 
9 /*
10  * Copyright (c) 2001-2006 Advanced Micro Devices, Inc.  All rights reserved.
11  *
12  * Redistribution and use in source and binary forms, with or without
13  * modification, are permitted provided that the following conditions are met:
14  *
15  * + Redistributions of source code must retain the above copyright notice,
16  * + this list of conditions and the following disclaimer.
17  *
18  * + Redistributions in binary form must reproduce the above copyright
19  * + notice, this list of conditions and the following disclaimer in the
20  * + documentation and/or other materials provided with the distribution.
21  *
22  * + Neither the name of Advanced Micro Devices, Inc. nor the names of its
23  * + contributors may be used to endorse or promote products derived from
24  * + this software without specific prior written permission.
25  *
26  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
27  * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
28  * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
29  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
30  * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. OR
31  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
33  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
34  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
36  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
37  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
38  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39  *
40  * Import/Export/Re-Export/Use/Release/Transfer Restrictions and
41  * Compliance with Applicable Laws.  Notice is hereby given that
42  * the software may be subject to restrictions on use, release,
43  * transfer, importation, exportation and/or re-exportation under
44  * the laws and regulations of the United States or other
45  * countries ("Applicable Laws"), which include but are not
46  * limited to U.S. export control laws such as the Export
47  * Administration Regulations and national security controls as
48  * defined thereunder, as well as State Department controls under
49  * the U.S. Munitions List.  Permission to use and/or
50  * redistribute the software is conditioned upon compliance with
51  * all Applicable Laws, including U.S. export control laws
52  * regarding specifically designated persons, countries and
53  * nationals of countries subject to national security controls.
54  */
55 
56 
57 /* Definitions for the type of Memory allocations needed */
58 
59 #define	ETH_LENGTH_OF_ADDRESS		6
60 #define	ETH_MAC_HDR_SIZE		14
61 
62 
63 #define	ADD_MULTICAST			1
64 
65 #define	ENABLE_MULTICAST		2
66 #define	DISABLE_MULTICAST		3
67 
68 #define	ENABLE_ALL_MULTICAST		4
69 #define	DISABLE_ALL_MULTICAST		5
70 
71 #define	ENABLE_BROADCAST		6
72 #define	DISABLE_BROADCAST		7
73 
74 #define	ADD_WAKE_UP_PATTERN		8
75 #define	REMOVE_WAKE_UP_PATTERN		9
76 #define	ENABLE_MAGIC_PACKET_WAKE_UP	10
77 
78 #define	SET_SINGLE_MULTICAST		11
79 #define	UNSET_SINGLE_MULTICAST		12
80 #define	DELETE_MULTICAST		13
81 
82 #define	LINK_DOWN		1
83 #define	LINK_UP			2
84 #define	LINK_UNKNOWN		3
85 
86 /* Setting the MODE */
87 #define	PROMISCOUS	1
88 #define	DISABLE_PROM	2
89 
90 #define	VIRTUAL		1
91 
92 #define	ALIGNMENT	0x0f
93 
94 #define	TX_RING_LEN_BITS		10	/* 1024 descriptors */
95 #define	RX_RING_LEN_BITS		10	/* 1024 descriptors */
96 #define	TX_BUF_SIZE			2048
97 #define	RX_BUF_SIZE			2048
98 
99 #define	TX_RING_SIZE			(1 << (TX_RING_LEN_BITS))
100 #define	TX_COALESC_SIZE			(1 << 11)
101 #define	TX_RING_MOD_MASK		(2 * TX_RING_SIZE - 1)
102 
103 #define	TX_RESCHEDULE_THRESHOLD		(TX_RING_SIZE >> 1)
104 
105 #define	RX_RING_SIZE			(1 << (RX_RING_LEN_BITS))
106 #define	RX_RING_MOD_MASK		(RX_RING_SIZE - 1)
107 
108 #define	MAX_MULTICAST_ADDRESSES		32
109 #define	JUMBO_ENABLED			0
110 #define	JUMBO_DISABLED			1
111 
112 /* Default value of IPG convergence time */
113 #define	MIN_IPG_DEFAULT			96
114 #define	MAX_IPG_DEFAULT			255
115 #define	MAX_BUFFER_COUNT		8 /* full coalesce */
116 
117 #define	ULONG unsigned long
118 #define	UCHAR unsigned char
119 
120 /* Generic MII registers. */
121 #define	MII_BMCR	0x00	/* Basic mode control register */
122 #define	MII_BMSR	0x01	/* Basic mode status register */
123 #define	MII_PHYSID1	0x02	/* PHYS ID 1 */
124 #define	MII_PHYSID2	0x03	/* PHYS ID 2 */
125 #define	MII_ADVERTISE	0x04	/* Advertisement control reg */
126 #define	MII_LPA		0x05	/* Link partner ability reg */
127 #define	MII_EXPANSION	0x06	/* Expansion register */
128 #define	MII_DCOUNTER	0x12	/* Disconnect counter */
129 #define	MII_FCSCOUNTER	0x13	/* False carrier counter */
130 #define	MII_NWAYTEST	0x14	/* N-way auto-neg test reg */
131 #define	MII_RERRCOUNTER	0x15	/* Receive error counter */
132 #define	MII_SREVISION	0x16	/* Silicon revision */
133 #define	MII_RESV1	0x17	/* Reserved... */
134 #define	MII_LBRERROR	0x18	/* Lpback, rx, bypass error */
135 #define	MII_PHYADDR	0x19	/* PHY address */
136 #define	MII_RESV2	0x1a	/* Reserved... */
137 #define	MII_TPISTATUS	0x1b	/* TPI status for 10mbps */
138 #define	MII_NCONFIG	0x1c	/* Network interface config */
139 
140 
141 #define	DEVICE_ID 0x744b
142 #define	VENDOR_ID 0x1022
143 
144 /* L4 Chip Name  */
145 #define	DEVICE_CHIPNAME			"Memory_Map_L7 AMDIDC"
146 
147 /* Error Status Registers */
148 #define	MIB_OFFSET		0x28
149 
150 /*
151  *	MIB counter definitions
152  */
153 #define	RcvMissPkts		0x00
154 #define	RcvOctets		0x01
155 #define	RcvBroadCastPkts	0x02
156 #define	RcvMultiCastPkts	0x03
157 #define	RcvUndersizePkts	0x04
158 #define	RcvOversizePkts		0x05
159 #define	RcvFragments		0x06
160 #define	RcvJabbers		0x07
161 #define	RcvUniCastPkts		0x08
162 #define	RcvAlignmentErrors	0x09
163 #define	RcvFCSErrors		0x0a
164 #define	RcvGoodOctets		0x0b
165 #define	RcvMACCtrl		0x0c
166 #define	RcvFlowCtrl		0x0d
167 #define	RcvPkts64Octets		0x0e
168 #define	RcvPkts65to127Octets	0x0f
169 #define	RcvPkts128to255Octets	0x10
170 #define	RcvPkts256to511Octets	0x11
171 #define	RcvPkts512to1023Octets	0x12
172 #define	RcvPkts1024to1518Octets	0x13
173 #define	RcvUnsupportedOpcode	0x14
174 #define	RcvSymbolErrors		0x15
175 #define	RcvDropPktsRing0	0x16
176 
177 #define	XmtUnderrunPkts		0x20
178 #define	XmtOctets		0x21
179 #define	XmtPackets		0x22
180 #define	XmtBroadCastPkts	0x23
181 #define	XmtMultiCastPkts	0x24
182 #define	XmtCollisions		0x25
183 #define	XmtUniCastPkts		0x26
184 #define	XmtOneCollision		0x27
185 #define	XmtMultipleCollision	0x28
186 #define	XmtDeferredTransmit	0x29
187 #define	XmtLateCollision	0x2a
188 #define	XmtExcessiveDefer	0x2b
189 #define	XmtLossCarrier		0x2c
190 #define	XmtExcessiveCollision	0x2d
191 #define	XmtBackPressure		0x2e
192 #define	XmtFlowCtrl		0x2f
193 #define	XmtPkts64Octets		0x30
194 #define	XmtPkts65to127Octets	0x31
195 #define	XmtPkts128to255Octets	0x32
196 #define	XmtPkts256to511Octets	0x33
197 #define	XmtPkts512to1023Octets	0x34
198 #define	XmtPkts1024to1518Octets	0x35
199 #define	XmtOversizePkts		0x36
200 
201 /* Link Status  */
202 #define	SPEED_MASK		0x0380	/* B9 .. B7 */
203 #define	SPEED_100Mbps		0x0180
204 #define	SPEED_10Mbps		0x0100
205 
206 
207 /* PMR (Pattern Match RAM) */
208 #define	MAX_ALLOWED_PATTERNS	8
209 #define	MAX_PATTERNS		1024
210 #define	ALL_MULTI		B16_MASK
211 #define	ONLY_MULTI		B15_MASK
212 
213 #define	B31_MASK	0x80000000
214 #define	B30_MASK	0x40000000
215 #define	B29_MASK	0x20000000
216 #define	B28_MASK	0x10000000
217 #define	B27_MASK	0x08000000
218 #define	B26_MASK	0x04000000
219 #define	B25_MASK	0x02000000
220 #define	B24_MASK	0x01000000
221 #define	B23_MASK	0x00800000
222 #define	B22_MASK	0x00400000
223 #define	B21_MASK	0x00200000
224 #define	B20_MASK	0x00100000
225 #define	B19_MASK	0x00080000
226 #define	B18_MASK	0x00040000
227 #define	B17_MASK	0x00020000
228 #define	B16_MASK	0x00010000
229 
230 #define	B15_MASK	0x8000
231 #define	B14_MASK	0x4000
232 #define	B13_MASK	0x2000
233 #define	B12_MASK	0x1000
234 #define	B11_MASK	0x0800
235 #define	B10_MASK	0x0400
236 #define	B9_MASK		0x0200
237 #define	B8_MASK		0x0100
238 #define	B7_MASK		0x0080
239 #define	B6_MASK		0x0040
240 #define	B5_MASK		0x0020
241 #define	B4_MASK		0x0010
242 #define	B3_MASK		0x0008
243 #define	B2_MASK		0x0004
244 #define	B1_MASK		0x0002
245 #define	B0_MASK		0x0001
246 
247 /* PCI register offset */
248 /* required by odl in getting the Memory Base Address */
249 #define	MEMBASE_MASK		0xFFFFF000
250 #define	PCI_CAP_ID_REG_OFFSET	0x34
251 #define	PCI_PMC_REG_OFFSET	0x36
252 #define	PCI_PMCSR_REG_OFFSET	0x38
253 #define	MIB_OFFSET		0x28
254 #define	STAT_ASF		0x00	/* 32bit register */
255 
256 #define	FORCED_PHY_MASK		0xFF07
257 
258 /* Offset of Drifrent Registers */
259 #define	AP_VALUE		0x98	/* 32bit register */
260 #define	AUTOPOLL0		0x88	/* 16bit register */
261 #define	AUTOPOLL1		0x8A	/* 16bit register */
262 #define	AUTOPOLL2		0x8C	/* 16bit register */
263 #define	AUTOPOLL3		0x8E	/* 16bit register */
264 #define	AUTOPOLL4		0x90	/* 16bit register */
265 #define	AUTOPOLL5		0x92	/* 16bit register */
266 /* Receive Ring Base Address Registers . */
267 #define	RCV_RING_BASE_ADDR0	0x120	/* 64bit register */
268 /* Transmit Ring Base Address */
269 #define	XMT_RING_BASE_ADDR0	0x100	/* 64bit register */
270 #define	XMT_RING_BASE_ADDR1	0x108	/* 64bit register */
271 #define	XMT_RING_BASE_ADDR2	0x110	/* 64bit register */
272 #define	XMT_RING_BASE_ADDR3	0x118	/* 64bit register */
273 /* CAM ADDRESS */
274 #define	CAM_ADDR		0x1A0	/* 16bit register */
275 #define	CAM_DATA		0x198	/* 64bit register */
276 /* CHIP ID */
277 #define	CHIPID			0x004	/* 32bit register */
278 /* COMMAND STYLE REGISTERS */
279 #define	CMD0			0x48	/* 32bit register */
280 #define	CMD2			0x50	/* 32bit register */
281 #define	CMD3			0x54	/* 32bit register */
282 #define	CMD7			0x64	/* 32bit register */
283 /* CONTRIOL REGISTER */
284 #define	CTRL1 			0x6C	/* 32bit register */
285 #define	CTRL2 			0x70	/* 32bit register */
286 /* DELAY INTERRUPT REGISTER */
287 #define	DLY_INT_A		0xA8	/* 32bit register */
288 #define	DLY_INT_B		0xAC	/* 32bit register */
289 /* FLOW CONTROL REGISTER */
290 #define	FLOW_CONTROL		0xC8	/* 32bit register */
291 /* INTER FRAME SPACING */
292 #define	IFS			0x18E	/* 16bit register */
293 #define	IFS1			0x18C	/* 8bit register */
294 /* INTERRUPT REGISTER */
295 #define	INT0			0x38	/* 32bit register */
296 #define	INTEN0			0x40	/* 32bit register */
297 /* LOGICAL ADDRESS */
298 #define	LADRF1			0x168	/* 64bit register */
299 /* MIB ADDRESS REGISTER */
300 #define	MIB_ADDR		0x14	/* 16bit register */
301 #define	MIB_DATA		0x10	/* 32bit register */
302 /* MAC ADDRESS */
303 #define	PADR			0x160	/* 48bit register */
304 /* PHY ADDRESS */
305 #define	PHY_ACCESS		0xD0	/* 32bit register */
306 /* PATTERN REGISTER */
307 #define	PMAT0			0x190	/* 32bit register */
308 #define	PMAT1			0x194	/* 32bit register */
309 /* RECEIVE RING LENGTH OFFSET */
310 #define	RCV_RING_LEN0		0x150	/* 16bit register */
311 /* SRAM BOUNDARY */
312 #define	SRAM_BOUNDARY		0x17A	/* 16bit register */
313 #define	SRAM_SIZE		0x178	/* 16bit register */
314 /* STATUS REGISTER */
315 #define	STAT0			0x30	/* 32bit register */
316 #define	STVAL			0xD8	/* 32bit register */
317 #define	TEST0			0x1A8	/* 32bit register */
318 #define	XMT_RING_LEN0		0x140	/* 16bit register */
319 #define	XMT_RING_LEN1		0x144	/* 16bit register */
320 #define	XMT_RING_LEN2		0x148	/* 16bit register */
321 #define	XMT_RING_LEN3		0x14C	/* 16bit register */
322 #define	XMT_RING_LIMIT		0x7C	/* 32bit register */
323 
324 
325 
326 #define	RCV_RING_LEN1		0x154	/* 16bit register */
327 #define	RCV_RING_LEN2		0x158	/* 16bit register */
328 #define	RCV_RING_LEN3		0x15C	/* 16bit register */
329 #define	FFC_THRESH		0xCC	/* 32bit register */
330 #define	RCV_RING_BASE_ADDR1	0x128	/* 64bit register */
331 #define	RCV_RING_BASE_ADDR2	0x130	/* 64bit register */
332 #define	RCV_RING_BASE_ADDR3	0x138	/* 64bit register */
333 #define	RCV_RING_CFG		0x78	/* 16bit register */
334 #define	PCS_ANEG		0x9C	/* 32bit register */
335 #define	PCS_RCFG		0xA0	/* 32bit register */
336 #define	PCS_XCFG		0xA4	/* 32bit register */
337 #define	DFC_INDEX2		0xB8	/* 16bit register */
338 #define	DFC_INDEX3		0xBA	/* 16bit register */
339 #define	DFC_INDEX0		0xBC	/* 16bit register */
340 #define	DFC_INDEX1		0xBE	/* 16bit register */
341 #define	DFC_THRESH2		0xC0	/* 16bit register */
342 #define	DFC_THRESH3		0xC2	/* 16bit register */
343 #define	DFC_THRESH0		0xC4	/* 16bit register */
344 #define	DFC_THRESH1		0xC6	/* 16bit register */
345 #define	PAUSE_CNT		0xDE	/* 32bit register */
346 #define	LED0			0xE0	/* 16bit register */
347 #define	LED1			0xE2	/* 16bit register */
348 #define	LED2			0xE4	/* 16bit register */
349 #define	LED3			0xE6	/* 16bit register */
350 
351 
352 #define	EEPROM_ACC		0x17C	/* 16bit register */
353 
354 
355 /* Register Bit Definitions */
356 /* STAT_ASF			0x00, 32bit register */
357 #define	ASF_INIT_DONE		B1_MASK
358 #define	ASF_INIT_PRESENT	B0_MASK
359 
360 /* MIB_ADDR			0x14, 16bit register */
361 #define	MIB_CMD_ACTIVE		B15_MASK
362 #define	MIB_RD_CMD		B13_MASK
363 #define	MIB_CLEAR		B12_MASK
364 #define	MIB_ADDRESS		0x0000003F	/* 5:0 */
365 
366 /* QOS_ADDR			0x1C, 16bit register */
367 #define	QOS_CMD_ACTIVE		B15_MASK
368 #define	QOS_WR_CMD		B14_MASK
369 #define	QOS_RD_CMD		B13_MASK
370 #define	QOS_ADDRESS		0x0000001F	/* 4:0 */
371 
372 /* STAT0			0x30, 32bit register */
373 #define	PAUSE_PEND		B14_MASK
374 #define	PAUSING			B13_MASK
375 #define	PMAT_DET		B12_MASK
376 #define	MP_DET			B11_MASK
377 #define	LC_DET			B10_MASK
378 #define	SPEED_MASK		0x0380		/* 9:7 */
379 #define	FULL_DPLX		B6_MASK
380 #define	LINK_STAT		B5_MASK
381 #define	AUTONEG_COMPLETE	B4_MASK
382 /* #define	MIIPD			B3_MASK */
383 #define	RX_SUSPENDED		B2_MASK
384 #define	TX_SUSPENDED		B1_MASK
385 #define	RUNNING			B0_MASK
386 
387 
388 /* INTEN0			0x40, 32bit register */
389 
390 #define	VAL3			B31_MASK
391 #define	VAL2			B23_MASK
392 #define	VAL1			B15_MASK
393 #define	VAL0			B7_MASK
394 
395 /* VAL3 */
396 #define	PSCINTEN		B28_MASK
397 #define	LCINTEN			B27_MASK
398 #define	APINT5EN		B26_MASK
399 #define	APINT4EN		B25_MASK
400 #define	APINT3EN		B24_MASK
401 
402 /* VAL2 */
403 #define	APINT2EN		B22_MASK
404 #define	APINT1EN		B21_MASK
405 #define	APINT0EN		B20_MASK
406 #define	MIIPDTINTEN		B19_MASK
407 #define	MCCIINTEN		B18_MASK
408 #define	MCCINTEN		B17_MASK
409 #define	MREINTEN		B16_MASK
410 
411 /* VAL1 */
412 #define	SPNDINTEN		B14_MASK
413 #define	MPINTEN			B13_MASK
414 #define	SINTEN			B12_MASK
415 #define	TINTEN3			B11_MASK
416 #define	TINTEN2			B10_MASK
417 #define	TINTEN1			B9_MASK
418 #define	TINTEN0			B8_MASK
419 
420 /* VAL0 */
421 #define	STINTEN			B4_MASK
422 #define	RINTEN3			B3_MASK
423 #define	RINTEN2			B2_MASK
424 #define	RINTEN1			B1_MASK
425 #define	RINTEN0			B0_MASK
426 
427 /* CMD0				0x48, 32bit register */
428 /* VAL2 */
429 #define	RDMD3			B19_MASK
430 #define	RDMD2			B18_MASK
431 #define	RDMD1			B17_MASK
432 #define	RDMD0			B16_MASK
433 
434 /* VAL1 */
435 #define	TDMD3			B11_MASK
436 #define	TDMD2			B10_MASK
437 #define	TDMD1			B9_MASK
438 #define	TDMD0			B8_MASK
439 
440 /* VAL0 */
441 #define	UINTCMD			B6_MASK
442 #define	RX_FAST_SPND		B5_MASK
443 #define	TX_FAST_SPND		B4_MASK
444 #define	RX_SPND			B3_MASK
445 #define	TX_SPND			B2_MASK
446 #define	INTREN			B1_MASK
447 #define	RUN			B0_MASK
448 
449 /* CMD2 			0x50, 32bit register */
450 /* VAL3 */
451 #define	CONDUIT_MODE		B29_MASK
452 #define	PREF_QTAG		B28_MASK
453 #define	ALT_PRI_OK		B27_MASK
454 
455 /* VAL2 */
456 #define	CAM_ENABLE		B22_MASK
457 #define	QOS_ENABLE		B21_MASK
458 #define	HASH_ENABLE		B20_MASK
459 #define	RPA			B19_MASK
460 #define	DRCVPA			B18_MASK
461 #define	DRCVBC			B17_MASK
462 #define	PROM			B16_MASK
463 
464 /* VAL1 */
465 #define	ASTRIP_RCV		B13_MASK
466 #define	CMD2_RCV_DROP0			B12_MASK
467 #define	EMBA			B11_MASK
468 #define	DXMT2PD			B10_MASK
469 #define	LTINTEN			B9_MASK
470 #define	DXMTFCS			B8_MASK
471 
472 /* VAL0 */
473 #define	APAD_XMT		B6_MASK
474 #define	DRTY			B5_MASK
475 #define	INLOOP			B4_MASK
476 #define	EXLOOP			B3_MASK
477 #define	REX_RTRY		B2_MASK
478 #define	REX_UFLO		B1_MASK
479 #define	REX_LCOL		B0_MASK
480 
481 /* CMD3				0x54, 32bit register */
482 
483 /* VAL3 */
484 #define	ASF_INIT_DONE_ALIAS	B29_MASK
485 
486 /* VAL2 */
487 #define	JUMBO			B21_MASK
488 #define	VSIZE			B20_MASK
489 #define	VLONLY			B19_MASK
490 #define	VL_TAG_DEL		B18_MASK
491 
492 /* VAL1 */
493 #define	EN_PMGR			B14_MASK
494 #define	INTLEVEL		B13_MASK
495 #define	FORCE_FULL_DUPLEX	B12_MASK
496 #define	FORCE_LINK_STATUS	B11_MASK
497 #define	APEP			B10_MASK
498 #define	MPPLBA			B9_MASK
499 
500 /* VAL0 */
501 #define	RESET_PHY_PULSE		B2_MASK
502 #define	RESET_PHY		B1_MASK
503 #define	PHY_RST_POL		B0_MASK
504 
505 /* CMD7				0x64, 32bit register */
506 /* VAL0 */
507 #define	PMAT_SAVE_MATCH		B4_MASK
508 #define	PMAT_MODE		B3_MASK
509 #define	MPEN_SW			B1_MASK
510 #define	LCMODE_SW		B0_MASK
511 
512 /* CTRL0			0x68, 32bit register */
513 #define	PHY_SEL			0x03000000	/* 25:24 */
514 #define	RESET_PHY_WIDTH		0x00FF0000	/* 23:16 */
515 #define	BSWP_REGS		B10_MASK
516 #define	BSWP_DESC		B9_MASK
517 #define	BSWP_DATA		B8_MASK
518 #define	CACHE_ALIGN		B4_MASK
519 #define	BURST_LIMIT		0x0000000F	/* 3:0 */
520 
521 /* CTRL1			0x6C, 32bit register */
522 #define	SLOTMOD_MASK		0x03000000	/* 25:24 */
523 #define	XMTSP_MASK		0x300		/* 17:16 */
524 #define	XMTSP_128		0x200
525 #define	XMTSP_64		0x100
526 
527 /* CTRL2			0x70, 32bit register */
528 #define	FS_MASK			0x00070000	/* 18:16 */
529 #define	FMDC_MASK		0x00000300	/* 9:8 */
530 #define	XPHYRST			B7_MASK
531 #define	XPHYANE			B6_MASK
532 #define	XPHYFD			B5_MASK
533 #define	XPHYSP_100		B3_MASK		/* 4:3, 100 Mbps */
534 #define	APDW_MASK		0x00000007	/* 2:0 */
535 
536 /* RCV_RING_CFG			0x78, 16bit register */
537 #define	RCV_DROP3		B11_MASK
538 #define	RCV_DROP2		B10_MASK
539 #define	RCV_DROP1		B9_MASK
540 #define	RCV_DROP0		B8_MASK
541 #define	RCV_RING_DEFAULT	0x0030		/* 5:4 */
542 #define	RCV_RING3_EN		B3_MASK
543 #define	RCV_RING2_EN		B2_MASK
544 #define	RCV_RING1_EN		B1_MASK
545 #define	RCV_RING0_EN		B0_MASK
546 
547 /* XMT_RING_LIMIT		0x7C, 32bit register */
548 #define	XMT_RING2_LIMIT		0x00FF0000	/* 23:16 */
549 #define	XMT_RING1_LIMIT		0x0000FF00	/* 15:8 */
550 #define	XMT_RING0_LIMIT		0x000000FF	/* 7:0 */
551 
552 /* AUTOPOLL0			0x88, 16bit register */
553 #define	AP_REG0_EN		B15_MASK
554 #define	AP_REG0_ADDR_MASK	0x1F00	/* 12:8 */
555 #define	AP_PHY0_ADDR_MASK	0x001F	/* 4:0 */
556 
557 /* AUTOPOLL1			0x8A, 16bit register */
558 #define	AP_REG1_EN		B15_MASK
559 #define	AP_REG1_ADDR_MASK	0x1F00	/* 12:8 */
560 #define	AP_PRE_SUP1		B6_MASK
561 #define	AP_PHY1_DFLT		B5_MASK
562 #define	AP_PHY1_ADDR_MASK	0x001F	/* 4:0 */
563 
564 /* AUTOPOLL2			0x8C, 16bit register */
565 #define	AP_REG2_EN		B15_MASK
566 #define	AP_REG2_ADDR_MASK	0x1F00	/* 12:8 */
567 #define	AP_PRE_SUP2		B6_MASK
568 #define	AP_PHY2_DFLT		B5_MASK
569 #define	AP_PHY2_ADDR_MASK	0x001F	/* 4:0 */
570 
571 /* AUTOPOLL3			0x8E, 16bit register */
572 #define	AP_REG3_EN		B15_MASK
573 #define	AP_REG3_ADDR_MASK	0x1F00	/* 12:8 */
574 #define	AP_PRE_SUP3		B6_MASK
575 #define	AP_PHY3_DFLT		B5_MASK
576 #define	AP_PHY3_ADDR_MASK	0x001F	/* 4:0 */
577 
578 /* AUTOPOLL4			0x90, 16bit register */
579 #define	AP_REG4_EN		B15_MASK
580 #define	AP_REG4_ADDR_MASK	0x1F00	/* 12:8 */
581 #define	AP_PRE_SUP4		B6_MASK
582 #define	AP_PHY4_DFLT		B5_MASK
583 #define	AP_PHY4_ADDR_MASK	0x001F	/* 4:0 */
584 
585 /* AUTOPOLL5			0x92, 16bit register */
586 #define	AP_REG5_EN		B15_MASK
587 #define	AP_REG5_ADDR_MASK	0x1F00	/* 12:8 */
588 #define	AP_PRE_SUP5		B6_MASK
589 #define	AP_PHY5_DFLT		B5_MASK
590 #define	AP_PHY5_ADDR_MASK	0x001F	/* 4:0 */
591 
592 /* AP_VALUE 			0x98, 32bit ragister */
593 #define	AP_VAL_ACTIVE		B31_MASK
594 #define	AP_VAL_RD_CMD		B29_MASK
595 #define	AP_ADDR			0x00070000	/* 18:16 */
596 #define	AP_VAL			0x0000FFFF	/* 15:0 */
597 
598 /* PCS_ANEG			0x9C, 32bit register */
599 #define	SYNC_LOST		B10_MASK
600 #define	IMATCH			B9_MASK
601 #define	CMATCH			B8_MASK
602 #define	PCS_AN_IDLE		B1_MASK
603 #define	PCS_AN_CFG		B0_MASK
604 
605 /* DLY_INT_A			0xA8, 32bit register */
606 #define	DLY_INT_A_R3		B31_MASK
607 #define	DLY_INT_A_R2		B30_MASK
608 #define	DLY_INT_A_R1		B29_MASK
609 #define	DLY_INT_A_R0		B28_MASK
610 #define	DLY_INT_A_T3		B27_MASK
611 #define	DLY_INT_A_T2		B26_MASK
612 #define	DLY_INT_A_T1		B25_MASK
613 #define	DLY_INT_A_T0		B24_MASK
614 #define	EVENT_COUNT_A		0x00FF0000	/* 20:16 */
615 #define	MAX_DELAY_TIME_A	0x000007FF	/* 10:0 */
616 
617 /* DLY_INT_B			0xAC, 32bit register */
618 #define	DLY_INT_B_R3		B31_MASK
619 #define	DLY_INT_B_R2		B30_MASK
620 #define	DLY_INT_B_R1		B29_MASK
621 #define	DLY_INT_B_R0		B28_MASK
622 #define	DLY_INT_B_T3		B27_MASK
623 #define	DLY_INT_B_T2		B26_MASK
624 #define	DLY_INT_B_T1		B25_MASK
625 #define	DLY_INT_B_T0		B24_MASK
626 #define	EVENT_COUNT_B		0x00FF0000	/* 20:16 */
627 #define	MAX_DELAY_TIME_B	0x000007FF	/* 10:0 */
628 
629 /* DFC_THRESH2			0xC0, 16bit register */
630 #define	DFC_THRESH2_HIGH	0xFF00		/* 15:8 */
631 #define	DFC_THRESH2_LOW		0x00FF		/* 7:0 */
632 
633 /* DFC_THRESH3			0xC2, 16bit register */
634 #define	DFC_THRESH3_HIGH	0xFF00		/* 15:8 */
635 #define	DFC_THRESH3_LOW		0x00FF		/* 7:0 */
636 
637 /* DFC_THRESH0			0xC4, 16bit register */
638 #define	DFC_THRESH0_HIGH	0xFF00		/* 15:8 */
639 #define	DFC_THRESH0_LOW		0x00FF		/* 7:0 */
640 
641 /* DFC_THRESH1			0xC6, 16bit register */
642 #define	DFC_THRESH1_HIGH	0xFF00		/* 15:8 */
643 #define	DFC_THRESH1_LOW		0x00FF		/* 7:0 */
644 
645 /* FLOW_CONTROL 		0xC8, 32bit register */
646 #define	PAUSE_LEN_CHG		B30_MASK
647 #define	FFC_EN			B28_MASK
648 #define	DFC_RING3_EN		B27_MASK
649 #define	DFC_RING2_EN		B26_MASK
650 #define	DFC_RING1_EN		B25_MASK
651 #define	DFC_RING0_EN		B24_MASK
652 #define	FIXP_CONGEST		B21_MASK
653 #define	NAPA			B20_MASK
654 #define	NPA			B19_MASK
655 #define	FIXP			B18_MASK
656 #define	FCPEN			B17_MASK
657 #define	FCCMD			B16_MASK
658 #define	PAUSE_LEN		0x0000FFFF	/* 15:0 */
659 
660 /* FFC THRESH			0xCC, 32bit register */
661 #define	FFC_HIGH		0xFFFF0000	/* 31:16 */
662 #define	FFC_LOW			0x0000FFFF	/* 15:0 */
663 
664 /* PHY_ACCESS			0xD0, 32bit register */
665 #define	PHY_CMD_ACTIVE		B31_MASK
666 #define	PHY_WR_CMD		B30_MASK
667 #define	PHY_RD_CMD		B29_MASK
668 #define	PHY_RD_ERR		B28_MASK
669 #define	PHY_PRE_SUP		B27_MASK
670 #define	PHY_ADDR		0x03E00000	/* 25:21 */
671 #define	PHY_REG_ADDR		0x001F0000	/* 20:16 */
672 #define	PHY_DATA		0x0000FFFF	/* 15:0 */
673 #define	PHY_ADDR_SHIFT		21
674 #define	PHY_REG_ADDR_SHIFT	16
675 
676 #define	PHY_MAX_RETRY		30
677 
678 
679 /* EEPROM_ACC			0x17C, 16bit register */
680 #define	PVALID			B15_MASK
681 #define	PREAD			B14_MASK
682 #define	EEDET			B13_MASK
683 #define	EEN			B4_MASK
684 #define	ECS			B2_MASK
685 #define	EESK			B1_MASK
686 #define	EDI_EDO			B0_MASK
687 
688 /* PMAT0			0x190,	 32bit register */
689 #define	PMR_ACTIVE		B31_MASK
690 #define	PMR_WR_CMD		B30_MASK
691 #define	PMR_RD_CMD		B29_MASK
692 #define	PMR_BANK		B28_MASK
693 #define	PMR_ADDR		0x007F0000	/* 22:16 */
694 #define	PMR_B4			0x000000FF	/* 15:0 */
695 
696 /* PMAT1			0x194,	 32bit register */
697 #define	PMR_B3			0xFF000000	/* 31:24 */
698 #define	PMR_B2			0x00FF0000	/* 23:16 */
699 #define	PMR_B1			0x0000FF00	/* 15:8 */
700 #define	PMR_B0			0x000000FF	/* 7:0 */
701 
702 /* CAMDATA			0x198, 16bit register */
703 #define	CAM_DATA_MASK		0x000000FFFFFFFFFFFF
704 
705 /* CAM_ADDR			0x1A0, 16bit register */
706 #define	CAM_CMD_ACTIVE		B15_MASK
707 #define	CAM_WR_CMD		B14_MASK
708 #define	CAM_RD_CMD		B13_MASK
709 #define	CAM_CLEAR		B12_MASK
710 #define	CAM_ADDRESS		0x001F
711 
712 /* INT0				0x38, 32bit register */
713 #define	INTR			B31_MASK
714 #define	LCINT			B27_MASK
715 #define	TINT0			B8_MASK
716 #define	STINT			B4_MASK
717 #define	RINT0			B0_MASK
718 
719 /* TEST0			0x1A8, 32bit register */
720 
721 /* VAL1 */
722 #define	MFSM_RESET		B10_MASK
723 #define	BFD_SCALE_DOWN		B9_MASK
724 
725 /* VAL0 */
726 #define	LEDCNTTST		B5_MASK
727 #define	RTYTST_RANGEN		B2_MASK
728 #define	RTYTST_SLOT		B1_MASK
729 #define	SERRLEVEL		B0_MASK
730 
731 #define	CABLE_CHK_TIME		100
732 
733 #define	PCI_IOMAP_BASE_REG	0x00
734 #define	PCI_MEM_BASE_REG	0x10
735 
736 #define	XPHYFD			B5_MASK
737 #define	XPHYSP			B3_MASK		/* 4:3 */
738 
739 #define	TX_RATE		0x1
740 #define	RX_RATE		0x2
741 #define	RX_BYTES	0xb
742 #define	TX_BYTES	0xc
743 
744 #define	LOW_COALESC	1
745 #define	MEDIUM_COALESC	2
746 #define	HIGH_COALESC	3
747 #define	NO_COALESC	4
748 
749 #define	CLIENT	0x1
750 #define	SERVER  0x2
751 #define	DISABLE 0x3
752 #define	PCI_OPT 0x4
753 
754 #define	MULTICAST_BITMAP_ARRAY_SIZE		64
755 
756 #define	PHY_AUTO_NEGOTIATION	0
757 #define	PHY_FORCE_HD_100	1	/* HD: Half Duplex */
758 #define	PHY_FORCE_FD_100	2	/* FD: Full Duplex */
759 #define	PHY_FORCE_HD_10		3
760 #define	PHY_FORCE_FD_10		4
761 
762 struct tx_desc {
763 	unsigned int Tx_BCNT	:16;	/* Buffer Byte Count */
764 	unsigned int Tx_RES4	:6;	/* RESVERD 6 bits */
765 	/*
766 	 * This bit causes the transmission of the corresponding frame to be
767 	 * aborted. If the transmitter has not started sending the frame at the
768 	 * time that the descriptor
769 	 */
770 	unsigned int KILL	:1;
771 	unsigned int Tx_RES3	:1;	/* RESVERD 1 bits */
772 	/* End Of packet to indicates the last Buffer */
773 	unsigned int Tx_EOP	:1;
774 	unsigned int Tx_SOP	:1;	/* Defer to Transmit */
775 	unsigned int Tx_RES2	:2;
776 	unsigned int Tx_LTINT	:1;	/* Start of packet for the Buffer */
777 	/*
778 	 * ADD_FCS dynamically controls the generation of FCS on a frame by
779 	 * frame basis.
780 	 */
781 	unsigned int Tx_ADD_FCS	:1;
782 	unsigned int Tx_RES1	:1;	/* Reserved Location */
783 	unsigned int Tx_OWN	:1;	/* Own Bit for the Transmit */
784 	unsigned int TCI 	:16;	/* VLAN Tag Control Command. */
785 	unsigned int TCC	:2;	/* Tag Control Information. */
786 	unsigned int Tx_RES0	:14;	/* Resvered Location */
787 	/*
788 	 * TBADR[31:0] Transmit Buffer Address. This field contains the address
789 	 * of the Transmit buffer that is associated with this descriptor
790 	 */
791 	unsigned int Tx_Base_Addr	:32;
792 	unsigned int Tx_USPACE		:32;	/* User Space */
793 };
794 
795 /* Receive Descriptor For the L7 */
796 struct rx_desc {
797 
798 	/* User Reserved amar - Its just reservered. */
799 	unsigned int Rx_USPACE	:32;
800 	/*
801 	 * Message Byte Count is the number of bytes of the received message
802 	 * written
803 	 */
804 	unsigned int Rx_MCNT	:16;
805 	unsigned int TCI	:16;
806 	/*
807 	 * Buffer Byte Count is the length of the buffer pointed to by this
808 	 * descriptor
809 	 */
810 	unsigned int Rx_BCNT	:16;
811 	unsigned int Rx_RES1	:2;	/* Reserved Location */
812 	/*
813 	 * VLAN Tag Type. Indicates what type of VLAN tag, if any, is included
814 	 * in the received
815 	 */
816 	unsigned int TT		:2;
817 	/*
818 	 * Broadcast Address Match is set by the Am79C976 controller when it
819 	 * accepts the reveice buffer
820 	 */
821 	unsigned int Rx_BAM	:1;
822 	/*
823 	 * Logical Address Filter Match is set by the Am79C976 controller
824 	 * to the Receive Buffer
825 	 */
826 	unsigned int Rx_LAFM	:1;
827 	/* Physical Address Match is set by the Am79C976 controller */
828 	unsigned int Rx_PAM	:1;
829 	unsigned int Rx_RES0	:1;	/* Resvered  Location */
830 	/* End Of packet to indicates the last Buffer */
831 	unsigned int Rx_EOP	:1;
832 	unsigned int Rx_SOP	:1;	/* Start of packet for the Buffer */
833 	unsigned int Rx_BUFF	:1;	/* Reserved location */
834 	/*
835 	 * CRC indicates that the receiver has detected a CRC (FCS) error on the
836 	 * incoming frame.
837 	 */
838 	unsigned int Rx_CRC	:1;
839 	/*
840 	 * Overflow error indicates that the receiver has lost all or part of
841 	 * the incoming frame.
842 	 */
843 	unsigned int Rx_OFLO	:1;
844 	unsigned int Rx_FRAM	:1;	/* Framing Error */
845 	unsigned int Rx_ERR	:1;	/* Error is Set By the Controller */
846 	unsigned int Rx_OWN	:1;	/* Own Bit of Descriptor */
847 	/*
848 	 * RBADR[31:0] Receive Buffer Address. This field contains the address
849 	 * of the receive buffer that is associated with this descriptor.
850 	 */
851 	unsigned int Rx_Base_Addr:32;
852 };
853 
854 
855 /* Initialization Block (SSIZE32 = 1) */
856 struct init_block {
857 	unsigned int MODE	:16;	/* Mode */
858 	unsigned int RES1	:4;		/* Reserved Location */
859 	/* Receive software structure is defined for 16 bit */
860 	unsigned int RLEN	:4;
861 	unsigned int RES2	:4;		/* Reserved bits */
862 	/* Transmit software structure is defined for the 16 bit */
863 	unsigned int TLEN	:4;
864 	unsigned int PADDR0	:8;
865 	unsigned int PADDR1	:8;
866 	unsigned int PADDR2	:8;
867 	unsigned int PADDR3	:8;
868 	unsigned int PADDR4	:8;
869 	unsigned int PADDR5	:8;
870 	unsigned int RES3	:16;
871 	unsigned char LADRF[8];
872 	/* RDRA indicate where the receive  descriptor ring begins */
873 	unsigned int RDRA	:32;
874 	/* TDRA indicate where the transmit descriptor ring begins */
875 	unsigned int TDRA	:32;
876 };
877 
878 /* MDL Physical and Normal Structure */
879 struct mdl {
880 	ULONG Io_Address;
881 	ULONG Mem_Address;
882 
883 	volatile int CSR;
884 	volatile int CardStatus;
885 
886 	/* PMR (Pattern Match RAM) */
887 	/*
888 	 * An array to store the indexes of each of the patterns in
889 	 * Pattern List.
890 	 */
891 	unsigned int *PMR_PtrList;
892 	/* An array of pattern controls and pattern data bytes */
893 	unsigned char *PatternList;
894 	unsigned int *PatternLength;
895 	int EnableMulticast;
896 	/* The begining of the free area in the PatternList array */
897 	unsigned short PatternList_FreeIndex;
898 	/* The total number of patterns present in the PMR */
899 	unsigned short TotalPatterns;
900 	unsigned short PatternEnableBit;
901 
902 	unsigned char Mac[6];
903 	unsigned char TEMP_MAC[6];
904 	unsigned int FLAGS;
905 	unsigned char TempLADRF[8];
906 
907 	ULONG Speed;
908 	ULONG FullDuplex;
909 
910 	struct init_block *init_blk;
911 
912 	int tmpPtrArray[8];
913 
914 	int MulticastBitMapArray[MULTICAST_BITMAP_ARRAY_SIZE];
915 	int External_Phy;
916 	unsigned int phy_id;
917 
918 	/* For interrupt delay */
919 	/* Unit is 10 us. Its value must < 0x800 (2^11) */
920 	unsigned int rx_intrcoalesc_time;
921 	/* Its value must < 32 (2^5) */
922 	unsigned int rx_intrcoalesc_events;
923 	unsigned int tx_intrcoalesc_time;
924 	unsigned int tx_intrcoalesc_events;
925 	int IntrCoalescFlag;
926 
927 	int RxRingLenBits;
928 	int TxRingLenBits;
929 	int TxRingSize;
930 	int RxRingSize;
931 
932 	int IpgValue;
933 };
934 
935 struct Rx_Buf_Desc {
936 	struct rx_desc *descriptor;
937 	long *USpaceMap;
938 };
939 
940 struct nonphysical
941 {
942 	/* Tx descriptors queue */
943 	struct tx_desc *TxDescQRead;	/* The next ring entry to be freed */
944 	struct tx_desc *TxDescQWrite;	/* The next free ring entry */
945 	struct tx_desc *TxDescQStart;	/* The start of the ring entries */
946 	struct tx_desc *TxDescQEnd;	/* The end of the ring entries */
947 
948 	/* struct Rx_Buf_Desc * queue */
949 	struct Rx_Buf_Desc *RxBufDescQRead;
950 	struct Rx_Buf_Desc *RxBufDescQStart;
951 	struct Rx_Buf_Desc *RxBufDescQEnd;
952 
953 };
954 
955 struct  mil
956 {
957 	/*
958 	 *	1) For memory allocation and free
959 	 */
960 
961 	/*
962 	 * Tx_desc: address of all tx descriptors block
963 	 * Tx_desc_pa: physical address of Tx_desc
964 	 */
965 	struct tx_desc *Tx_desc;
966 	unsigned int Tx_desc_pa;
967 	/* Original address, because Tx_desc needs 16 bytes alignment */
968 	ULONG Tx_desc_original;
969 
970 	struct rx_desc *Rx_desc;
971 	unsigned int Rx_desc_pa;
972 	/* Original address, because Rx_desc needs 16 bytes alignment */
973 	ULONG Rx_desc_original;
974 
975 	long *USpaceMapArray;	/* Queue of struct rxBufInfo * */
976 
977 	/*
978 	 *	2) For descriptor queue/buffer queue operation
979 	 */
980 	struct nonphysical *pNonphysical;
981 
982 	/*
983 	 *	3) Parameters
984 	 */
985 	int RxRingSize;
986 	int TxRingSize;
987 	int RxBufSize;
988 
989 	/*
990 	 *	4) Other
991 	 */
992 	int tx_reschedule;
993 	char *name;
994 };
995 
996 struct LayerPointers
997 {
998 	struct odl *pOdl;
999 	struct mil *pMil;
1000 	struct mdl *pMdl;
1001 
1002 	int instance;
1003 	int attach_progress;
1004 	int run;	/* B_TRUE on plumb; B_FALSE on unplumb */
1005 };
1006 
1007 /* MIL Function Prototypes. */
1008 
1009 /*
1010  * Initialisation of MIL data structures and External Interface Function
1011  * Pointers.
1012  */
1013 void milInitGlbds(struct LayerPointers *);
1014 
1015 void milInitRxQ(struct LayerPointers *);
1016 
1017 void milResetTxQ(struct LayerPointers *);
1018 
1019 void milFreeResources(struct LayerPointers *, ULONG *);
1020 
1021 void milRequestResources(ULONG *);
1022 void milSetResources(struct LayerPointers *, ULONG *);
1023 
1024 /* Open Functions. */
1025 void mdlOpen(struct LayerPointers *);
1026 
1027 void mdlHWReset(struct LayerPointers *);
1028 
1029 /* Multicast */
1030 void mdlDeleteMulticastAddress(struct LayerPointers *, UCHAR *);
1031 void mdlAddMulticastAddress(struct LayerPointers *, UCHAR *);
1032 
1033 /* Transmit/Receive Interface provided by MDL */
1034 void mdlTransmit(struct LayerPointers *);
1035 void mdlReceive(struct LayerPointers *);
1036 
1037 unsigned int mdlReadMib(struct LayerPointers *, char);
1038 
1039 /* Read Link Status */
1040 int mdlReadLink(struct LayerPointers *);
1041 
1042 /* Interrupt Handling */
1043 unsigned int mdlReadInterrupt(struct LayerPointers *);
1044 
1045 void mdlEnableInterrupt(struct LayerPointers *);
1046 void mdlDisableInterrupt(struct LayerPointers *);
1047 
1048 void mdlGetActiveMediaInfo(struct LayerPointers *);
1049 
1050 void mdlStartChip(struct LayerPointers *);
1051 void mdlStopChip(struct LayerPointers *);
1052 
1053 void mdlGetMacAddress(struct LayerPointers *, unsigned char *);
1054 void mdlSetMacAddress(struct LayerPointers *, unsigned char *);
1055 
1056 void mdlAddMulticastAddresses(struct LayerPointers *, int, unsigned char *);
1057 
1058 void mdlSetPromiscuous(struct LayerPointers *);
1059 void mdlDisablePromiscuous(struct LayerPointers *);
1060 
1061 void mdlSendPause(struct LayerPointers *);
1062 
1063 void SetIntrCoalesc(struct LayerPointers *, boolean_t);
1064 void mdlPHYAutoNegotiation(struct LayerPointers *, unsigned int);
1065 void mdlRxFastSuspend(struct LayerPointers *);
1066 void mdlRxFastSuspendClear(struct LayerPointers *);
1067 
1068 /* Externs */
1069 
1070 /* ODL functions */
1071 extern void amd8111s_reset(struct LayerPointers *);
1072 extern unsigned char READ_REG8(struct LayerPointers *, long);
1073 extern void WRITE_REG8(struct LayerPointers *, long, int);
1074 extern int READ_REG16(struct LayerPointers *, long);
1075 extern void WRITE_REG16(struct LayerPointers *, long, int);
1076 extern long READ_REG32(struct LayerPointers *, long);
1077 extern void WRITE_REG32(struct LayerPointers *, long, int);
1078 extern void WRITE_REG64(struct LayerPointers *, long, char *);
1079 
1080 #endif	/* AMD8111S_HW_H */
1081