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Searched refs:I915_WRITE16 (Results 1 – 4 of 4) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Di915_irq.c2918 I915_WRITE16(IMR, 0xffff); in i8xx_irq_preinstall()
2919 I915_WRITE16(IER, 0x0); in i8xx_irq_preinstall()
2927 I915_WRITE16(EMR, in i8xx_irq_postinstall()
2938 I915_WRITE16(IMR, dev_priv->irq_mask); in i8xx_irq_postinstall()
2940 I915_WRITE16(IER, in i8xx_irq_postinstall()
3026 I915_WRITE16(IIR, iir & ~flip_mask); in i8xx_irq_handler()
3058 I915_WRITE16(IMR, 0xffff); in i8xx_irq_uninstall()
3059 I915_WRITE16(IER, 0x0); in i8xx_irq_uninstall()
3060 I915_WRITE16(IIR, I915_READ16(IIR)); in i8xx_irq_uninstall()
3075 I915_WRITE16(HWSTAM, 0xeffe); in i915_irq_preinstall()
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H A Dintel_pm.c2924 I915_WRITE16(MEMSWCTL, rgvswctl); in ironlake_set_drps()
2928 I915_WRITE16(MEMSWCTL, rgvswctl); in ironlake_set_drps()
2942 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); in ironlake_enable_drps()
2943 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); in ironlake_enable_drps()
4458 I915_WRITE16(DEUC, 0); in crestline_init_clock_gating()
H A Dintel_ringbuffer.c916 I915_WRITE16(IMR, dev_priv->irq_mask); in i8xx_ring_get_irq()
934 I915_WRITE16(IMR, dev_priv->irq_mask); in i8xx_ring_put_irq()
H A Di915_drv.h2013 #define I915_WRITE16(reg,val) i915_write16(dev_priv, (reg), (u16)(val)) macro