Searched refs:I915_GEM_GPU_DOMAINS (Results 1 – 5 of 5) sorted by relevance
833 obj->base.write_domain &= ~I915_GEM_GPU_DOMAINS; in i915_gem_object_wait_rendering__tail()915 if (write_domain & I915_GEM_GPU_DOMAINS) in i915_gem_set_domain_ioctl()918 if (read_domains & I915_GEM_GPU_DOMAINS) in i915_gem_set_domain_ioctl()1422 BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS); in i915_gem_object_move_to_inactive()1795 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; in i915_gem_reset()2969 if ((obj->base.read_domains & I915_GEM_GPU_DOMAINS) == 0) in i915_gem_object_finish_gpu()2977 obj->base.read_domains &= ~I915_GEM_GPU_DOMAINS; in i915_gem_object_finish_gpu()
1683 if (invalidate & I915_GEM_GPU_DOMAINS) in gen6_bsd_ring_flush()2065 ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS); in intel_ring_flush_all_caches()2082 flush_domains = I915_GEM_GPU_DOMAINS; in intel_ring_invalidate_all_caches()2084 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains); in intel_ring_invalidate_all_caches()
389 ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0); in mi_set_context()
128 & ~I915_GEM_GPU_DOMAINS)) { in i915_gem_execbuffer_relocate_entry()408 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND; in i915_gem_execbuffer_reserve()
120 #define I915_GEM_GPU_DOMAINS \ macro