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Searched refs:GEN7_MISCCPCTL (Results 1 – 3 of 3) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Di915_gem.c3449 misccpctl = I915_READ(GEN7_MISCCPCTL); in i915_gem_l3_remap()
3450 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); in i915_gem_l3_remap()
3451 POSTING_READ(GEN7_MISCCPCTL); in i915_gem_l3_remap()
3466 I915_WRITE(GEN7_MISCCPCTL, misccpctl); in i915_gem_l3_remap()
H A Di915_irq.c734 misccpctl = I915_READ(GEN7_MISCCPCTL); in ivybridge_parity_work()
735 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); in ivybridge_parity_work()
736 POSTING_READ(GEN7_MISCCPCTL); in ivybridge_parity_work()
747 I915_WRITE(GEN7_MISCCPCTL, misccpctl); in ivybridge_parity_work()
H A Di915_reg.h4683 #define GEN7_MISCCPCTL (0x9424) macro