Searched refs:GEN6_PMIMR (Results 1 – 5 of 5) sorted by relevance
/gfx-drm/usr/src/uts/intel/io/i915/ |
H A D | intel_ringbuffer.c | 1089 u32 pm_imr = I915_READ(GEN6_PMIMR); in hsw_vebox_get_irq() 1091 I915_WRITE(GEN6_PMIMR, pm_imr & ~ring->irq_enable_mask); in hsw_vebox_get_irq() 1092 POSTING_READ(GEN6_PMIMR); in hsw_vebox_get_irq() 1111 u32 pm_imr = I915_READ(GEN6_PMIMR); in hsw_vebox_put_irq() 1113 I915_WRITE(GEN6_PMIMR, pm_imr | ring->irq_enable_mask); in hsw_vebox_put_irq() 1114 POSTING_READ(GEN6_PMIMR); in hsw_vebox_put_irq()
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H A D | i915_irq.c | 674 pm_imr = I915_READ(GEN6_PMIMR); in gen6_pm_rps_work() 675 I915_WRITE(GEN6_PMIMR, pm_imr & ~GEN6_PM_RPS_EVENTS); in gen6_pm_rps_work() 817 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir); in gen6_queue_rps_work() 818 POSTING_READ(GEN6_PMIMR); in gen6_queue_rps_work() 896 I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir); in hsw_pm_irq_handler() 898 WARN_ON(I915_READ_NOTRACE(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS); in hsw_pm_irq_handler() 2588 I915_WRITE(GEN6_PMIMR, 0xffffffff); in ivybridge_irq_preinstall() 2786 I915_WRITE(GEN6_PMIMR, in ivybridge_irq_postinstall() 2787 (I915_READ(GEN6_PMIMR) | ~GEN6_PM_RPS_EVENTS) & ~pm_irqs); in ivybridge_irq_postinstall()
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H A D | intel_pm.c | 3349 I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS); in gen6_enable_rps() 3621 I915_WRITE(GEN6_PMIMR, 0); in valleyview_enable_rps()
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H A D | i915_reg.h | 4643 #define GEN6_PMIMR 0x44024 /* rps_lock */ macro
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/gfx-drm/usr/src/cmd/mdb/i915/ |
H A D | i915.c | 1454 ret = i915_read(dev_priv, (uintptr_t)GEN6_PMIMR, &val); in i915_interrupt_info()
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