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Searched refs:GEN6_CXT_PIPELINE_SIZE (Results 1 – 1 of 1) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Di915_reg.h1790 #define GEN6_CXT_PIPELINE_SIZE(cxt_reg) ((cxt_reg >> 0) & 0x3f) macro
1795 GEN6_CXT_PIPELINE_SIZE(cxt_reg))