xref: /illumos-gate/usr/src/uts/intel/sys/mc_intel.h (revision eb00b1c8)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  * Copyright 2019 Joyent, Inc.
26  */
27 
28 #ifndef _MC_INTEL_H
29 #define	_MC_INTEL_H
30 
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34 
35 #define	FM_EREPORT_CPU_INTEL	"intel"
36 
37 #define	MCINTEL_NVLIST_VERSTR	"mcintel-nvlist-version"
38 #define	MCINTEL_NVLIST_VERS0	0
39 #define	MCINTEL_NVLIST_VERS1	1
40 
41 #define	MCINTEL_NVLIST_VERS	MCINTEL_NVLIST_VERS0
42 
43 #define	MCINTEL_NVLIST_MEM	"memory-controller"
44 #define	MCINTEL_NVLIST_NMEM	"memory-controllers"
45 #define	MCINTEL_NVLIST_MC	"memory-channels"
46 #define	MCINTEL_NVLIST_DIMMS	"memory-dimms"
47 #define	MCINTEL_NVLIST_DIMMSZ	"memory-dimm-size"
48 #define	MCINTEL_NVLIST_NRANKS	"dimm-max-ranks"
49 #define	MCINTEL_NVLIST_NDIMMS	"dimm-max-dimms"
50 #define	MCINTEL_NVLIST_RANKS	"dimm-ranks"
51 #define	MCINTEL_NVLIST_1ST_RANK	"dimm-start-rank"
52 #define	MCINTEL_NVLIST_DIMM_NUM	"dimm-number"
53 #define	MCINTEL_NVLIST_ROWS	"dimm-rows"
54 #define	MCINTEL_NVLIST_COL	"dimm-column"
55 #define	MCINTEL_NVLIST_BANK	"dimm-banks"
56 #define	MCINTEL_NVLIST_WIDTH	"dimm-width"
57 #define	MCINTEL_NVLIST_MID	"dimm-manufacture-id"
58 #define	MCINTEL_NVLIST_MLOC	"dimm-manufacture-location"
59 #define	MCINTEL_NVLIST_MWEEK	"dimm-manufacture-week"
60 #define	MCINTEL_NVLIST_MYEAR	"dimm-manufacture-year"
61 #define	MCINTEL_NVLIST_SERIALNO	"dimm-serial-number"
62 #define	MCINTEL_NVLIST_PARTNO	"dimm-part-number"
63 #define	MCINTEL_NVLIST_REV	"dimm-part-rev"
64 
65 /*
66  * Version 1 payload. Whereas the version 0 payload uses a flat name space, we
67  * instead opt to use a hierarchical name space. This means that we can know how
68  * many devices there are at any level, as each level has this. Effectively,
69  * this means that we have an nvlist structure, for a socket that looks like:
70  *
71  * socket
72  *	string	version
73  *	uint8_t num-memory-controllers
74  *	nvlist array memory-controller[]
75  *		uint8_t num-channels
76  *		boolean ecc
77  *		string page policy
78  *		string lockstep || independent
79  *		nvlist array channel[]
80  *			uint8_t dpc
81  *			nvlist array dimm[]
82  *				boolean_t present;
83  *				uint32_t ncolumns
84  *				uint32_t nrows
85  *				uint64_t density (in bytes)
86  *				uint32_t width
87  *				uint32_t ranks
88  *				uint32_t banks
89  *				boolean_t array ranks_disabled
90  *				boolean_t hdrl-enabled
91  *				boolean_t hdrl-parity
92  *				uint32_t 3dnumranks
93  */
94 
95 #define	MCINTEL_NVLIST_V1_NMC		"num-memory-controllers"
96 #define	MCINTEL_NVLIST_V1_MCS		"memory-controllers"
97 #define	MCINTEL_NVLIST_V1_MC_NCHAN	"num-memory-channels"
98 #define	MCINTEL_NVLIST_V1_MC_CHANNELS	"memory-controller-channels"
99 #define	MCINTEL_NVLIST_V1_MC_ECC	"memory-controller-ecc"
100 #define	MCINTEL_NVLIST_V1_MC_POLICY	"memory-controller-page-policy"
101 #define	MCINTEL_NVLIST_V1_MC_POLICY_OPEN	"open-page"
102 #define	MCINTEL_NVLIST_V1_MC_POLICY_CLOSED	"closed-page"
103 #define	MCINTEL_NVLIST_V1_MC_CHAN_MODE	"memory-controller-channel-mode"
104 #define	MCINTEL_NVLIST_V1_MC_CHAN_MODE_LOCK	"lockstep"
105 #define	MCINTEL_NVLIST_V1_MC_CHAN_MODE_INDEP	"independent"
106 #define	MCINTEL_NVLIST_V1_CHAN_NDPC	"memory-channel-dimms-per-channel"
107 #define	MCINTEL_NVLIST_V1_CHAN_DIMMS	"memory-channel-dimms"
108 #define	MCINTEL_NVLIST_V1_DIMM_PRESENT	"dimm-present"
109 #define	MCINTEL_NVLIST_V1_DIMM_SIZE	"dimm-size"
110 #define	MCINTEL_NVLIST_V1_DIMM_NCOLS	"dimm-num-columns"
111 #define	MCINTEL_NVLIST_V1_DIMM_NROWS	"dimm-num-rows"
112 #define	MCINTEL_NVLIST_V1_DIMM_DENSITY	"dimm-density"
113 #define	MCINTEL_NVLIST_V1_DIMM_WIDTH	"dimm-width"
114 #define	MCINTEL_NVLIST_V1_DIMM_RANKS	"dimm-ranks"
115 #define	MCINTEL_NVLIST_V1_DIMM_BANKS	"dimm-banks"
116 #define	MCINTEL_NVLIST_V1_DIMM_RDIS	"dimm-ranks-disabled"
117 #define	MCINTEL_NVLIST_V1_DIMM_HDRL	"dimm-hdrl-enabled"
118 #define	MCINTEL_NVLIST_V1_DIMM_HDRLP	"dimm-hdrl-parity-enabled"
119 #define	MCINTEL_NVLIST_V1_DIMM_3DRANK	"dimm-3dranks"
120 
121 #define	FM_EREPORT_PAYLOAD_NAME_FERR_GLOBAL		"ferr_global"
122 #define	FM_EREPORT_PAYLOAD_NAME_NERR_GLOBAL		"nerr_global"
123 #define	FM_EREPORT_PAYLOAD_NAME_FSB			"fsb"
124 #define	FM_EREPORT_PAYLOAD_NAME_FERR_FAT_FSB		"ferr_fat_fsb"
125 #define	FM_EREPORT_PAYLOAD_NAME_NERR_FAT_FSB		"nerr_fat_fsb"
126 #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_FSB		"ferr_nf_fsb"
127 #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_FSB		"nerr_nf_fsb"
128 #define	FM_EREPORT_PAYLOAD_NAME_NRECFSB			"nrecfsb"
129 #define	FM_EREPORT_PAYLOAD_NAME_NRECFSB_ADDR		"nrecfsb_addr"
130 #define	FM_EREPORT_PAYLOAD_NAME_RECFSB			"recfsb"
131 #define	FM_EREPORT_PAYLOAD_NAME_PEX			"pex"
132 #define	FM_EREPORT_PAYLOAD_NAME_PEX_FAT_FERR		"pex_fat_ferr"
133 #define	FM_EREPORT_PAYLOAD_NAME_PEX_FAT_NERR		"pex_fat_nerr"
134 #define	FM_EREPORT_PAYLOAD_NAME_PEX_NF_CORR_FERR	"pex_nf_corr_ferr"
135 #define	FM_EREPORT_PAYLOAD_NAME_PEX_NF_CORR_NERR	"pex_nf_corr_nerr"
136 #define	FM_EREPORT_PAYLOAD_NAME_UNCERRSEV		"uncerrsev"
137 #define	FM_EREPORT_PAYLOAD_NAME_RPERRSTS		"rperrsts"
138 #define	FM_EREPORT_PAYLOAD_NAME_RPERRSID		"rperrsid"
139 #define	FM_EREPORT_PAYLOAD_NAME_UNCERRSTS		"uncerrsts"
140 #define	FM_EREPORT_PAYLOAD_NAME_AERRCAPCTRL		"aerrcapctrl"
141 #define	FM_EREPORT_PAYLOAD_NAME_CORERRSTS		"corerrsts"
142 #define	FM_EREPORT_PAYLOAD_NAME_PEXDEVSTS		"pexdevsts"
143 #define	FM_EREPORT_PAYLOAD_NAME_FERR_FAT_INT		"ferr_fat_int"
144 #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_INT		"ferr_nf_int"
145 #define	FM_EREPORT_PAYLOAD_NAME_NERR_FAT_INT		"nerr_fat_int"
146 #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_INT		"nerr_nf_int"
147 #define	FM_EREPORT_PAYLOAD_NAME_NRECINT			"nrecint"
148 #define	FM_EREPORT_PAYLOAD_NAME_RECINT			"recint"
149 #define	FM_EREPORT_PAYLOAD_NAME_NRECSF			"nrecsf"
150 #define	FM_EREPORT_PAYLOAD_NAME_RECSF			"recsf"
151 #define	FM_EREPORT_PAYLOAD_NAME_RANK			"rank"
152 #define	FM_EREPORT_PAYLOAD_NAME_BANK			"bank"
153 #define	FM_EREPORT_PAYLOAD_NAME_CAS			"cas"
154 #define	FM_EREPORT_PAYLOAD_NAME_RAS			"ras"
155 #define	FM_EREPORT_PAYLOAD_NAME_FERR_FAT_FBD		"ferr_fat_fbd"
156 #define	FM_EREPORT_PAYLOAD_NAME_NERR_FAT_FBD		"nerr_fat_fbd"
157 #define	FM_EREPORT_PAYLOAD_NAME_VALIDLOG		"validlog"
158 #define	FM_EREPORT_PAYLOAD_NAME_NRECMEMA		"nrecmema"
159 #define	FM_EREPORT_PAYLOAD_NAME_NRECMEMB		"nrecmemb"
160 #define	FM_EREPORT_PAYLOAD_NAME_NRECFGLOG		"nrecfglog"
161 #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDA		"nrecfbda"
162 #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDB		"nrecfbdb"
163 #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDC		"nrecfbdc"
164 #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDD		"nrecfbdd"
165 #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDE		"nrecfbde"
166 #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDF		"nrecfbdf"
167 #define	FM_EREPORT_PAYLOAD_NAME_SPCPC			"spcpc"
168 #define	FM_EREPORT_PAYLOAD_NAME_SPCPS			"spcps"
169 #define	FM_EREPORT_PAYLOAD_NAME_UERRCNT			"uerrcnt"
170 #define	FM_EREPORT_PAYLOAD_NAME_UERRCNT_LAST		"uerrcnt_last"
171 #define	FM_EREPORT_PAYLOAD_NAME_BADRAM			"badram"
172 #define	FM_EREPORT_PAYLOAD_NAME_BADRAMA			"badrama"
173 #define	FM_EREPORT_PAYLOAD_NAME_BADRAMB			"badramb"
174 #define	FM_EREPORT_PAYLOAD_NAME_BADCNT			"badcnt"
175 #define	FM_EREPORT_PAYLOAD_NAME_MC			"mc"
176 #define	FM_EREPORT_PAYLOAD_NAME_MCA			"mca"
177 #define	FM_EREPORT_PAYLOAD_NAME_TOLM			"tolm"
178 #define	FM_EREPORT_PAYLOAD_NAME_MIR			"mir"
179 #define	FM_EREPORT_PAYLOAD_NAME_MTR			"mtr"
180 #define	FM_EREPORT_PAYLOAD_NAME_DMIR			"dmir"
181 #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_FBD		"ferr_nf_fbd"
182 #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_FBD		"nerr_nf_fbd"
183 #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_MEM		"ferr_nf_mem"
184 #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_MEM		"nerr_nf_mem"
185 #define	FM_EREPORT_PAYLOAD_NAME_RECMEMA			"recmema"
186 #define	FM_EREPORT_PAYLOAD_NAME_RECMEMB			"recmemb"
187 #define	FM_EREPORT_PAYLOAD_NAME_REDMEMA			"redmema"
188 #define	FM_EREPORT_PAYLOAD_NAME_REDMEMB			"redmemb"
189 #define	FM_EREPORT_PAYLOAD_NAME_RECFGLOG		"recfglog"
190 #define	FM_EREPORT_PAYLOAD_NAME_RECFBDA			"recfbda"
191 #define	FM_EREPORT_PAYLOAD_NAME_RECFBDB			"recfbdb"
192 #define	FM_EREPORT_PAYLOAD_NAME_RECFBDC			"recfbdc"
193 #define	FM_EREPORT_PAYLOAD_NAME_RECFBDD			"recfbdd"
194 #define	FM_EREPORT_PAYLOAD_NAME_RECFBDE			"recfbde"
195 #define	FM_EREPORT_PAYLOAD_NAME_RECFBDF			"recfbdf"
196 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNT			"cerrcnt"
197 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNT_LAST		"cerrcnt_last"
198 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNT_EXT		"cerrcnt_ext"
199 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNT_EXT_LAST	"cerrcnt_ext_last"
200 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTA		"cerrcnta"
201 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTB		"cerrcntb"
202 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTC		"cerrcntc"
203 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTD		"cerrcntd"
204 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTA_LAST		"cerrcnta_last"
205 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTB_LAST		"cerrcntb_last"
206 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTC_LAST		"cerrcntc_last"
207 #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTD_LAST		"cerrcntd_last"
208 #define	FM_EREPORT_PAYLOAD_NAME_PCISTS			"pcists"
209 #define	FM_EREPORT_PAYLOAD_NAME_PEXDEVSTS		"pexdevsts"
210 #define	FM_EREPORT_PAYLOAD_NAME_ERROR_NO		"intel-error-list"
211 
212 #define	FM_EREPORT_PAYLOAD_NAME_CTSTS			"ctsts"
213 #define	FM_EREPORT_PAYLOAD_NAME_THRTSTS			"thrtsts"
214 #define	FM_EREPORT_PAYLOAD_NAME_FERR_FAT_THR		"ferr_fat_thr"
215 #define	FM_EREPORT_PAYLOAD_NAME_NERR_FAT_THR		"nerr_fat_thr"
216 #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_THR		"ferr_nf_thr"
217 #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_THR		"nerr_nf_thr"
218 
219 #define	FM_EREPORT_PAYLOAD_NAME_ADDR			"addr"
220 #define	FM_EREPORT_PAYLOAD_NAME_BANK_NUM		"bank-number"
221 #define	FM_EREPORT_PAYLOAD_NAME_BANK_MISC		"bank-misc"
222 #define	FM_EREPORT_PAYLOAD_NAME_BANK_STAT		"bank-status"
223 #define	FM_EREPORT_PAYLOAD_NAME_BANK_OFFSET		"bank-offset"
224 #define	FM_EREPORT_PAYLOAD_NAME_MC_TYPE			"mc-type"
225 #define	FM_EREPORT_PAYLOAD_CPUID			"cpuid"
226 
227 #define	FM_EREPORT_PAYLOAD_BQR				"Bus-queue-request"
228 #define	FM_EREPORT_PAYLOAD_BQET				"Bus-queue-error-type"
229 #define	FM_EREPORT_PAYLOAD_FRC				"FRC-error"
230 #define	FM_EREPORT_PAYLOAD_BERR				"BERR"
231 #define	FM_EREPORT_PAYLOAD_INT_BINT			"Internal-BINT"
232 #define	FM_EREPORT_PAYLOAD_EXT_BINT			"External-BINT"
233 #define	FM_EREPORT_PAYLOAD_BUS_BINT			"Bus-BINT"
234 #define	FM_EREPORT_PAYLOAD_TO_BINT			"Timeout-BINT"
235 #define	FM_EREPORT_PAYLOAD_HARD				"Hard-error"
236 #define	FM_EREPORT_PAYLOAD_IERR				"IERR"
237 #define	FM_EREPORT_PAYLOAD_AERR				"AERR"
238 #define	FM_EREPORT_PAYLOAD_UERR				"UERR"
239 #define	FM_EREPORT_PAYLOAD_CECC				"CECC"
240 #define	FM_EREPORT_PAYLOAD_UECC				"UECC"
241 #define	FM_EREPORT_PAYLOAD_ECC_SYND			"ECC-syndrome"
242 
243 #define	FM_EREPORT_PAYLOAD_FSB_PARITY			"fsb-address-parity"
244 #define	FM_EREPORT_PAYLOAD_RESP_HF			"response-hard-fail"
245 #define	FM_EREPORT_PAYLOAD_RESP_PARITY			"response-parity"
246 #define	FM_EREPORT_PAYLOAD_DATA_PARITY			"bus-data-parity"
247 #define	FM_EREPORT_PAYLOAD_INV_PIC			"invalid-pic-request"
248 #define	FM_EREPORT_PAYLOAD_PAD_SM			"pad-state-machine"
249 #define	FM_EREPORT_PAYLOAD_PAD_SG			"pad-strobe-glitch"
250 
251 #define	FM_EREPORT_PAYLOAD_TAG				"tag-error"
252 #define	FM_EREPORT_PAYLOAD_TAG_CLEAN			"clean"
253 #define	FM_EREPORT_PAYLOAD_TAG_HIT			"hit"
254 #define	FM_EREPORT_PAYLOAD_TAG_MISS			"miss"
255 #define	FM_EREPORT_PAYLOAD_DATA				"data-error"
256 #define	FM_EREPORT_PAYLOAD_DATA_SINGLE			"single-bit"
257 #define	FM_EREPORT_PAYLOAD_DATA_DBL_CLEAN		"double-bit-clean"
258 #define	FM_EREPORT_PAYLOAD_DATA_DBL_MOD			"double-bit-modified"
259 #define	FM_EREPORT_PAYLOAD_L3				"l3-cache"
260 #define	FM_EREPORT_PAYLOAD_INV_PIC			"invalid-pic-request"
261 #define	FM_EREPORT_PAYLOAD_CACHE_NERRORS		"cache-error-count"
262 
263 #define	FM_EREPORT_PAYLOAD_NAME_RESOURCE		"resource"
264 #define	FM_EREPORT_PAYLOAD_MEM_ECC_COUNTER_THIS	"mem_cor_ecc_counter"
265 #define	FM_EREPORT_PAYLOAD_MEM_ECC_COUNTER_LAST	"mem_cor_ecc_counter_last"
266 
267 #define	INTEL_NB_5000P	0x25d88086
268 #define	INTEL_NB_5000V	0x25d48086
269 #define	INTEL_NB_5000X	0x25c08086
270 #define	INTEL_NB_5000Z	0x25d08086
271 #define	INTEL_NB_5100	0x65c08086
272 #define	INTEL_NB_5400	0x40008086
273 #define	INTEL_NB_5400A	0x40018086
274 #define	INTEL_NB_5400B	0x40038086
275 #define	INTEL_NB_7300	0x36008086
276 
277 #define	INTEL_NHM	0x2c408086
278 #define	INTEL_QP_IO	0x34008086
279 #define	INTEL_QP_36D	0x34068086
280 #define	INTEL_QP_24D	0x34038086
281 #define	INTEL_QP_WP	0x34058086
282 #define	INTEL_QP_U1	0x34018086
283 #define	INTEL_QP_U2	0x34028086
284 #define	INTEL_QP_U3	0x34048086
285 #define	INTEL_QP_U4	0x34078086
286 #define	INTEL_QP_JF	0x37208086
287 #define	INTEL_QP_JF0	0x37008086
288 #define	INTEL_QP_JF1	0x37018086
289 #define	INTEL_QP_JF2	0x37028086
290 #define	INTEL_QP_JF3	0x37038086
291 #define	INTEL_QP_JF4	0x37048086
292 #define	INTEL_QP_JF5	0x37058086
293 #define	INTEL_QP_JF6	0x37068086
294 #define	INTEL_QP_JF7	0x37078086
295 #define	INTEL_QP_JF8	0x37088086
296 #define	INTEL_QP_JF9	0x37098086
297 #define	INTEL_QP_JFa	0x370a8086
298 #define	INTEL_QP_JFb	0x370b8086
299 #define	INTEL_QP_JFc	0x370c8086
300 #define	INTEL_QP_JFd	0x370d8086
301 #define	INTEL_QP_JFe	0x370e8086
302 #define	INTEL_QP_JFf	0x370f8086
303 
304 /* Intel QuickPath Bus Interconnect Errors */
305 
306 #define	MSR_MC_STATUS_QP_HEADER_PARITY		(1 << 16)
307 #define	MSR_MC_STATUS_QP_DATA_PARITY		(1 << 17)
308 #define	MSR_MC_STATUS_QP_RETRIES_EXCEEDED	(1 << 18)
309 #define	MSR_MC_STATUS_QP_POISON		(1 << 19)
310 
311 #define	MSR_MC_STATUS_QP_UNSUPPORTED_MSG	(1 << 22)
312 #define	MSR_MC_STATUS_QP_UNSUPPORTED_CREDIT	(1 << 23)
313 #define	MSR_MC_STATUS_QP_FLIT_BUF_OVER		(1 << 24)
314 #define	MSR_MC_STATUS_QP_FAILED_RESPONSE	(1 << 25)
315 #define	MSR_MC_STATUS_QP_CLOCK_JITTER		(1 << 26)
316 
317 #define	MSR_MC_MISC_QP_CLASS		0x000000ff
318 #define	MSR_MC_MISC_QP_RTID		0x00003f00
319 #define	MSR_MC_MISC_QP_RHNID		0x00070000
320 #define	MSR_MC_MISC_QP_IIB		0x01000000
321 
322 /* Intel QuickPath Memory Errors */
323 
324 #define	MCAX86_COMPOUND_BUS_MEMORY		0x0080
325 #define	MCAX86_COMPOUND_BUS_MEMORY_MASK		0xff80
326 #define	MCAX86_COMPOUND_BUS_MEMORY_TRANSACTION	0x0070
327 #define	MCAX86_COMPOUND_BUS_MEMORY_READ		0x0010
328 #define	MCAX86_COMPOUND_BUS_MEMORY_WRITE	0x0020
329 #define	MCAX86_COMPOUND_BUS_MEMORY_CMD		0x0030
330 #define	MCAX86_COMPOUND_BUS_MEMORY_CHANNEL	0x000f
331 
332 #define	MSR_MC_STATUS_MEM_ECC_READ	(1 << 16)
333 #define	MSR_MC_STATUS_MEM_ECC_SCRUB	(1 << 17)
334 #define	MSR_MC_STATUS_MEM_PARITY	(1 << 18)
335 #define	MSR_MC_STATUS_MEM_REDUNDANT_MEM	(1 << 19)
336 #define	MSR_MC_STATUS_MEM_SPARE_MEM	(1 << 20)
337 #define	MSR_MC_STATUS_MEM_ILLEGAL_ADDR	(1 << 21)
338 #define	MSR_MC_STATUS_MEM_BAD_ID	(1 << 22)
339 #define	MSR_MC_STATUS_MEM_ADDR_PARITY	(1 << 23)
340 #define	MSR_MC_STATUS_MEM_BYTE_PARITY	(1 << 24)
341 
342 #define	MSR_MC_MISC_MEM_RTID		0x00000000000000ffULL
343 #define	MSR_MC_MISC_MEM_DIMM		0x0000000000030000ULL
344 #define	MSR_MC_MISC_MEM_DIMM_SHIFT	16
345 #define	MSR_MC_MISC_MEM_CHANNEL		0x00000000000c0000ULL
346 #define	MSR_MC_MISC_MEM_CHANNEL_SHIFT	18
347 #define	MSR_MC_MISC_MEM_SYNDROME	0xffffffff00000000ULL
348 #define	MSR_MC_MISC_MEM_SYNDROME_SHIFT	32
349 
350 #define	OFFSET_ROW_BANK_COL	0x8000000000000000ULL
351 #define	OFFSET_RANK_SHIFT	52
352 #define	OFFSET_RAS_SHIFT	32
353 #define	OFFSET_BANK_SHIFT	24
354 #define	TCODE_OFFSET(rank, bank, ras, cas) (OFFSET_ROW_BANK_COL | \
355 	((uint64_t)(rank) << OFFSET_RANK_SHIFT) | \
356 	((uint64_t)(ras) << OFFSET_RAS_SHIFT) | \
357 	((uint64_t)(bank) << OFFSET_BANK_SHIFT) | (cas))
358 
359 #define	MAX_CAS_MASK	0xFFFFFF
360 #define	MAX_BANK_MASK	0xFF
361 #define	MAX_RAS_MASK	0xFFFFF
362 #define	MAX_RANK_MASK	0x7FF
363 #define	TCODE_OFFSET_RANK(tcode) \
364 	(((tcode) >> OFFSET_RANK_SHIFT) & MAX_RANK_MASK)
365 #define	TCODE_OFFSET_RAS(tcode) (((tcode) >> OFFSET_RAS_SHIFT) & MAX_RAS_MASK)
366 #define	TCODE_OFFSET_BANK(tcode) \
367 	(((tcode) >> OFFSET_BANK_SHIFT) & MAX_BANK_MASK)
368 #define	TCODE_OFFSET_CAS(tcode) ((tcode) & MAX_CAS_MASK)
369 
370 #ifdef __cplusplus
371 }
372 #endif
373 
374 #endif /* _MC_INTEL_H */
375