xref: /illumos-gate/usr/src/uts/sun/io/eri/eri.h (revision bd78278b)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_ERI_H
27 #define	_SYS_ERI_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 
34 #ifdef _KERNEL
35 
36 /* Named Dispatch Parameter Management Structure */
37 typedef struct param_s {
38 	uint32_t param_min;
39 	uint32_t param_max;
40 	uint32_t param_val;
41 	char   *param_name;
42 } param_t;
43 
44 #define	ERI_PARAM_CNT	51
45 
46 typedef enum  {
47 	MIF_POLL_STOP,
48 	MIF_POLL_START
49 } soft_mif_enable_t;
50 
51 
52 /*
53  * kstats
54  */
55 typedef struct stats {
56 	/*
57 	 * Link Input/Output stats
58 	 * ifspeed is now in bits/second.
59 	 */
60 	uint64_t	ipackets64;
61 	uint64_t	iipackets64;
62 	uint32_t	ierrors;
63 	uint64_t	opackets64;
64 	uint64_t	oerrors;
65 	uint32_t	collisions;
66 	uint64_t	ifspeed;
67 
68 	/*
69 	 * MAC TX Event stats
70 	 */
71 	uint32_t	txmac_urun;
72 	uint32_t	txmac_maxpkt_err;
73 	uint32_t	excessive_coll;
74 	uint32_t	late_coll;
75 	uint32_t	first_coll;
76 	uint32_t	defer_timer_exp;
77 	uint32_t	peak_attempt_cnt;
78 	uint32_t	tx_hang;
79 
80 	/*
81 	 * MAC RX Event stats
82 	 */
83 	uint32_t	rx_corr;
84 	uint32_t	no_free_rx_desc;	/* no free rx desc. */
85 	uint32_t	rx_overflow;
86 	uint32_t	rx_ovrflpkts;
87 	uint32_t	rx_hang;
88 	uint32_t	rx_align_err;
89 	uint32_t	rx_crc_err;
90 	uint32_t	rx_length_err;
91 	uint32_t	rx_code_viol_err;
92 
93 	/*
94 	 * MAC Control event stats
95 	 */
96 	uint32_t	pause_rxcount;	/* PAUSE Receive cnt */
97 	uint32_t	pause_oncount;
98 	uint32_t	pause_offcount;
99 	uint32_t	pause_time_count;
100 	uint32_t	pausing;
101 
102 	/*
103 	 * Software event stats
104 	 */
105 	uint32_t	inits;
106 	uint32_t	rx_inits;
107 	uint32_t	tx_inits;
108 	uint32_t	tnocar;	/* Link down counter */
109 
110 	uint32_t	jab;
111 	uint32_t	notmds;
112 	uint32_t	nocanput;
113 	uint32_t	allocbfail;
114 	uint32_t	drop;
115 	uint32_t	rx_corrupted;
116 	uint32_t	rx_bad_pkts;
117 	uint32_t	rx_runt;
118 	uint32_t	rx_toolong_pkts;
119 
120 
121 	/*
122 	 * Fatal errors
123 	 */
124 	uint32_t	rxtag_err;
125 
126 	/*
127 	 * parity error
128 	 */
129 	uint32_t	parity_error;
130 
131 	/*
132 	 * Fatal error stats
133 	 */
134 	uint32_t	pci_error_int;	/* PCI error interrupt */
135 	uint32_t	unknown_fatal;	/* unknown fatal errors */
136 
137 	/*
138 	 * PCI Configuration space staus register
139 	 */
140 	uint32_t	pci_data_parity_err;	/* Data parity err */
141 	uint32_t	pci_signal_target_abort;
142 	uint32_t	pci_rcvd_target_abort;
143 	uint32_t	pci_rcvd_master_abort;
144 	uint32_t	pci_signal_system_err;
145 	uint32_t	pci_det_parity_err;
146 
147 	/*
148 	 * MIB II variables
149 	 */
150 	uint64_t	rbytes64;	/* # bytes received */
151 	uint64_t	obytes64;	/* # bytes transmitted */
152 	uint32_t	multircv;	/* # multicast packets received */
153 	uint32_t	multixmt;	/* # multicast packets for xmit */
154 	uint32_t	brdcstrcv;	/* # broadcast packets received */
155 	uint32_t	brdcstxmt;	/* # broadcast packets for xmit */
156 	uint32_t	norcvbuf;	/* # rcv packets discarded */
157 	uint32_t	noxmtbuf;	/* # xmit packets discarded */
158 
159 	uint32_t	pmcap;		/* power management */
160 
161 	/*
162 	 * Link Status
163 	 */
164 	uint32_t	link_up;
165 	uint32_t	link_duplex;
166 } stats_t;
167 
168 #define	HSTAT(erip, x)		erip->stats.x++;
169 #define	HSTATN(erip, x, n)	erip->stats.x += n;
170 
171 
172 #define	RX_BCOPY_MAX		704	/* bcopy for packets < 704 bytes */
173 
174 /*
175  * Per-Stream instance state information.
176  *
177  * Each instance is dynamically allocated at open() and free'd
178  * at close().  Each per-Stream instance points to at most one
179  * per-device structure using the sb_erip field.  All instances
180  * are threaded together into one list of active instances
181  * ordered on minor device number.
182  */
183 
184 #define	NMCFILTER_BITS	256		/* # of multicast filter bits */
185 
186 
187 /*
188  * Maximum number of receive descriptors posted to the chip.
189  */
190 #define	ERI_RPENDING		(erip->rpending)
191 
192 /*
193  * Maximum number of transmit descriptors for lazy reclaim.
194  */
195 #define	ERI_TPENDING	(erip->tpending)
196 
197 /*
198  * Return the address of an adjacent descriptor in the given ring.
199  */
200 #define	NEXTRMD(erip, rmdp)	(((rmdp) + 1) == (erip)->rmdlimp ?	\
201 	(erip)->rmdp : ((rmdp) + 1))
202 #define	NEXTTMD(erip, tmdp)	(((tmdp) + 1) == (erip)->eri_tmdlimp ?	\
203 	(erip)->eri_tmdp : ((tmdp) + 1))
204 #define	PREVTMD(erip, tmdp)	((tmdp) == (erip)->eri_tmdp ?		\
205 	((erip)->eri_tmdlimp - 1) : ((tmdp) - 1))
206 
207 #define	MSECOND(t)	t
208 #define	SECOND(t)	t*1000
209 #define	ERI_TICKS	MSECOND(100)
210 
211 #define	ERI_NTRIES_LOW		(SECOND(5)/ERI_TICKS)   /* 5 Seconds */
212 #define	ERI_NTRIES_HIGH		(SECOND(5)/ERI_TICKS)   /* 5 Seconds */
213 #define	ERI_NTRIES_LOW_10	(SECOND(2)/ERI_TICKS)   /* 2 Seconds */
214 #define	ERI_LINKDOWN_TIME	(SECOND(2)/ERI_TICKS)   /* 2 Seconds */
215 
216 
217 /*
218  * ERI ASIC Revision Numbers
219  */
220 #define	ERI_ERIREV_1_0	0x1
221 
222 /*
223  * Link poll interval for detecting change of transceivers
224  */
225 #define	ERI_LINKCHECK_TIMER	SECOND(3)
226 
227 /*
228  * Parallel detection Fault restart timer
229  */
230 #define	ERI_P_FAULT_TIMER	SECOND(3)
231 
232 /*
233  * Check rmac hang restart timer
234  */
235 #define	ERI_CHECK_HANG_TIMER	MSECOND(400)
236 #define	ERI_RMAC_HANG_WORKAROUND
237 
238 /*
239  * undefine ERI_PM_WORKAROUND this time. With ERI_PM_WORKAROUND defined,
240  * each non_fatal error causes pci clock to go up for 30 seconds. Therefore,
241  * no TXMAC_UNDERRUN or excessive RXFIFO_OVERFLOW should happen.
242  */
243 
244 
245 /*
246  * Link bringup modes
247  */
248 #define	ERI_AUTO_BRINGUP	0
249 #define	ERI_FORCED_BRINGUP	1
250 
251 /*
252  * Transceivers selected for use by the driver.
253  */
254 #define	NO_XCVR		2
255 #define	INTERNAL_XCVR	0
256 #define	EXTERNAL_XCVR	1
257 
258 /*
259  * states for manually creating the link down condition
260  */
261 #define	ERI_LINKDOWN_OK		0
262 #define	ERI_FORCE_LINKDOWN	1
263 #define	ERI_LINKDOWN_STARTED	2
264 #define	ERI_LINKDOWN_DONE	3
265 
266 /*
267  * states for bringing up the link in auto-negotiation mode
268  */
269 #define	ERI_HWAN_TRY		0 /* Try Hardware autonegotiation */
270 #define	ERI_HWAN_INPROGRESS	1 /* Hardware autonegotiation in progress */
271 #define	ERI_HWAN_SUCCESFUL	2 /* Hardware autonegotiation succesful */
272 #define	ERI_HWAN_FAILED		3 /* Hardware autonegotiation failed */
273 
274 /*
275  * states for resetting the transceiver
276  */
277 #define	RESET_TO_BE_ISSUED	0 /* Reset command to be issued to the PHY */
278 #define	RESET_ISSUED		1 /* Reset command has been issued */
279 #define	ISOLATE_ISSUED		2 /* Isolate-remove command has been issued */
280 
281 /*
282  * ERI Supported PHY devices
283  * ERI ASIC supports a built in Gigabit Serial LInk Interface and MII
284  * External SERDES interfaces with shared pins.
285  * On some product implementations, the built-in Serial Link may not be present
286  * either because the Serial Link circuitry does not work or because the product
287  * needs to use only the MII interface.
288  * When both the Serial Link and MII PHY's are present, the driver normally
289  * tries to bring up both the links. If both of them come up, it will select the
290  * link defined by the "eri_default_link" variable by default.
291  * The user may use the configuration variable
292  * eri_select_link to manually select
293  * either the Serial Link or the MII PHY to be used.
294  */
295 
296 /*
297  * Values for the eri_serial_link field
298  */
299 #define	ERI_SERIAL_LINK_NOT_PRESENT	0
300 #define	ERI_SERIAL_LINK_PRESENT		1
301 
302 /*
303  * Values for the eri_non-serial-link field
304  */
305 #define	ERI_NO_SHARED_PIN_PHY		0
306 #define	ERI_MII_PRESENT			1
307 #define	ERI_SERDES_PRESENT		2
308 
309 /*
310  * Values for the default selection when both the serial link and
311  * the MII links are present.
312  */
313 #define	ERI_DEFAULT_SERIAL_LINK	0
314 #define	ERI_DEFAULT_MII_LINK	1
315 
316 /*
317  * Values for the eri_select_link field to manually select the PHY
318  */
319 #define	ERI_AUTO_PHY			0	/* Select PHY automatically */
320 #define	ERI_USE_SERIAL_LINK		1	/* Select serial-link */
321 #define	ERI_USE_NON_SERIAL_LINK		2	/* Select non-serial-link */
322 
323 /*
324  * eri_linkup_state" definitions
325  */
326 #define	ERI_START_LINK_BRINGUP	0
327 #define	ERI_SERIAL_LINK_BRINGUP	1
328 #define	ERI_SERDES_LINK_BRINGUP	2
329 #define	ERI_MII_LINK_BRINGUP	3
330 #define	ERI_DEFAULT_LINK_BRINGUP	4
331 #define	ERI_ALT_LINK_BRINGUP	5
332 
333 /*
334  * structure used to detect tx hang condition
335  */
336 struct	erisave {
337 	ulong_t	starts;		  /* # of tx packets posted to the hw */
338 	uint64_t reclaim_opackets; /* # of tx packets reclaimed */
339 };
340 
341 /*
342  * ERI Device Channel instance state information.
343  *
344  * Each instance is dynamically allocated on first attach.
345  */
346 struct	eri {
347 	mac_handle_t		mh;		/* GLDv3 handle */
348 	dev_info_t		*dip;		/* associated dev_info */
349 	uint_t			instance;	/* instance */
350 
351 	int			pci_mode;	/* sbus/pci device (future) */
352 	int			cpci_mode;	/* compact pci dev (future) */
353 	int			low_power_mode; /* E* (low power) */
354 	int			asic_rev;	/* ERI ASIC rev no. */
355 	int			board_rev;	/* ERI ASIC rev no. */
356 	int			burstsizes;	/* binary encoded val */
357 	int			pagesize;	/* btop(9f) */
358 	uint32_t		rxfifo_size;	/* RX FIFO size */
359 
360 	int			rpending;	/* Max.no. of RX bufs post */
361 	int			tpending;	/* Max.no. of tX bufs post */
362 	int			tx_cur_cnt;	/* # of packets for int_me */
363 
364 	uint_t			multi_refcnt;
365 	boolean_t		promisc;
366 
367 	int			mifpoll_enable;
368 	int			frame_enable;
369 	int			lance_mode_enable;
370 	int			ngu_enable;
371 	int			link_pulse_disabled;
372 	int			xmit_dma_mode;
373 	int			rcv_dma_mode;
374 	uint8_t			ouraddr[ETHERADDRL];	/* unicast address */
375 	uint32_t		flags;		/* misc. flags */
376 	uint32_t		alloc_flag;	/* Buff alloc. status flags */
377 	boolean_t		wantw;		/* xmit: out of resources */
378 
379 	uint16_t		ladrf[NMCFILTER_BITS/16]; /* Multicast filter */
380 	uint16_t		ladrf_refcnt[NMCFILTER_BITS];
381 
382 	volatile struct	global	*globregp;	/* ERI global regs */
383 	volatile struct	etx	*etxregp;	/* ERI ETX regs */
384 	volatile struct	erx	*erxregp;	/* ERI ERX regs */
385 
386 	volatile struct	bmac	*bmacregp;	/* MAC regs */
387 	volatile struct	mif	*mifregp;	/* ERI transceiver */
388 	volatile struct	pcslink	*pcsregp;	/* ERI PCS regs */
389 
390 	uint32_t		*sw_reset_reg;
391 
392 	uint32_t		rx_kick;	/* RX kick register val */
393 	uint32_t		rx_completion;	/* RX completion reg val */
394 #ifdef	RCV_OVRFLOW_CORRUPTION_BUG
395 	uint32_t		rx_ovrflpks;	/* RX recompute checksum */
396 #endif
397 	uint32_t		tx_kick;	/* TX kick register val */
398 	uint32_t		tx_completion;	/* TX completion reg val */
399 
400 	struct	rmd		*rmdp;		/* rcv descript  ring start */
401 	struct	rmd		*rmdlimp;	/* rcv  descript ring end */
402 	struct	eri_tmd		*eri_tmdp;	/* xmit descript ring start */
403 	struct	eri_tmd		*eri_tmdlimp;	/* xmit descript ring end */
404 	volatile struct	rmd	*rnextp;	/* next chip rmd */
405 	volatile struct	rmd	*rlastp;	/* last free rmd */
406 	volatile struct	eri_tmd	*tnextp;	/* next free tmd */
407 
408 	volatile struct	eri_tmd	*tcurp;	/* nxt tmd to reclaim(used) */
409 	/*
410 	 * these are handles for the dvma resources reserved
411 	 * by dvma_reserve
412 	 */
413 	ddi_dma_handle_t	eri_dvmarh;	/* dvma recv handle */
414 
415 	/*
416 	 * these are used if dvma reserve fails, and we have to fall
417 	 * back on the older ddi_dma_addr_setup routines
418 	 */
419 	ddi_dma_handle_t	ndmarh[ERI_RMDMAX];
420 
421 	ddi_dma_handle_t	tbuf_handle;
422 	ddi_acc_handle_t	tbuf_acch;
423 	caddr_t			tbuf_kaddr;
424 	uint32_t		tbuf_ioaddr;
425 
426 	int			rcv_handle_cnt;
427 
428 	int			rx_reset_issued;
429 	int			tx_reset_issued;
430 	int			rxmac_reset_issued;
431 	int			txmac_reset_issued;
432 
433 	int			global_reset_issued;
434 	uint32_t		rpending_mask;
435 	int			rmdmax_mask;
436 	int			init_macregs;
437 
438 	int			phyad;	/* addr of the PHY in use */
439 	int			xcvr;  /* current PHY in use */
440 
441 	int			openloop_autoneg;
442 
443 	uint16_t		mif_config;
444 	uint16_t		mif_mask;
445 
446 	uint32_t		tx_config;
447 
448 	uint32_t		vendor_id;	/* Vendor ID	*/
449 	uint16_t		device_id;	/* Device Model	*/
450 	uint16_t		device_rev;	/* Device Rev.	*/
451 	uint32_t		phy_address;	/* PHY Address	*/
452 	uint32_t		xcvr_status;	/* xcvr_status	*/
453 	uint32_t		xcvr_state;	/* xcvr_state	*/
454 	uint32_t		bringup_mode;	/* Bringup Mode	*/
455 	uint32_t		speed;		/* Current speed */
456 	uint32_t		duplex;		/* Xcvr Duplex	*/
457 	uint32_t		capability;	/* Xcvr Capability */
458 
459 	uint16_t		mii_control;
460 	uint16_t		mii_status;
461 	uint16_t		mii_anar;
462 	uint16_t		mii_lpanar;
463 
464 	int			autoneg;
465 	int			force_linkdown;
466 	int			mode;
467 
468 	int			linkup_10;
469 	int			pace_count;	/* pacing pkt count */
470 
471 	int			nlasttries;
472 	int			ntries;
473 	int			delay;
474 	int			linkup_attempts;
475 
476 	int			polling_on;
477 	int			mifpoll_data;
478 	int			mifpoll_flag; /* indicates MIF intr */
479 
480 	int			pauseTX;	/* pcs link-pause TX enable */
481 	int			pauseRX;	/* pcs link-pause RX enable */
482 	int			macfdx;	/* mac full-duplex mode */
483 	timeout_id_t		timerid;	/* timer id for links */
484 	int			linkup_cnt;
485 
486 	uint16_t		aner;	/* MII ANER register */
487 
488 	int			linkup;		/* selected link status */
489 	int			linkup_state; /* link bringup state */
490 	int			linkup_changed; /* link bringup state */
491 
492 	int			linkcheck;
493 	caddr_t			g_nd;	/* head of the */
494 						/* named dispatch table */
495 
496 	ddi_device_acc_attr_t	dev_attr;
497 	ddi_iblock_cookie_t	cookie;	/* interrupt cookie */
498 	ddi_acc_handle_t	globregh;   /* ERI global regs */
499 	ddi_acc_handle_t	etxregh;    /* ERI ETX regs */
500 	ddi_acc_handle_t	erxregh;    /* ERI ERX regs */
501 	ddi_acc_handle_t	bmacregh;   /* BigMAC registers */
502 	ddi_acc_handle_t	mifregh;    /* ERI transceiver */
503 	ddi_acc_handle_t	pcsregh;    /* ERI PCS regs */
504 
505 	ddi_acc_handle_t	sw_reset_regh;	/* ERI Reset Reg */
506 
507 	ddi_dma_cookie_t	md_c;	/* trmd dma cookie */
508 	ddi_acc_handle_t	mdm_h;	/* trmd memory handle */
509 	ddi_dma_handle_t	md_h;	/* trmdp dma handle */
510 
511 	ddi_acc_handle_t	pci_config_handle; /* ERI PCI config */
512 
513 	/*
514 	 * DDI dma handle, kernel virtual base,
515 	 * and io virtual base of IOPB area.
516 	 */
517 	ddi_dma_handle_t	iopbhandle;
518 	uintptr_t		iopbkbase;
519 	uintptr_t		iopbiobase;
520 	kstat_t			*ksp;		/* kstat pointer */
521 
522 	kmutex_t		xmitlock;	/* protect xmit-side fields */
523 	kmutex_t		xcvrlock;	/* */
524 	kmutex_t		intrlock;	/* protect intr-side fields */
525 	kmutex_t		linklock;	/* protect link-side fields */
526 
527 	mblk_t		*tmblkp[ERI_TMDMAX]; /* mblks assoc with TMD */
528 	mblk_t		*rmblkp[ERI_RMDMAX]; /* mblks assoc with RMD */
529 	param_t		param_arr[ERI_PARAM_CNT];
530 
531 	struct	stats stats;	/* kstats */
532 
533 	/*
534 	 * Check if transmitter is hung
535 	 */
536 	uint32_t	starts;
537 	uint32_t	txhung;
538 	struct		erisave erisave;
539 
540 	uint64_t	ifspeed_old;
541 
542 #ifdef ERI_RMAC_HANG_WORKAROUND
543 	uint32_t	check_rmac_hang;
544 	uint32_t	check2_rmac_hang;
545 	uint32_t	rxfifo_wr_ptr;
546 	uint32_t	rxfifo_rd_ptr;
547 	uint32_t	rxfifo_wr_ptr_c;
548 	uint32_t	rxfifo_rd_ptr_c;
549 #endif
550 	uint32_t	tx_int_me;
551 };
552 
553 /*
554  * LADRF bit array manipulation macros.  These are for working within the
555  * array of words defined by erip->ladrf, converting a bit (0-255) into
556  * the index and offset in the ladrf bit array.  Note that the array is
557  * provided in "Big Endian" order.
558  */
559 #define	LADRF_MASK(bit)		(1 << ((bit) % 16))
560 #define	LADRF_WORD(erip, bit)	erip->ladrf[(15 - ((bit) / 16))]
561 #define	LADRF_SET(erip, bit)	(LADRF_WORD(erip, bit) |= LADRF_MASK(bit))
562 #define	LADRF_CLR(erip, bit)	(LADRF_WORD(erip, bit) &= ~LADRF_MASK(bit))
563 
564 /*
565  * ERI IOCTLS.
566  * Change : TODO : MBE
567  */
568 #define	ERIIOC		('G' << 8)
569 #define	ERI_SET_LOOP_MODE	(ERIIOC|1)	/* Set Rio Loopback mode */
570 #define	ERI_GET_LOOP_MODE	(ERIIOC|2)	/* Get Rio Loopback modes */
571 #define	ERI_GET_LOOP_IFCNT	(ERIIOC|4)	/* Get Rio IF Count */
572 
573 /*
574  * Loopback modes: For diagnostic testing purposes the ERI card
575  * can be placed in loopback mode.
576  * There are three modes of loopback provided by the driver,
577  * Mac loopback, PCS loopback and Serdes loopback.
578  */
579 #define	ERI_LOOPBACK_OFF		0
580 #define	ERI_MAC_LOOPBACK_ON		1
581 #define	ERI_PCS_LOOPBACK_ON 		2
582 #define	ERI_SER_LOOPBACK_ON 		4
583 typedef struct {
584 	int loopback;
585 } loopback_t;
586 
587 
588 /*
589  * flags
590  * TODO : MBE
591  */
592 #define	ERI_UNKOWN	0x00	/* unknown state	*/
593 #define	ERI_RUNNING	0x01	/* chip is initialized	*/
594 #define	ERI_STARTED	0x02	/* mac layer started */
595 #define	ERI_SUSPENDED	0x08	/* suspended interface	*/
596 #define	ERI_INITIALIZED	0x10	/* interface initialized */
597 #define	ERI_NOTIMEOUTS	0x20	/* disallow timeout rescheduling */
598 #define	ERI_TXINIT	0x40	/* TX Portion Init'ed	*/
599 #define	ERI_RXINIT	0x80	/* RX Portion Init'ed	*/
600 #define	ERI_MACLOOPBACK	0x100	/* device has MAC int lpbk (DIAG) */
601 #define	ERI_SERLOOPBACK	0x200	/* device has SERDES int lpbk (DIAG) */
602 #define	ERI_DLPI_LINKUP	0x400	/* */
603 
604 /*
605  * Mac address flags
606  */
607 #define	ERI_FACTADDR_PRESENT	0x01	/* factory MAC id present */
608 #define	ERI_FACTADDR_USE	0x02	/* use factory MAC id */
609 
610 struct erikstat {
611 	/*
612 	 * Software event stats
613 	 */
614 	struct kstat_named	erik_inits;
615 	struct kstat_named	erik_rx_inits;
616 	struct kstat_named	erik_tx_inits;
617 
618 	struct kstat_named	erik_allocbfail;
619 	struct kstat_named	erik_drop;
620 
621 	/*
622 	 * MAC Control event stats
623 	 */
624 	struct kstat_named	erik_pause_rxcount; /* PAUSE Receive count */
625 	struct kstat_named	erik_pause_oncount;
626 	struct kstat_named	erik_pause_offcount;
627 	struct kstat_named	erik_pause_time_count;
628 
629 	/*
630 	 * MAC TX Event stats
631 	 */
632 	struct kstat_named	erik_txmac_maxpkt_err;
633 	struct kstat_named	erik_defer_timer_exp;
634 	struct kstat_named	erik_peak_attempt_cnt;
635 	struct kstat_named	erik_jab;
636 	struct kstat_named	erik_notmds;
637 	struct kstat_named	erik_tx_hang;
638 
639 	/*
640 	 * MAC RX Event stats
641 	 */
642 	struct kstat_named	erik_no_free_rx_desc; /* no free rx desc. */
643 	struct kstat_named	erik_rx_hang;
644 	struct kstat_named	erik_rx_length_err;
645 	struct kstat_named	erik_rx_code_viol_err;
646 	struct kstat_named	erik_rx_bad_pkts;
647 
648 	/*
649 	 * Fatal errors
650 	 */
651 	struct kstat_named	erik_rxtag_err;
652 
653 	/*
654 	 * Parity error
655 	 */
656 	struct kstat_named	erik_parity_error;
657 
658 	/*
659 	 * PCI fatal error stats
660 	 */
661 	struct kstat_named	erik_pci_error_int;  /* PCI error interrupt */
662 	struct kstat_named	erik_unknown_fatal;	/* unknow fatal error */
663 
664 	/*
665 	 * PCI Configuration space staus register
666 	 */
667 	struct kstat_named	erik_pci_data_parity_err; /* dparity err */
668 	struct kstat_named	erik_pci_signal_target_abort;
669 	struct kstat_named	erik_pci_rcvd_target_abort;
670 	struct kstat_named	erik_pci_rcvd_master_abort;
671 	struct kstat_named	erik_pci_signal_system_err;
672 	struct kstat_named	erik_pci_det_parity_err;
673 
674 
675 	struct kstat_named	erik_pmcap;	/* Power management */
676 };
677 
678 /* TBD: new value ? */
679 #define	ERI_DRAINTIME	(400000)	/* # microseconds xmit drain */
680 
681 #define	ROUNDUP(a, n)	(((a) + ((n) - 1)) & ~((n) - 1))
682 #define	ROUNDUP2(a, n)	(uchar_t *)((((uintptr_t)(a)) + ((n) - 1)) & ~((n) - 1))
683 
684 /*
685  * Xmit/receive buffer structure.
686  * This structure is organized to meet the following requirements:
687  * - hb_buf starts on an ERI_BURSTSIZE boundary.
688  * - eribuf is an even multiple of ERI_BURSTSIZE
689  * - hb_buf[] is large enough to contain max frame (1518) plus
690  *   (3 x ERI_BURSTSIZE) rounded up to the next ERI_BURSTSIZE
691  */
692 /*
693  * #define		ERI_BURSTSIZE	(64)
694  */
695 #define		ERI_BURSTSIZE	(128)
696 #define		ERI_BURSTMASK	(ERIBURSTSIZE - 1)
697 #define		ERI_BUFSIZE	(1728)	/* (ETHERMTU + 228) */
698 #define		ERI_HEADROOM	(34)
699 
700 /* Offset for the first byte in the receive buffer */
701 #define	ERI_FSTBYTE_OFFSET	2
702 #define	ERI_CKSUM_OFFSET	14
703 
704 
705 #define	ERI_PMCAP_NONE	0
706 #define	ERI_PMCAP_4MHZ	4
707 
708 #endif	/* _KERNEL */
709 
710 #ifdef	__cplusplus
711 }
712 #endif
713 
714 #endif	/* _SYS_ERI_H */
715