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Searched refs:DP_TP_CTL_LINK_TRAIN_PAT1 (Results 1 – 3 of 3) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Dintel_ddi.c209 DP_TP_CTL_LINK_TRAIN_PAT1 | in hsw_fdi_link_train()
266 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; in hsw_fdi_link_train()
1085 val |= DP_TP_CTL_LINK_TRAIN_PAT1; in intel_ddi_post_disable()
1216 val |= DP_TP_CTL_LINK_TRAIN_PAT1; in intel_ddi_prepare_link_retrain()
1225 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; in intel_ddi_prepare_link_retrain()
H A Dintel_dp.c1940 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; in intel_dp_set_link_train()
H A Di915_reg.h4882 #define DP_TP_CTL_LINK_TRAIN_PAT1 (0<<8) macro