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Searched refs:CACHE_MODE_1 (Results 1 – 2 of 2) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Dintel_pm.c4222 I915_WRITE(CACHE_MODE_1, in haswell_init_clock_gating()
4320 I915_WRITE(CACHE_MODE_1, in ivybridge_init_clock_gating()
4406 I915_WRITE(CACHE_MODE_1, in valleyview_init_clock_gating()
H A Di915_reg.h936 #define CACHE_MODE_1 0x7004 /* IVB+ */ macro