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Searched refs:CACHE_MODE_0 (Results 1 – 4 of 4) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Di915_suspend.c375 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); in i915_save_state()
422 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000); in i915_restore_state()
H A Dintel_pm.c3996 I915_WRITE(CACHE_MODE_0, in ironlake_init_clock_gating()
4076 I915_WRITE(CACHE_MODE_0, in gen6_init_clock_gating()
4444 I915_WRITE(CACHE_MODE_0, in g4x_init_clock_gating()
H A Dintel_ringbuffer.c587 I915_WRITE(CACHE_MODE_0, in init_render_ring()
H A Di915_reg.h919 #define CACHE_MODE_0 0x02120 /* 915+ only */ macro