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Searched refs:CACHE_LINE_SIZE (Results 1 – 11 of 11) sorted by relevance

/illumos-gate/usr/src/uts/common/fs/zfs/sys/
H A Daggsum.h28 #define CACHE_LINE_SIZE 64 macro
35 } aggsum_bucket_t __aligned(CACHE_LINE_SIZE);
/illumos-gate/usr/src/boot/sys/sys/
H A D_mutex.h62 } __aligned(CACHE_LINE_SIZE);
H A D_rwlock.h60 } __aligned(CACHE_LINE_SIZE);
/illumos-gate/usr/src/compat/bhyve/amd64/machine/
H A Dparam.h39 #define CACHE_LINE_SIZE 64 macro
/illumos-gate/usr/src/boot/sys/i386/include/
H A Dparam.h86 #define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT) macro
/illumos-gate/usr/src/boot/sys/amd64/include/
H A Dparam.h93 #define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT) macro
/illumos-gate/usr/src/uts/intel/io/vmm/
H A Dvmm_cpuid.c590 regs[1] = func > 0 ? CACHE_LINE_SIZE - 1 : 0; in legacy_emulate_cpuid()
/illumos-gate/usr/src/boot/include/netinet/
H A Din_pcb.h430 } __aligned(CACHE_LINE_SIZE);
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/device/
H A Dlm_sp.c255 …rx->cache_line_alignment_log_size = (u8_t)LOG2(CACHE_LINE_SIZE/* TODO mm_get_cache_line_alignment(… in lm_eth_init_client_init_rx_data()
300 …>params.l2_cli_con_params[cid].lah_size - (u16_t)pdev->params.rcv_buffer_offset - CACHE_LINE_SIZE); in lm_eth_init_client_init_rx_data()
307 …_le16(MAX_L2_CLI_BUFFER_SIZE(pdev, cid) - (u16_t)pdev->params.rcv_buffer_offset - CACHE_LINE_SIZE); in lm_eth_init_client_init_rx_data()
H A Dlm_pf.c767 …client_init_data_virt->rx.cache_line_alignment_log_size = (u8_t)LOG2(CACHE_LINE_SIZE/* TODO mm_get… in lm_pf_init_vf_client_init_data()
/illumos-gate/usr/src/uts/common/io/bnxe/577xx/drivers/common/lm/include/
H A Dlm5710.h333 #define CACHE_LINE_SIZE (CACHE_LINE_SIZE_MASK + 1) macro
769 …t + ETHERNET_PACKET_HEADER_SIZE+ ETHERNET_VLAN_TAG_SIZE + ETHERNET_LLC_SNAP_SIZE + CACHE_LINE_SIZE)