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Searched refs:CACHE_ALIGN (Results 1 – 7 of 7) sorted by relevance

/illumos-gate/usr/src/uts/common/io/dmfe/
H A Ddmfe.h181 #define CACHE_ALIGN (3 << 14) /* 32 Dwords */ macro
H A Ddmfe_main.c113 static uint32_t dmfe_bus_modes = TX_POLL_INTVL | CACHE_ALIGN;
/illumos-gate/usr/src/uts/intel/io/dnet/
H A Ddnet.h137 #define CACHE_ALIGN 0x04000UL /* 8 long word boundary align */ macro
H A Ddnet.c912 CACHE_ALIGN | BURST_SIZE); /* CSR0 */ in dnet_chip_init()
/illumos-gate/usr/src/uts/common/inet/
H A Dip.h1225 #define CACHE_ALIGN(align_struct) P2ROUNDUP(sizeof (struct align_struct),\ macro
1234 char phyint_list_filler[CACHE_ALIGN(_phyint_list_s_)];
1363 char illif_filler[CACHE_ALIGN(_ill_if_s_)];
1390 char ill_g_head_filler[CACHE_ALIGN(_ill_g_head_s_)];
/illumos-gate/usr/src/uts/intel/io/amd8111s/
H A Damd8111s_hw.h518 #define CACHE_ALIGN B4_MASK macro
/illumos-gate/usr/src/uts/common/inet/ip/
H A Dipclassifier.c315 char itcu_filler[CACHE_ALIGN(conn_s)];