xref: /illumos-gate/usr/src/uts/common/io/nxge/npi/npi.h (revision 2d6eb4a5)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _NPI_H
27 #define	_NPI_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 #include <nxge_common_impl.h>
34 
35 typedef	uint32_t			npi_status_t;
36 
37 /* Common Block ID */
38 
39 #define	MAC_BLK_ID			0x1
40 #define	TXMAC_BLK_ID			0x2
41 #define	RXMAC_BLK_ID			0x3
42 #define	MIF_BLK_ID			0x4
43 #define	IPP_BLK_ID			0x5
44 #define	TXC_BLK_ID			0x6
45 #define	TXDMA_BLK_ID			0x7
46 #define	RXDMA_BLK_ID			0x8
47 #define	ZCP_BLK_ID			0x9
48 #define	ESPC_BLK_ID			0xa
49 #define	FFLP_BLK_ID			0xb
50 #define	PHY_BLK_ID			0xc
51 #define	ETHER_SERDES_BLK_ID		0xd
52 #define	PCIE_SERDES_BLK_ID		0xe
53 #define	VIR_BLK_ID			0xf
54 #define	XAUI_BLK_ID			0x10
55 #define	XFP_BLK_ID			0x11
56 
57 /* Common HW error code */
58 /* HW unable to exit from reset state. */
59 #define	RESET_FAILED			0x81
60 
61 /* Write operation failed on indirect write. */
62 #define	WRITE_FAILED			0x82
63 /* Read operation failed on indirect read.	 */
64 #define	READ_FAILED			0x83
65 
66 /* Error code boundary */
67 
68 #define	COMMON_SW_ERR_START		0x40
69 #define	COMMON_SW_ERR_END		0x4f
70 #define	BLK_SPEC_SW_ERR_START		0x50
71 #define	BLK_SPEC_SW_ERR_END		0x7f
72 #define	COMMON_HW_ERR_START		0x80
73 #define	COMMON_HW_ERR_END		0x8f
74 #define	BLK_SPEC_HW_ERR_START		0x90
75 #define	BLK_SPEC_HW_ERR_END		0xbf
76 
77 #define	IS_PORT				0x00100000
78 #define	IS_CHAN				0x00200000
79 
80 /* Common SW errors code */
81 
82 #define	PORT_INVALID			0x41	/* Invalid port number */
83 #define	CHANNEL_INVALID			0x42	/* Invalid dma channel number */
84 #define	OPCODE_INVALID			0x43	/* Invalid opcode */
85 #define	REGISTER_INVALID		0x44	/* Invalid register number */
86 #define	COUNTER_INVALID			0x45	/* Invalid counter number */
87 #define	CONFIG_INVALID			0x46	/* Invalid config input */
88 #define	LOGICAL_PAGE_INVALID		0x47	/* Invalid logical page # */
89 #define	VLAN_INVALID			0x48	/* Invalid Vlan ID */
90 #define	RDC_TAB_INVALID			0x49	/* Invalid RDC Group Number */
91 #define	LOCATION_INVALID		0x4a	/* Invalid Entry Location */
92 
93 #define	NPI_SUCCESS			0		/* Operation succeed */
94 #define	NPI_FAILURE			0x80000000	/* Operation failed */
95 
96 #define	NPI_CNT_CLR_VAL			0
97 
98 /*
99  * Block identifier starts at bit 8.
100  */
101 #define	NPI_BLOCK_ID_SHIFT		8
102 
103 /*
104  * Port, channel and misc. information starts at bit 12.
105  */
106 #define	NPI_PORT_CHAN_SHIFT			12
107 
108 /*
109  * Software Block specific error codes start at 0x50.
110  */
111 #define	NPI_BK_ERROR_START		0x50
112 
113 /*
114  * Hardware block specific error codes start at 0x90.
115  */
116 #define	NPI_BK_HW_ER_START		0x90
117 
118 /* Structures for register tracing */
119 
120 typedef struct _rt_buf {
121 	uint32_t	ctl_addr;
122 	uint32_t	align;
123 	uint32_t	val_h32;
124 	uint32_t	val_l32;
125 	char		name[16];
126 } rt_buf_t;
127 
128 /*
129  * Control Address field format
130  *
131  * Bit 0 - 23: Address
132  * Bit 24 - 25: Function Number
133  * Bit 26 - 29: Instance Number
134  * Bit 30: Read/Write Direction bit
135  * Bit 31: Invalid bit
136  */
137 
138 #define	MAX_RTRACE_ENTRIES	1024
139 #define	MAX_RTRACE_IOC_ENTRIES	64
140 #define	TRACE_ADDR_MASK		0x00FFFFFF
141 #define	TRACE_FUNC_MASK		0x03000000
142 #define	TRACE_INST_MASK		0x3C000000
143 #define	TRACE_CTL_WR		0x40000000
144 #define	TRACE_CTL_INVALID	0x80000000
145 #define	TRACE_FUNC_SHIFT	24
146 #define	TRACE_INST_SHIFT	26
147 #define	MSG_BUF_SIZE		1024
148 
149 
150 typedef struct _rtrace {
151 	uint16_t	next_idx;
152 	uint16_t	last_idx;
153 	boolean_t	wrapped;
154 	uint64_t	align;
155 	rt_buf_t	buf[MAX_RTRACE_ENTRIES];
156 } rtrace_t;
157 
158 typedef struct _err_inject {
159 	uint8_t		blk_id;
160 	uint8_t		chan;
161 	uint32_t	err_id;
162 	uint32_t	control;
163 } err_inject_t;
164 
165 /* Configuration options */
166 typedef enum config_op {
167 	DISABLE = 0,
168 	ENABLE,
169 	INIT
170 } config_op_t;
171 
172 /* I/O options */
173 typedef enum io_op {
174 	OP_SET = 0,
175 	OP_GET,
176 	OP_UPDATE,
177 	OP_CLEAR
178 } io_op_t;
179 
180 /* Counter options */
181 typedef enum counter_op {
182 	SNAP_STICKY = 0,
183 	SNAP_ACCUMULATE,
184 	CLEAR
185 } counter_op_t;
186 
187 /* NPI attribute */
188 typedef struct _npi_attr_t {
189 	uint32_t type;
190 	uint32_t idata[16];
191 	uint32_t odata[16];
192 } npi_attr_t;
193 
194 /* NPI Handle */
195 typedef	struct	_npi_handle_function {
196 	uint16_t		instance;
197 	uint16_t		function;
198 } npi_handle_function_t;
199 
200 /* NPI Handle */
201 typedef	struct	_npi_handle {
202 	npi_reg_handle_t	regh;
203 	npi_reg_ptr_t		regp;
204 	boolean_t		is_vraddr; /* virtualization region address */
205 	npi_handle_function_t	function;
206 	void * nxgep;
207 } npi_handle_t;
208 
209 /* NPI Counter */
210 typedef struct _npi_counter_t {
211 	uint32_t id;
212 	char *name;
213 	uint32_t val;
214 } npi_counter_t;
215 
216 /*
217  * Commmon definitions for NPI RXDMA and TXDMA functions.
218  */
219 typedef struct _dma_log_page {
220 	uint8_t			page_num;
221 	boolean_t		valid;
222 	uint8_t			func_num;
223 	uint64_t		mask;
224 	uint64_t		value;
225 	uint64_t		reloc;
226 } dma_log_page_t, *p_dma_log_page_t;
227 
228 extern	rtrace_t npi_rtracebuf;
229 void npi_rtrace_buf_init(rtrace_t *);
230 void npi_rtrace_update(npi_handle_t, boolean_t, rtrace_t *,
231     uint32_t, uint64_t);
232 void npi_trace_update(npi_handle_t, boolean_t, rtrace_t *,
233     const char *, uint32_t, uint64_t);
234 void npi_rtrace_buf_init(rtrace_t *);
235 
236 void npi_debug_msg(npi_handle_function_t, uint64_t,
237 	char *, ...);
238 
239 #ifdef	NPI_DEBUG
240 #define	NPI_DEBUG_MSG(params) npi_debug_msg params
241 #else
242 #define	NPI_DEBUG_MSG(params)
243 #endif
244 
245 #define	NPI_ERROR_MSG(params) npi_debug_msg params
246 #define	NPI_REG_DUMP_MSG(params) npi_debug_msg params
247 
248 #ifdef	__cplusplus
249 }
250 #endif
251 
252 #endif	/* _NPI_H */
253