1 /* 2 * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved. 3 */ 4 5 /* 6 * Copyright (c) 2006, 2013, Intel Corporation 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a 9 * copy of this software and associated documentation files (the "Software"), 10 * to deal in the Software without restriction, including without limitation 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 12 * and/or sell copies of the Software, and to permit persons to whom the 13 * Software is furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice (including the next 16 * paragraph) shall be included in all copies or substantial portions of the 17 * Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 25 * SOFTWARE. 26 * 27 * Authors: 28 * Eric Anholt <eric@anholt.net> 29 * 30 */ 31 32 #ifndef _I830_BIOS_H_ 33 #define _I830_BIOS_H_ 34 35 #include "drmP.h" 36 37 #pragma pack(1) 38 struct vbt_header { 39 u8 signature[20]; /**< Always starts with 'VBT$' */ 40 u16 version; /**< decimal */ 41 u16 header_size; /**< in bytes */ 42 u16 vbt_size; /**< in bytes */ 43 u8 vbt_checksum; 44 u8 reserved0; 45 u32 bdb_offset; /**< from beginning of VBT */ 46 u32 aim_offset[4]; /**< from beginning of VBT */ 47 } __attribute__((packed)); 48 #pragma pack() 49 50 struct bdb_header { 51 u8 signature[16]; /**< Always 'BIOS_DATA_BLOCK' */ 52 u16 version; /**< decimal */ 53 u16 header_size; /**< in bytes */ 54 u16 bdb_size; /**< in bytes */ 55 }; 56 57 /* strictly speaking, this is a "skip" block, but it has interesting info */ 58 #pragma pack(1) 59 struct vbios_data { 60 u8 type; /* 0 == desktop, 1 == mobile */ 61 u8 relstage; 62 u8 chipset; 63 u8 lvds_present:1; 64 u8 tv_present:1; 65 u8 rsvd2:6; /* finish byte */ 66 u8 rsvd3[4]; 67 u8 signon[155]; 68 u8 copyright[61]; 69 u16 code_segment; 70 u8 dos_boot_mode; 71 u8 bandwidth_percent; 72 u8 rsvd4; /* popup memory size */ 73 u8 resize_pci_bios; 74 u8 rsvd5; /* is crt already on ddc2 */ 75 } __attribute__((packed)); 76 #pragma pack() 77 78 /* 79 * There are several types of BIOS data blocks (BDBs), each block has 80 * an ID and size in the first 3 bytes (ID in first, size in next 2). 81 * Known types are listed below. 82 */ 83 #define BDB_GENERAL_FEATURES 1 84 #define BDB_GENERAL_DEFINITIONS 2 85 #define BDB_OLD_TOGGLE_LIST 3 86 #define BDB_MODE_SUPPORT_LIST 4 87 #define BDB_GENERIC_MODE_TABLE 5 88 #define BDB_EXT_MMIO_REGS 6 89 #define BDB_SWF_IO 7 90 #define BDB_SWF_MMIO 8 91 #define BDB_DOT_CLOCK_TABLE 9 92 #define BDB_MODE_REMOVAL_TABLE 10 93 #define BDB_CHILD_DEVICE_TABLE 11 94 #define BDB_DRIVER_FEATURES 12 95 #define BDB_DRIVER_PERSISTENCE 13 96 #define BDB_EXT_TABLE_PTRS 14 97 #define BDB_DOT_CLOCK_OVERRIDE 15 98 #define BDB_DISPLAY_SELECT 16 99 /* 17 rsvd */ 100 #define BDB_DRIVER_ROTATION 18 101 #define BDB_DISPLAY_REMOVE 19 102 #define BDB_OEM_CUSTOM 20 103 #define BDB_EFP_LIST 21 /* workarounds for VGA hsync/vsync */ 104 #define BDB_SDVO_LVDS_OPTIONS 22 105 #define BDB_SDVO_PANEL_DTDS 23 106 #define BDB_SDVO_LVDS_PNP_IDS 24 107 #define BDB_SDVO_LVDS_POWER_SEQ 25 108 #define BDB_TV_OPTIONS 26 109 #define BDB_EDP 27 110 #define BDB_LVDS_OPTIONS 40 111 #define BDB_LVDS_LFP_DATA_PTRS 41 112 #define BDB_LVDS_LFP_DATA 42 113 #define BDB_LVDS_BACKLIGHT 43 114 #define BDB_LVDS_POWER 44 115 #define BDB_SKIP 254 /* VBIOS private block, ignore */ 116 117 #pragma pack(1) 118 struct bdb_general_features { 119 /* bits 1 */ 120 u8 panel_fitting:2; 121 u8 flexaim:1; 122 u8 msg_enable:1; 123 u8 clear_screen:3; 124 u8 color_flip:1; 125 126 /* bits 2 */ 127 u8 download_ext_vbt:1; 128 u8 enable_ssc:1; 129 u8 ssc_freq:1; 130 u8 enable_lfp_on_override:1; 131 u8 disable_ssc_ddt:1; 132 u8 rsvd7:1; 133 u8 display_clock_mode:1; 134 u8 rsvd8:1; /* finish byte */ 135 136 /* bits 3 */ 137 u8 disable_smooth_vision:1; 138 u8 single_dvi:1; 139 u8 rsvd9:1; 140 u8 fdi_rx_polarity_inverted:1; 141 u8 rsvd10:4; /* finish byte */ 142 143 /* bits 4 */ 144 u8 legacy_monitor_detect; 145 146 /* bits 5 */ 147 u8 int_crt_support:1; 148 u8 int_tv_support:1; 149 u8 int_efp_support:1; 150 u8 dp_ssc_enb:1; /* PCH attached eDP supports SSC */ 151 u8 dp_ssc_freq:1; /* SSC freq for PCH attached eDP */ 152 u8 rsvd11:3; /* finish byte */ 153 } __attribute__((packed)); 154 #pragma pack() 155 156 /* pre-915 */ 157 #define GPIO_PIN_DVI_LVDS 0x03 /* "DVI/LVDS DDC GPIO pins" */ 158 #define GPIO_PIN_ADD_I2C 0x05 /* "ADDCARD I2C GPIO pins" */ 159 #define GPIO_PIN_ADD_DDC 0x04 /* "ADDCARD DDC GPIO pins" */ 160 #define GPIO_PIN_ADD_DDC_I2C 0x06 /* "ADDCARD DDC/I2C GPIO pins" */ 161 162 /* Pre 915 */ 163 #define DEVICE_TYPE_NONE 0x00 164 #define DEVICE_TYPE_CRT 0x01 165 #define DEVICE_TYPE_TV 0x09 166 #define DEVICE_TYPE_EFP 0x12 167 #define DEVICE_TYPE_LFP 0x22 168 /* On 915+ */ 169 #define DEVICE_TYPE_CRT_DPMS 0x6001 170 #define DEVICE_TYPE_CRT_DPMS_HOTPLUG 0x4001 171 #define DEVICE_TYPE_TV_COMPOSITE 0x0209 172 #define DEVICE_TYPE_TV_MACROVISION 0x0289 173 #define DEVICE_TYPE_TV_RF_COMPOSITE 0x020c 174 #define DEVICE_TYPE_TV_SVIDEO_COMPOSITE 0x0609 175 #define DEVICE_TYPE_TV_SCART 0x0209 176 #define DEVICE_TYPE_TV_CODEC_HOTPLUG_PWR 0x6009 177 #define DEVICE_TYPE_EFP_HOTPLUG_PWR 0x6012 178 #define DEVICE_TYPE_EFP_DVI_HOTPLUG_PWR 0x6052 179 #define DEVICE_TYPE_EFP_DVI_I 0x6053 180 #define DEVICE_TYPE_EFP_DVI_D_DUAL 0x6152 181 #define DEVICE_TYPE_EFP_DVI_D_HDCP 0x60d2 182 #define DEVICE_TYPE_OPENLDI_HOTPLUG_PWR 0x6062 183 #define DEVICE_TYPE_OPENLDI_DUALPIX 0x6162 184 #define DEVICE_TYPE_LFP_PANELLINK 0x5012 185 #define DEVICE_TYPE_LFP_CMOS_PWR 0x5042 186 #define DEVICE_TYPE_LFP_LVDS_PWR 0x5062 187 #define DEVICE_TYPE_LFP_LVDS_DUAL 0x5162 188 #define DEVICE_TYPE_LFP_LVDS_DUAL_HDCP 0x51e2 189 190 #define DEVICE_CFG_NONE 0x00 191 #define DEVICE_CFG_12BIT_DVOB 0x01 192 #define DEVICE_CFG_12BIT_DVOC 0x02 193 #define DEVICE_CFG_24BIT_DVOBC 0x09 194 #define DEVICE_CFG_24BIT_DVOCB 0x0a 195 #define DEVICE_CFG_DUAL_DVOB 0x11 196 #define DEVICE_CFG_DUAL_DVOC 0x12 197 #define DEVICE_CFG_DUAL_DVOBC 0x13 198 #define DEVICE_CFG_DUAL_LINK_DVOBC 0x19 199 #define DEVICE_CFG_DUAL_LINK_DVOCB 0x1a 200 201 #define DEVICE_WIRE_NONE 0x00 202 #define DEVICE_WIRE_DVOB 0x01 203 #define DEVICE_WIRE_DVOC 0x02 204 #define DEVICE_WIRE_DVOBC 0x03 205 #define DEVICE_WIRE_DVOBB 0x05 206 #define DEVICE_WIRE_DVOCC 0x06 207 #define DEVICE_WIRE_DVOB_MASTER 0x0d 208 #define DEVICE_WIRE_DVOC_MASTER 0x0e 209 210 #define DEVICE_PORT_DVOA 0x00 /* none on 845+ */ 211 #define DEVICE_PORT_DVOB 0x01 212 #define DEVICE_PORT_DVOC 0x02 213 214 #pragma pack(1) 215 struct child_device_config { 216 u16 handle; 217 u16 device_type; 218 u8 device_id[10]; /* ascii string */ 219 u16 addin_offset; 220 u8 dvo_port; /* See Device_PORT_* above */ 221 u8 i2c_pin; 222 u8 slave_addr; 223 u8 ddc_pin; 224 u16 edid_ptr; 225 u8 dvo_cfg; /* See DEVICE_CFG_* above */ 226 u8 dvo2_port; 227 u8 i2c2_pin; 228 u8 slave2_addr; 229 u8 ddc2_pin; 230 u8 capabilities; 231 u8 dvo_wiring;/* See DEVICE_WIRE_* above */ 232 u8 dvo2_wiring; 233 u16 extended_type; 234 u8 dvo_function; 235 } __attribute__((packed)); 236 #pragma pack() 237 238 #pragma pack(1) 239 struct bdb_general_definitions { 240 /* DDC GPIO */ 241 u8 crt_ddc_gmbus_pin; 242 243 /* DPMS bits */ 244 u8 dpms_acpi:1; 245 u8 skip_boot_crt_detect:1; 246 u8 dpms_aim:1; 247 u8 rsvd1:5; /* finish byte */ 248 249 /* boot device bits */ 250 u8 boot_display[2]; 251 u8 child_dev_size; 252 253 /* 254 * Device info: 255 * If TV is present, it'll be at devices[0]. 256 * LVDS will be next, either devices[0] or [1], if present. 257 * On some platforms the number of device is 6. But could be as few as 258 * 4 if both TV and LVDS are missing. 259 * And the device num is related with the size of general definition 260 * block. It is obtained by using the following formula: 261 * number = (block_size - sizeof(bdb_general_definitions))/ 262 * sizeof(child_device_config); 263 */ 264 /* OSOL_i915 struct child_device_config devices[0]; */ 265 } __attribute__((packed)); 266 #pragma pack() 267 268 #pragma pack(1) 269 struct __bdb_general_definitions { 270 /* DDC GPIO */ 271 u8 crt_ddc_gmbus_pin; 272 273 /* DPMS bits */ 274 u8 dpms_acpi:1; 275 u8 skip_boot_crt_detect:1; 276 u8 dpms_aim:1; 277 u8 rsvd1:5; /* finish byte */ 278 279 /* boot device bits */ 280 u8 boot_display[2]; 281 u8 child_dev_size; 282 283 /* 284 * Device info: 285 * If TV is present, it'll be at devices[0]. 286 * LVDS will be next, either devices[0] or [1], if present. 287 * On some platforms the number of device is 6. But could be as few as 288 * 4 if both TV and LVDS are missing. 289 * And the device num is related with the size of general definition 290 * block. It is obtained by using the following formula: 291 * number = (block_size - sizeof(bdb_general_definitions))/ 292 * sizeof(child_device_config); 293 */ 294 struct child_device_config devices[6]; 295 } __attribute__((packed)); 296 #pragma pack() 297 298 #pragma pack(1) 299 struct bdb_lvds_options { 300 u8 panel_type; 301 u8 rsvd1; 302 /* LVDS capabilities, stored in a dword */ 303 u8 pfit_mode:2; 304 u8 pfit_text_mode_enhanced:1; 305 u8 pfit_gfx_mode_enhanced:1; 306 u8 pfit_ratio_auto:1; 307 u8 pixel_dither:1; 308 u8 lvds_edid:1; 309 u8 rsvd2:1; 310 u8 rsvd4; 311 } __attribute__((packed)); 312 #pragma pack() 313 314 #pragma pack(1) 315 /* LFP pointer table contains entries to the struct below */ 316 struct bdb_lvds_lfp_data_ptr { 317 u16 fp_timing_offset; /* offsets are from start of bdb */ 318 u8 fp_table_size; 319 u16 dvo_timing_offset; 320 u8 dvo_table_size; 321 u16 panel_pnp_id_offset; 322 u8 pnp_table_size; 323 } __attribute__((packed)); 324 #pragma pack() 325 326 #pragma pack(1) 327 struct bdb_lvds_lfp_data_ptrs { 328 u8 lvds_entries; /* followed by one or more lvds_data_ptr structs */ 329 struct bdb_lvds_lfp_data_ptr ptr[16]; 330 } __attribute__((packed)); 331 #pragma pack() 332 333 #pragma pack(1) 334 /* LFP data has 3 blocks per entry */ 335 struct lvds_fp_timing { 336 u16 x_res; 337 u16 y_res; 338 u32 lvds_reg; 339 u32 lvds_reg_val; 340 u32 pp_on_reg; 341 u32 pp_on_reg_val; 342 u32 pp_off_reg; 343 u32 pp_off_reg_val; 344 u32 pp_cycle_reg; 345 u32 pp_cycle_reg_val; 346 u32 pfit_reg; 347 u32 pfit_reg_val; 348 u16 terminator; 349 } __attribute__((packed)); 350 #pragma pack() 351 352 #pragma pack(1) 353 struct lvds_dvo_timing { 354 u16 clock; /**< In 10khz */ 355 u8 hactive_lo; 356 u8 hblank_lo; 357 u8 hblank_hi:4; 358 u8 hactive_hi:4; 359 u8 vactive_lo; 360 u8 vblank_lo; 361 u8 vblank_hi:4; 362 u8 vactive_hi:4; 363 u8 hsync_off_lo; 364 u8 hsync_pulse_width; 365 u8 vsync_pulse_width:4; 366 u8 vsync_off:4; 367 u8 rsvd0:6; 368 u8 hsync_off_hi:2; 369 u8 h_image; 370 u8 v_image; 371 u8 max_hv; 372 u8 h_border; 373 u8 v_border; 374 u8 rsvd1:3; 375 u8 digital:2; 376 u8 vsync_positive:1; 377 u8 hsync_positive:1; 378 u8 rsvd2:1; 379 } __attribute__((packed)); 380 #pragma pack() 381 382 #pragma pack(1) 383 struct lvds_pnp_id { 384 u16 mfg_name; 385 u16 product_code; 386 u32 serial; 387 u8 mfg_week; 388 u8 mfg_year; 389 } __attribute__((packed)); 390 #pragma pack() 391 392 #pragma pack(1) 393 struct bdb_lvds_lfp_data_entry { 394 struct lvds_fp_timing fp_timing; 395 struct lvds_dvo_timing dvo_timing; 396 struct lvds_pnp_id pnp_id; 397 } __attribute__((packed)); 398 #pragma pack() 399 400 #pragma pack(1) 401 struct bdb_lvds_lfp_data { 402 struct bdb_lvds_lfp_data_entry data[16]; 403 } __attribute__((packed)); 404 #pragma pack() 405 406 #pragma pack(1) 407 struct aimdb_header { 408 char signature[16]; 409 char oem_device[20]; 410 u16 aimdb_version; 411 u16 aimdb_header_size; 412 u16 aimdb_size; 413 } __attribute__((packed)); 414 #pragma pack() 415 416 #pragma pack(1) 417 struct aimdb_block { 418 u8 aimdb_id; 419 u16 aimdb_size; 420 } __attribute__((packed)); 421 #pragma pack() 422 423 #pragma pack(1) 424 struct vch_panel_data { 425 u16 fp_timing_offset; 426 u8 fp_timing_size; 427 u16 dvo_timing_offset; 428 u8 dvo_timing_size; 429 u16 text_fitting_offset; 430 u8 text_fitting_size; 431 u16 graphics_fitting_offset; 432 u8 graphics_fitting_size; 433 } __attribute__((packed)); 434 #pragma pack() 435 436 #pragma pack(1) 437 struct vch_bdb_22 { 438 struct aimdb_block aimdb_block; 439 struct vch_panel_data panels[16]; 440 } __attribute__((packed)); 441 #pragma pack() 442 443 #pragma pack(1) 444 struct bdb_sdvo_lvds_options { 445 u8 panel_backlight; 446 u8 h40_set_panel_type; 447 u8 panel_type; 448 u8 ssc_clk_freq; 449 u16 als_low_trip; 450 u16 als_high_trip; 451 u8 sclalarcoeff_tab_row_num; 452 u8 sclalarcoeff_tab_row_size; 453 u8 coefficient[8]; 454 u8 panel_misc_bits_1; 455 u8 panel_misc_bits_2; 456 u8 panel_misc_bits_3; 457 u8 panel_misc_bits_4; 458 } __attribute__((packed)); 459 #pragma pack() 460 461 462 #define BDB_DRIVER_FEATURE_NO_LVDS 0 463 #define BDB_DRIVER_FEATURE_INT_LVDS 1 464 #define BDB_DRIVER_FEATURE_SDVO_LVDS 2 465 #define BDB_DRIVER_FEATURE_EDP 3 466 467 #pragma pack(1) 468 struct bdb_driver_features { 469 u8 boot_dev_algorithm:1; 470 u8 block_display_switch:1; 471 u8 allow_display_switch:1; 472 u8 hotplug_dvo:1; 473 u8 dual_view_zoom:1; 474 u8 int15h_hook:1; 475 u8 sprite_in_clone:1; 476 u8 primary_lfp_id:1; 477 478 u16 boot_mode_x; 479 u16 boot_mode_y; 480 u8 boot_mode_bpp; 481 u8 boot_mode_refresh; 482 483 u16 enable_lfp_primary:1; 484 u16 selective_mode_pruning:1; 485 u16 dual_frequency:1; 486 u16 render_clock_freq:1; /* 0: high freq; 1: low freq */ 487 u16 nt_clone_support:1; 488 u16 power_scheme_ui:1; /* 0: CUI; 1: 3rd party */ 489 u16 sprite_display_assign:1; /* 0: secondary; 1: primary */ 490 u16 cui_aspect_scaling:1; 491 u16 preserve_aspect_ratio:1; 492 u16 sdvo_device_power_down:1; 493 u16 crt_hotplug:1; 494 u16 lvds_config:2; 495 u16 tv_hotplug:1; 496 u16 hdmi_config:2; 497 498 u8 static_display:1; 499 u8 reserved2:7; 500 u16 legacy_crt_max_x; 501 u16 legacy_crt_max_y; 502 u8 legacy_crt_max_refresh; 503 504 u8 hdmi_termination; 505 u8 custom_vbt_version; 506 } __attribute__((packed)); 507 #pragma pack() 508 509 #define EDP_18BPP 0 510 #define EDP_24BPP 1 511 #define EDP_30BPP 2 512 #define EDP_RATE_1_62 0 513 #define EDP_RATE_2_7 1 514 #define EDP_LANE_1 0 515 #define EDP_LANE_2 1 516 #define EDP_LANE_4 3 517 #define EDP_PREEMPHASIS_NONE 0 518 #define EDP_PREEMPHASIS_3_5dB 1 519 #define EDP_PREEMPHASIS_6dB 2 520 #define EDP_PREEMPHASIS_9_5dB 3 521 #define EDP_VSWING_0_4V 0 522 #define EDP_VSWING_0_6V 1 523 #define EDP_VSWING_0_8V 2 524 #define EDP_VSWING_1_2V 3 525 526 #pragma pack(1) 527 struct edp_power_seq { 528 u16 t1_t3; 529 u16 t8; 530 u16 t9; 531 u16 t10; 532 u16 t11_t12; 533 } __attribute__ ((packed)); 534 #pragma pack() 535 536 #pragma pack(1) 537 struct edp_link_params { 538 u8 rate:4; 539 u8 lanes:4; 540 u8 preemphasis:4; 541 u8 vswing:4; 542 } __attribute__ ((packed)); 543 #pragma pack() 544 545 #pragma pack(1) 546 struct bdb_edp { 547 struct edp_power_seq power_seqs[16]; 548 u32 color_depth; 549 struct edp_link_params link_params[16]; 550 u32 sdrrs_msa_timing_delay; 551 552 /* ith bit indicates enabled/disabled for (i+1)th panel */ 553 u16 edp_s3d_feature; 554 u16 edp_t3_optimization; 555 } __attribute__ ((packed)); 556 #pragma pack() 557 558 void intel_setup_bios(struct drm_device *dev); 559 int intel_parse_bios(struct drm_device *dev); 560 561 /* 562 * Driver<->VBIOS interaction occurs through scratch bits in 563 * GR18 & SWF*. 564 */ 565 566 /* GR18 bits are set on display switch and hotkey events */ 567 #define GR18_DRIVER_SWITCH_EN (1<<7) /* 0: VBIOS control, 1: driver control */ 568 #define GR18_HOTKEY_MASK 0x78 /* See also SWF4 15:0 */ 569 #define GR18_HK_NONE (0x0<<3) 570 #define GR18_HK_LFP_STRETCH (0x1<<3) 571 #define GR18_HK_TOGGLE_DISP (0x2<<3) 572 #define GR18_HK_DISP_SWITCH (0x4<<3) /* see SWF14 15:0 for what to enable */ 573 #define GR18_HK_POPUP_DISABLED (0x6<<3) 574 #define GR18_HK_POPUP_ENABLED (0x7<<3) 575 #define GR18_HK_PFIT (0x8<<3) 576 #define GR18_HK_APM_CHANGE (0xa<<3) 577 #define GR18_HK_MULTIPLE (0xc<<3) 578 #define GR18_USER_INT_EN (1<<2) 579 #define GR18_A0000_FLUSH_EN (1<<1) 580 #define GR18_SMM_EN (1<<0) 581 582 /* Set by driver, cleared by VBIOS */ 583 #define SWF00_YRES_SHIFT 16 584 #define SWF00_XRES_SHIFT 0 585 #define SWF00_RES_MASK 0xffff 586 587 /* Set by VBIOS at boot time and driver at runtime */ 588 #define SWF01_TV2_FORMAT_SHIFT 8 589 #define SWF01_TV1_FORMAT_SHIFT 0 590 #define SWF01_TV_FORMAT_MASK 0xffff 591 592 #define SWF10_VBIOS_BLC_I2C_EN (1<<29) 593 #define SWF10_GTT_OVERRIDE_EN (1<<28) 594 #define SWF10_LFP_DPMS_OVR (1<<27) /* override DPMS on display switch */ 595 #define SWF10_ACTIVE_TOGGLE_LIST_MASK (7<<24) 596 #define SWF10_OLD_TOGGLE 0x0 597 #define SWF10_TOGGLE_LIST_1 0x1 598 #define SWF10_TOGGLE_LIST_2 0x2 599 #define SWF10_TOGGLE_LIST_3 0x3 600 #define SWF10_TOGGLE_LIST_4 0x4 601 #define SWF10_PANNING_EN (1<<23) 602 #define SWF10_DRIVER_LOADED (1<<22) 603 #define SWF10_EXTENDED_DESKTOP (1<<21) 604 #define SWF10_EXCLUSIVE_MODE (1<<20) 605 #define SWF10_OVERLAY_EN (1<<19) 606 #define SWF10_PLANEB_HOLDOFF (1<<18) 607 #define SWF10_PLANEA_HOLDOFF (1<<17) 608 #define SWF10_VGA_HOLDOFF (1<<16) 609 #define SWF10_ACTIVE_DISP_MASK 0xffff 610 #define SWF10_PIPEB_LFP2 (1<<15) 611 #define SWF10_PIPEB_EFP2 (1<<14) 612 #define SWF10_PIPEB_TV2 (1<<13) 613 #define SWF10_PIPEB_CRT2 (1<<12) 614 #define SWF10_PIPEB_LFP (1<<11) 615 #define SWF10_PIPEB_EFP (1<<10) 616 #define SWF10_PIPEB_TV (1<<9) 617 #define SWF10_PIPEB_CRT (1<<8) 618 #define SWF10_PIPEA_LFP2 (1<<7) 619 #define SWF10_PIPEA_EFP2 (1<<6) 620 #define SWF10_PIPEA_TV2 (1<<5) 621 #define SWF10_PIPEA_CRT2 (1<<4) 622 #define SWF10_PIPEA_LFP (1<<3) 623 #define SWF10_PIPEA_EFP (1<<2) 624 #define SWF10_PIPEA_TV (1<<1) 625 #define SWF10_PIPEA_CRT (1<<0) 626 627 #define SWF11_MEMORY_SIZE_SHIFT 16 628 #define SWF11_SV_TEST_EN (1<<15) 629 #define SWF11_IS_AGP (1<<14) 630 #define SWF11_DISPLAY_HOLDOFF (1<<13) 631 #define SWF11_DPMS_REDUCED (1<<12) 632 #define SWF11_IS_VBE_MODE (1<<11) 633 #define SWF11_PIPEB_ACCESS (1<<10) /* 0 here means pipe a */ 634 #define SWF11_DPMS_MASK 0x07 635 #define SWF11_DPMS_OFF (1<<2) 636 #define SWF11_DPMS_SUSPEND (1<<1) 637 #define SWF11_DPMS_STANDBY (1<<0) 638 #define SWF11_DPMS_ON 0 639 640 #define SWF14_GFX_PFIT_EN (1<<31) 641 #define SWF14_TEXT_PFIT_EN (1<<30) 642 #define SWF14_LID_STATUS_CLOSED (1<<29) /* 0 here means open */ 643 #define SWF14_POPUP_EN (1<<28) 644 #define SWF14_DISPLAY_HOLDOFF (1<<27) 645 #define SWF14_DISP_DETECT_EN (1<<26) 646 #define SWF14_DOCKING_STATUS_DOCKED (1<<25) /* 0 here means undocked */ 647 #define SWF14_DRIVER_STATUS (1<<24) 648 #define SWF14_OS_TYPE_WIN9X (1<<23) 649 #define SWF14_OS_TYPE_WINNT (1<<22) 650 /* 21:19 rsvd */ 651 #define SWF14_PM_TYPE_MASK 0x00070000 652 #define SWF14_PM_ACPI_VIDEO (0x4 << 16) 653 #define SWF14_PM_ACPI (0x3 << 16) 654 #define SWF14_PM_APM_12 (0x2 << 16) 655 #define SWF14_PM_APM_11 (0x1 << 16) 656 #define SWF14_HK_REQUEST_MASK 0x0000ffff /* see GR18 6:3 for event type */ 657 /* if GR18 indicates a display switch */ 658 #define SWF14_DS_PIPEB_LFP2_EN (1<<15) 659 #define SWF14_DS_PIPEB_EFP2_EN (1<<14) 660 #define SWF14_DS_PIPEB_TV2_EN (1<<13) 661 #define SWF14_DS_PIPEB_CRT2_EN (1<<12) 662 #define SWF14_DS_PIPEB_LFP_EN (1<<11) 663 #define SWF14_DS_PIPEB_EFP_EN (1<<10) 664 #define SWF14_DS_PIPEB_TV_EN (1<<9) 665 #define SWF14_DS_PIPEB_CRT_EN (1<<8) 666 #define SWF14_DS_PIPEA_LFP2_EN (1<<7) 667 #define SWF14_DS_PIPEA_EFP2_EN (1<<6) 668 #define SWF14_DS_PIPEA_TV2_EN (1<<5) 669 #define SWF14_DS_PIPEA_CRT2_EN (1<<4) 670 #define SWF14_DS_PIPEA_LFP_EN (1<<3) 671 #define SWF14_DS_PIPEA_EFP_EN (1<<2) 672 #define SWF14_DS_PIPEA_TV_EN (1<<1) 673 #define SWF14_DS_PIPEA_CRT_EN (1<<0) 674 /* if GR18 indicates a panel fitting request */ 675 #define SWF14_PFIT_EN (1<<0) /* 0 means disable */ 676 /* if GR18 indicates an APM change request */ 677 #define SWF14_APM_HIBERNATE 0x4 678 #define SWF14_APM_SUSPEND 0x3 679 #define SWF14_APM_STANDBY 0x1 680 #define SWF14_APM_RESTORE 0x0 681 682 /* Add the device class for LFP, TV, HDMI */ 683 #define DEVICE_TYPE_INT_LFP 0x1022 684 #define DEVICE_TYPE_INT_TV 0x1009 685 #define DEVICE_TYPE_HDMI 0x60D2 686 #define DEVICE_TYPE_DP 0x68C6 687 #define DEVICE_TYPE_eDP 0x78C6 688 689 /* define the DVO port for HDMI output type */ 690 #define DVO_B 1 691 #define DVO_C 2 692 #define DVO_D 3 693 694 /* define the PORT for DP output type */ 695 #define PORT_IDPB 7 696 #define PORT_IDPC 8 697 #define PORT_IDPD 9 698 699 #endif /* _I830_BIOS_H_ */ 700