1 /*
2 * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved.
3 */
4
5 /*
6 * Copyright (c) 2009, 2013, Intel Corporation.
7 * All Rights Reserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * IN THE SOFTWARE.
27 *
28 * Authors:
29 * Keith Packard <keithp@keithp.com>
30 *
31 */
32
33 #include "drmP.h"
34 #include "drm.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37
38 int gpu_dump = B_TRUE;
39 int gpu_panic_on_hang = B_FALSE;
40
41 #define BUFFER_FAIL(_count, _len, _name) { \
42 DRM_ERROR("Buffer size too small in %s (%d < %d)", \
43 (_name), (_count), (_len)); \
44 (*failures)++; \
45 return count; \
46 }
47
48
49 static uint32_t saved_s2 = 0, saved_s4 = 0;
50 static char saved_s2_set = 0, saved_s4_set = 0;
51
52
53 #define MAX_INSTDONE_BITS 100
54
55 struct instdone_bit {
56 uint32_t reg;
57 uint32_t bit;
58 const char *name;
59 };
60
61 struct instdone_bit instdone_bits[MAX_INSTDONE_BITS];
62 int num_instdone_bits = 0;
63
64 static void
add_instdone_bit(uint32_t reg,uint32_t bit,const char * name)65 add_instdone_bit(uint32_t reg, uint32_t bit, const char *name)
66 {
67 instdone_bits[num_instdone_bits].reg = reg;
68 instdone_bits[num_instdone_bits].bit = bit;
69 instdone_bits[num_instdone_bits].name = name;
70 num_instdone_bits++;
71 }
72
73 static void
gen3_instdone_bit(uint32_t bit,const char * name)74 gen3_instdone_bit(uint32_t bit, const char *name)
75 {
76 add_instdone_bit(INST_DONE, bit, name);
77 }
78
79 static void
gen4_instdone_bit(uint32_t bit,const char * name)80 gen4_instdone_bit(uint32_t bit, const char *name)
81 {
82 add_instdone_bit(INST_DONE_I965, bit, name);
83 }
84
85 static void
gen4_instdone1_bit(uint32_t bit,const char * name)86 gen4_instdone1_bit(uint32_t bit, const char *name)
87 {
88 add_instdone_bit(INST_DONE_1, bit, name);
89 }
90
91 static void
gen6_instdone1_bit(uint32_t bit,const char * name)92 gen6_instdone1_bit(uint32_t bit, const char *name)
93 {
94 add_instdone_bit(GEN6_INSTDONE_1, bit, name);
95 }
96
97 static void
gen6_instdone2_bit(uint32_t bit,const char * name)98 gen6_instdone2_bit(uint32_t bit, const char *name)
99 {
100 add_instdone_bit(GEN6_INSTDONE_2, bit, name);
101 }
102
103 static void
init_g965_instdone1(void)104 init_g965_instdone1(void)
105 {
106 gen4_instdone1_bit(I965_GW_CS_DONE_CR, "GW CS CR");
107 gen4_instdone1_bit(I965_SVSM_CS_DONE_CR, "SVSM CS CR");
108 gen4_instdone1_bit(I965_SVDW_CS_DONE_CR, "SVDW CS CR");
109 gen4_instdone1_bit(I965_SVDR_CS_DONE_CR, "SVDR CS CR");
110 gen4_instdone1_bit(I965_SVRW_CS_DONE_CR, "SVRW CS CR");
111 gen4_instdone1_bit(I965_SVRR_CS_DONE_CR, "SVRR CS CR");
112 gen4_instdone1_bit(I965_SVTW_CS_DONE_CR, "SVTW CS CR");
113 gen4_instdone1_bit(I965_MASM_CS_DONE_CR, "MASM CS CR");
114 gen4_instdone1_bit(I965_MASF_CS_DONE_CR, "MASF CS CR");
115 gen4_instdone1_bit(I965_MAW_CS_DONE_CR, "MAW CS CR");
116 gen4_instdone1_bit(I965_EM1_CS_DONE_CR, "EM1 CS CR");
117 gen4_instdone1_bit(I965_EM0_CS_DONE_CR, "EM0 CS CR");
118 gen4_instdone1_bit(I965_UC1_CS_DONE, "UC1 CS");
119 gen4_instdone1_bit(I965_UC0_CS_DONE, "UC0 CS");
120 gen4_instdone1_bit(I965_URB_CS_DONE, "URB CS");
121 gen4_instdone1_bit(I965_ISC_CS_DONE, "ISC CS");
122 gen4_instdone1_bit(I965_CL_CS_DONE, "CL CS");
123 gen4_instdone1_bit(I965_GS_CS_DONE, "GS CS");
124 gen4_instdone1_bit(I965_VS0_CS_DONE, "VS0 CS");
125 gen4_instdone1_bit(I965_VF_CS_DONE, "VF CS");
126 }
127
128 static void
init_g4x_instdone1(void)129 init_g4x_instdone1(void)
130 {
131 gen4_instdone1_bit(G4X_BCS_DONE, "BCS");
132 gen4_instdone1_bit(G4X_CS_DONE, "CS");
133 gen4_instdone1_bit(G4X_MASF_DONE, "MASF");
134 gen4_instdone1_bit(G4X_SVDW_DONE, "SVDW");
135 gen4_instdone1_bit(G4X_SVDR_DONE, "SVDR");
136 gen4_instdone1_bit(G4X_SVRW_DONE, "SVRW");
137 gen4_instdone1_bit(G4X_SVRR_DONE, "SVRR");
138 gen4_instdone1_bit(G4X_ISC_DONE, "ISC");
139 gen4_instdone1_bit(G4X_MT_DONE, "MT");
140 gen4_instdone1_bit(G4X_RC_DONE, "RC");
141 gen4_instdone1_bit(G4X_DAP_DONE, "DAP");
142 gen4_instdone1_bit(G4X_MAWB_DONE, "MAWB");
143 gen4_instdone1_bit(G4X_MT_IDLE, "MT idle");
144 //gen4_instdone1_bit(G4X_GBLT_BUSY, "GBLT");
145 gen4_instdone1_bit(G4X_SVSM_DONE, "SVSM");
146 gen4_instdone1_bit(G4X_MASM_DONE, "MASM");
147 gen4_instdone1_bit(G4X_QC_DONE, "QC");
148 gen4_instdone1_bit(G4X_FL_DONE, "FL");
149 gen4_instdone1_bit(G4X_SC_DONE, "SC");
150 gen4_instdone1_bit(G4X_DM_DONE, "DM");
151 gen4_instdone1_bit(G4X_FT_DONE, "FT");
152 gen4_instdone1_bit(G4X_DG_DONE, "DG");
153 gen4_instdone1_bit(G4X_SI_DONE, "SI");
154 gen4_instdone1_bit(G4X_SO_DONE, "SO");
155 gen4_instdone1_bit(G4X_PL_DONE, "PL");
156 gen4_instdone1_bit(G4X_WIZ_DONE, "WIZ");
157 gen4_instdone1_bit(G4X_URB_DONE, "URB");
158 gen4_instdone1_bit(G4X_SF_DONE, "SF");
159 gen4_instdone1_bit(G4X_CL_DONE, "CL");
160 gen4_instdone1_bit(G4X_GS_DONE, "GS");
161 gen4_instdone1_bit(G4X_VS0_DONE, "VS0");
162 gen4_instdone1_bit(G4X_VF_DONE, "VF");
163 }
164
165 void
init_instdone_definitions(struct drm_device * dev)166 init_instdone_definitions(struct drm_device *dev)
167 {
168 if (IS_GEN6(dev)) {
169 /* Now called INSTDONE_1 in the docs. */
170 gen6_instdone1_bit(GEN6_MA_3_DONE, "Message Arbiter 3");
171 gen6_instdone1_bit(GEN6_EU_32_DONE, "EU 32");
172 gen6_instdone1_bit(GEN6_EU_31_DONE, "EU 31");
173 gen6_instdone1_bit(GEN6_EU_30_DONE, "EU 30");
174 gen6_instdone1_bit(GEN6_MA_3_DONE, "Message Arbiter 2");
175 gen6_instdone1_bit(GEN6_EU_22_DONE, "EU 22");
176 gen6_instdone1_bit(GEN6_EU_21_DONE, "EU 21");
177 gen6_instdone1_bit(GEN6_EU_20_DONE, "EU 20");
178 gen6_instdone1_bit(GEN6_MA_3_DONE, "Message Arbiter 1");
179 gen6_instdone1_bit(GEN6_EU_12_DONE, "EU 12");
180 gen6_instdone1_bit(GEN6_EU_11_DONE, "EU 11");
181 gen6_instdone1_bit(GEN6_EU_10_DONE, "EU 10");
182 gen6_instdone1_bit(GEN6_MA_3_DONE, "Message Arbiter 0");
183 gen6_instdone1_bit(GEN6_EU_02_DONE, "EU 02");
184 gen6_instdone1_bit(GEN6_EU_01_DONE, "EU 01");
185 gen6_instdone1_bit(GEN6_EU_00_DONE, "EU 00");
186
187 gen6_instdone1_bit(GEN6_IC_3_DONE, "IC 3");
188 gen6_instdone1_bit(GEN6_IC_2_DONE, "IC 2");
189 gen6_instdone1_bit(GEN6_IC_1_DONE, "IC 1");
190 gen6_instdone1_bit(GEN6_IC_0_DONE, "IC 0");
191 gen6_instdone1_bit(GEN6_ISC_10_DONE, "ISC 1/0");
192 gen6_instdone1_bit(GEN6_ISC_32_DONE, "ISC 3/2");
193
194 gen6_instdone1_bit(GEN6_VSC_DONE, "VSC");
195 gen6_instdone1_bit(GEN6_IEF_DONE, "IEF");
196 gen6_instdone1_bit(GEN6_VFE_DONE, "VFE");
197 gen6_instdone1_bit(GEN6_TD_DONE, "TD");
198 gen6_instdone1_bit(GEN6_TS_DONE, "TS");
199 gen6_instdone1_bit(GEN6_GW_DONE, "GW");
200 gen6_instdone1_bit(GEN6_HIZ_DONE, "HIZ");
201 gen6_instdone1_bit(GEN6_AVS_DONE, "AVS");
202
203 /* Now called INSTDONE_2 in the docs. */
204 gen6_instdone2_bit(GEN6_GAM_DONE, "GAM");
205 gen6_instdone2_bit(GEN6_CS_DONE, "CS");
206 gen6_instdone2_bit(GEN6_WMBE_DONE, "WMBE");
207 gen6_instdone2_bit(GEN6_SVRW_DONE, "SVRW");
208 gen6_instdone2_bit(GEN6_RCC_DONE, "RCC");
209 gen6_instdone2_bit(GEN6_SVG_DONE, "SVG");
210 gen6_instdone2_bit(GEN6_ISC_DONE, "ISC");
211 gen6_instdone2_bit(GEN6_MT_DONE, "MT");
212 gen6_instdone2_bit(GEN6_RCPFE_DONE, "RCPFE");
213 gen6_instdone2_bit(GEN6_RCPBE_DONE, "RCPBE");
214 gen6_instdone2_bit(GEN6_VDI_DONE, "VDI");
215 gen6_instdone2_bit(GEN6_RCZ_DONE, "RCZ");
216 gen6_instdone2_bit(GEN6_DAP_DONE, "DAP");
217 gen6_instdone2_bit(GEN6_PSD_DONE, "PSD");
218 gen6_instdone2_bit(GEN6_IZ_DONE, "IZ");
219 gen6_instdone2_bit(GEN6_WMFE_DONE, "WMFE");
220 gen6_instdone2_bit(GEN6_SVSM_DONE, "SVSM");
221 gen6_instdone2_bit(GEN6_QC_DONE, "QC");
222 gen6_instdone2_bit(GEN6_FL_DONE, "FL");
223 gen6_instdone2_bit(GEN6_SC_DONE, "SC");
224 gen6_instdone2_bit(GEN6_DM_DONE, "DM");
225 gen6_instdone2_bit(GEN6_FT_DONE, "FT");
226 gen6_instdone2_bit(GEN6_DG_DONE, "DG");
227 gen6_instdone2_bit(GEN6_SI_DONE, "SI");
228 gen6_instdone2_bit(GEN6_SO_DONE, "SO");
229 gen6_instdone2_bit(GEN6_PL_DONE, "PL");
230 gen6_instdone2_bit(GEN6_VME_DONE, "VME");
231 gen6_instdone2_bit(GEN6_SF_DONE, "SF");
232 gen6_instdone2_bit(GEN6_CL_DONE, "CL");
233 gen6_instdone2_bit(GEN6_GS_DONE, "GS");
234 gen6_instdone2_bit(GEN6_VS0_DONE, "VS0");
235 gen6_instdone2_bit(GEN6_VF_DONE, "VF");
236 } else if (IS_GEN5(dev)) {
237 gen4_instdone_bit(ILK_ROW_0_EU_0_DONE, "Row 0, EU 0");
238 gen4_instdone_bit(ILK_ROW_0_EU_1_DONE, "Row 0, EU 1");
239 gen4_instdone_bit(ILK_ROW_0_EU_2_DONE, "Row 0, EU 2");
240 gen4_instdone_bit(ILK_ROW_0_EU_3_DONE, "Row 0, EU 3");
241 gen4_instdone_bit(ILK_ROW_1_EU_0_DONE, "Row 1, EU 0");
242 gen4_instdone_bit(ILK_ROW_1_EU_1_DONE, "Row 1, EU 1");
243 gen4_instdone_bit(ILK_ROW_1_EU_2_DONE, "Row 1, EU 2");
244 gen4_instdone_bit(ILK_ROW_1_EU_3_DONE, "Row 1, EU 3");
245 gen4_instdone_bit(ILK_ROW_2_EU_0_DONE, "Row 2, EU 0");
246 gen4_instdone_bit(ILK_ROW_2_EU_1_DONE, "Row 2, EU 1");
247 gen4_instdone_bit(ILK_ROW_2_EU_2_DONE, "Row 2, EU 2");
248 gen4_instdone_bit(ILK_ROW_2_EU_3_DONE, "Row 2, EU 3");
249 gen4_instdone_bit(ILK_VCP_DONE, "VCP");
250 gen4_instdone_bit(ILK_ROW_0_MATH_DONE, "Row 0 math");
251 gen4_instdone_bit(ILK_ROW_1_MATH_DONE, "Row 1 math");
252 gen4_instdone_bit(ILK_ROW_2_MATH_DONE, "Row 2 math");
253 gen4_instdone_bit(ILK_VC1_DONE, "VC1");
254 gen4_instdone_bit(ILK_ROW_0_MA_DONE, "Row 0 MA");
255 gen4_instdone_bit(ILK_ROW_1_MA_DONE, "Row 1 MA");
256 gen4_instdone_bit(ILK_ROW_2_MA_DONE, "Row 2 MA");
257 gen4_instdone_bit(ILK_ROW_0_ISC_DONE, "Row 0 ISC");
258 gen4_instdone_bit(ILK_ROW_1_ISC_DONE, "Row 1 ISC");
259 gen4_instdone_bit(ILK_ROW_2_ISC_DONE, "Row 2 ISC");
260 gen4_instdone_bit(ILK_VFE_DONE, "VFE");
261 gen4_instdone_bit(ILK_TD_DONE, "TD");
262 gen4_instdone_bit(ILK_SVTS_DONE, "SVTS");
263 gen4_instdone_bit(ILK_TS_DONE, "TS");
264 gen4_instdone_bit(ILK_GW_DONE, "GW");
265 gen4_instdone_bit(ILK_AI_DONE, "AI");
266 gen4_instdone_bit(ILK_AC_DONE, "AC");
267 gen4_instdone_bit(ILK_AM_DONE, "AM");
268
269 init_g4x_instdone1();
270 } else if (IS_GEN4(dev)) {
271 gen4_instdone_bit(I965_ROW_0_EU_0_DONE, "Row 0, EU 0");
272 gen4_instdone_bit(I965_ROW_0_EU_1_DONE, "Row 0, EU 1");
273 gen4_instdone_bit(I965_ROW_0_EU_2_DONE, "Row 0, EU 2");
274 gen4_instdone_bit(I965_ROW_0_EU_3_DONE, "Row 0, EU 3");
275 gen4_instdone_bit(I965_ROW_1_EU_0_DONE, "Row 1, EU 0");
276 gen4_instdone_bit(I965_ROW_1_EU_1_DONE, "Row 1, EU 1");
277 gen4_instdone_bit(I965_ROW_1_EU_2_DONE, "Row 1, EU 2");
278 gen4_instdone_bit(I965_ROW_1_EU_3_DONE, "Row 1, EU 3");
279 gen4_instdone_bit(I965_SF_DONE, "Strips and Fans");
280 gen4_instdone_bit(I965_SE_DONE, "Setup Engine");
281 gen4_instdone_bit(I965_WM_DONE, "Windowizer");
282 gen4_instdone_bit(I965_DISPATCHER_DONE, "Dispatcher");
283 gen4_instdone_bit(I965_PROJECTION_DONE, "Projection and LOD");
284 gen4_instdone_bit(I965_DG_DONE, "Dependent address generator");
285 gen4_instdone_bit(I965_QUAD_CACHE_DONE, "Texture fetch");
286 gen4_instdone_bit(I965_TEXTURE_FETCH_DONE, "Texture fetch");
287 gen4_instdone_bit(I965_TEXTURE_DECOMPRESS_DONE, "Texture decompress");
288 gen4_instdone_bit(I965_SAMPLER_CACHE_DONE, "Sampler cache");
289 gen4_instdone_bit(I965_FILTER_DONE, "Filtering");
290 gen4_instdone_bit(I965_BYPASS_DONE, "Bypass FIFO");
291 gen4_instdone_bit(I965_PS_DONE, "Pixel shader");
292 gen4_instdone_bit(I965_CC_DONE, "Color calculator");
293 gen4_instdone_bit(I965_MAP_FILTER_DONE, "Map filter");
294 gen4_instdone_bit(I965_MAP_L2_IDLE, "Map L2");
295 gen4_instdone_bit(I965_MA_ROW_0_DONE, "Message Arbiter row 0");
296 gen4_instdone_bit(I965_MA_ROW_1_DONE, "Message Arbiter row 1");
297 gen4_instdone_bit(I965_IC_ROW_0_DONE, "Instruction cache row 0");
298 gen4_instdone_bit(I965_IC_ROW_1_DONE, "Instruction cache row 1");
299 gen4_instdone_bit(I965_CP_DONE, "Command Processor");
300
301 if (IS_G4X(dev)) {
302 init_g4x_instdone1();
303 } else {
304 init_g965_instdone1();
305 }
306 } else if (IS_GEN3(dev)) {
307 gen3_instdone_bit(IDCT_DONE, "IDCT");
308 gen3_instdone_bit(IQ_DONE, "IQ");
309 gen3_instdone_bit(PR_DONE, "PR");
310 gen3_instdone_bit(VLD_DONE, "VLD");
311 gen3_instdone_bit(IP_DONE, "Instruction parser");
312 gen3_instdone_bit(FBC_DONE, "Framebuffer Compression");
313 gen3_instdone_bit(BINNER_DONE, "Binner");
314 gen3_instdone_bit(SF_DONE, "Strips and fans");
315 gen3_instdone_bit(SE_DONE, "Setup engine");
316 gen3_instdone_bit(WM_DONE, "Windowizer");
317 gen3_instdone_bit(IZ_DONE, "Intermediate Z");
318 gen3_instdone_bit(PERSPECTIVE_INTERP_DONE, "Perspective interpolation");
319 gen3_instdone_bit(DISPATCHER_DONE, "Dispatcher");
320 gen3_instdone_bit(PROJECTION_DONE, "Projection and LOD");
321 gen3_instdone_bit(DEPENDENT_ADDRESS_DONE, "Dependent address calculation");
322 gen3_instdone_bit(TEXTURE_FETCH_DONE, "Texture fetch");
323 gen3_instdone_bit(TEXTURE_DECOMPRESS_DONE, "Texture decompression");
324 gen3_instdone_bit(SAMPLER_CACHE_DONE, "Sampler Cache");
325 gen3_instdone_bit(FILTER_DONE, "Filtering");
326 gen3_instdone_bit(BYPASS_FIFO_DONE, "Bypass FIFO");
327 gen3_instdone_bit(PS_DONE, "Pixel shader");
328 gen3_instdone_bit(CC_DONE, "Color calculator");
329 gen3_instdone_bit(MAP_FILTER_DONE, "Map filter");
330 gen3_instdone_bit(MAP_L2_IDLE, "Map L2");
331 } else {
332 gen3_instdone_bit(I830_GMBUS_DONE, "GMBUS");
333 gen3_instdone_bit(I830_FBC_DONE, "FBC");
334 gen3_instdone_bit(I830_BINNER_DONE, "BINNER");
335 gen3_instdone_bit(I830_MPEG_DONE, "MPEG");
336 gen3_instdone_bit(I830_MECO_DONE, "MECO");
337 gen3_instdone_bit(I830_MCD_DONE, "MCD");
338 gen3_instdone_bit(I830_MCSTP_DONE, "MCSTP");
339 gen3_instdone_bit(I830_CC_DONE, "CC");
340 gen3_instdone_bit(I830_DG_DONE, "DG");
341 gen3_instdone_bit(I830_DCMP_DONE, "DCMP");
342 gen3_instdone_bit(I830_FTCH_DONE, "FTCH");
343 gen3_instdone_bit(I830_IT_DONE, "IT");
344 gen3_instdone_bit(I830_MG_DONE, "MG");
345 gen3_instdone_bit(I830_MEC_DONE, "MEC");
346 gen3_instdone_bit(I830_PC_DONE, "PC");
347 gen3_instdone_bit(I830_QCC_DONE, "QCC");
348 gen3_instdone_bit(I830_TB_DONE, "TB");
349 gen3_instdone_bit(I830_WM_DONE, "WM");
350 gen3_instdone_bit(I830_EF_DONE, "EF");
351 gen3_instdone_bit(I830_BLITTER_DONE, "Blitter");
352 gen3_instdone_bit(I830_MAP_L2_DONE, "Map L2 cache");
353 gen3_instdone_bit(I830_SECONDARY_RING_3_DONE, "Secondary ring 3");
354 gen3_instdone_bit(I830_SECONDARY_RING_2_DONE, "Secondary ring 2");
355 gen3_instdone_bit(I830_SECONDARY_RING_1_DONE, "Secondary ring 1");
356 gen3_instdone_bit(I830_SECONDARY_RING_0_DONE, "Secondary ring 0");
357 gen3_instdone_bit(I830_PRIMARY_RING_1_DONE, "Primary ring 1");
358 gen3_instdone_bit(I830_PRIMARY_RING_0_DONE, "Primary ring 0");
359 }
360 }
361 #define ring_read(ring, reg) I915_READ(ring->mmio + reg)
362 #define MAX_NUM_TOP_BITS 100
363 #define SAMPLES_PER_SEC 10000
364 #define SAMPLES_TO_PERCENT_RATIO (SAMPLES_PER_SEC / 100)
365
366 #define HAS_STATS_REGS(dev) (IS_GEN4(dev) || \
367 IS_GEN5(dev) || \
368 IS_GEN6(dev))
369 struct top_bit {
370 struct instdone_bit *bit;
371 int count;
372 } top_bits[MAX_NUM_TOP_BITS];
373 struct top_bit *top_bits_sorted[MAX_NUM_TOP_BITS];
374 static uint32_t instdone, instdone1;
375
376 struct ring {
377 const char *name;
378 uint32_t mmio, size;
379 int head, tail;
380 uint64_t full;
381 int idle;
382 };
383
384 enum stats_counts {
385 IA_VERTICES,
386 IA_PRIMITIVES,
387 VS_INVOCATION,
388 GS_INVOCATION,
389 GS_PRIMITIVES,
390 CL_INVOCATION,
391 CL_PRIMITIVES,
392 PS_INVOCATION,
393 PS_DEPTH,
394 STATS_COUNT
395 };
396
397 const uint32_t stats_regs[STATS_COUNT] = {
398 IA_VERTICES_COUNT_QW,
399 IA_PRIMITIVES_COUNT_QW,
400 VS_INVOCATION_COUNT_QW,
401 GS_INVOCATION_COUNT_QW,
402 GS_PRIMITIVES_COUNT_QW,
403 CL_INVOCATION_COUNT_QW,
404 CL_PRIMITIVES_COUNT_QW,
405 PS_INVOCATION_COUNT_QW,
406 PS_DEPTH_COUNT_QW,
407 };
408
409 const char *stats_reg_names[STATS_COUNT] = {
410 "vert fetch",
411 "prim fetch",
412 "VS invocations",
413 "GS invocations",
414 "GS prims",
415 "CL invocations",
416 "CL prims",
417 "PS invocations",
418 "PS depth pass",
419 };
420
421 uint64_t stats[STATS_COUNT];
422 uint64_t last_stats[STATS_COUNT];
423
424 static unsigned long
gettime(void)425 gettime(void)
426 {
427 struct timeval t;
428 do_gettimeofday(&t);
429 return (t.tv_usec + (t.tv_sec * 1000000));
430 }
431
432 static int
top_bits_sort(const void * a,const void * b)433 top_bits_sort(const void *a, const void *b)
434 {
435 struct top_bit * const *bit_a = a;
436 struct top_bit * const *bit_b = b;
437 int a_count = (*bit_a)->count;
438 int b_count = (*bit_b)->count;
439
440 if (a_count < b_count)
441 return 1;
442 else if (a_count == b_count)
443 return 0;
444 else
445 return -1;
446 }
447
448 static void
update_idle_bit(struct top_bit * top_bit)449 update_idle_bit(struct top_bit *top_bit)
450 {
451 uint32_t reg_val;
452
453 if (top_bit->bit->reg == INST_DONE_1)
454 reg_val = instdone1;
455 else
456 reg_val = instdone;
457
458 if ((reg_val & top_bit->bit->bit) == 0)
459 top_bit->count++;
460 }
461
462 static void
print_clock(char * name,int clock)463 print_clock(char *name, int clock) {
464 if (clock == -1)
465 DRM_ERROR("%s clock: unknown", name);
466 else
467 DRM_ERROR("%s clock: %d Mhz", name, clock);
468 }
469
470 static void
print_clock_info(struct drm_device * dev)471 print_clock_info(struct drm_device *dev)
472 {
473 uint16_t gcfgc;
474
475 if (IS_GM45(dev)) {
476 int core_clock = -1;
477
478 (void) pci_read_config_word(dev->pdev, I915_GCFGC, &gcfgc);
479
480 switch (gcfgc & 0xf) {
481 case 8:
482 core_clock = 266;
483 break;
484 case 9:
485 core_clock = 320;
486 break;
487 case 11:
488 core_clock = 400;
489 break;
490 case 13:
491 core_clock = 533;
492 break;
493 }
494 print_clock("core", core_clock);
495 } else if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
496 int render_clock = -1, sampler_clock = -1;
497
498 (void) pci_read_config_word(dev->pdev, I915_GCFGC, &gcfgc);
499
500 switch (gcfgc & 0xf) {
501 case 2:
502 render_clock = 250; sampler_clock = 267;
503 break;
504 case 3:
505 render_clock = 320; sampler_clock = 333;
506 break;
507 case 4:
508 render_clock = 400; sampler_clock = 444;
509 break;
510 case 5:
511 render_clock = 500; sampler_clock = 533;
512 break;
513 }
514
515 print_clock("render", render_clock);
516 print_clock("sampler", sampler_clock);
517 } else if (IS_I945GM(dev) && IS_MOBILE(dev)) {
518 int render_clock = -1, display_clock = -1;
519
520 (void) pci_read_config_word(dev->pdev, I915_GCFGC, &gcfgc);
521
522 switch (gcfgc & 0x7) {
523 case 0:
524 render_clock = 166;
525 break;
526 case 1:
527 render_clock = 200;
528 break;
529 case 3:
530 render_clock = 250;
531 break;
532 case 5:
533 render_clock = 400;
534 break;
535 }
536
537 switch (gcfgc & 0x70) {
538 case 0:
539 display_clock = 200;
540 break;
541 case 4:
542 display_clock = 320;
543 break;
544 }
545 if (gcfgc & (1 << 7))
546 display_clock = 133;
547
548 print_clock("render", render_clock);
549 print_clock("display", display_clock);
550 } else if (IS_I915GM(dev) && IS_MOBILE(dev)) {
551 int render_clock = -1, display_clock = -1;
552
553 (void) pci_read_config_word(dev->pdev, I915_GCFGC, &gcfgc);
554
555 switch (gcfgc & 0x7) {
556 case 0:
557 render_clock = 160;
558 break;
559 case 1:
560 render_clock = 190;
561 break;
562 case 4:
563 render_clock = 333;
564 break;
565 }
566 if (gcfgc & (1 << 13))
567 render_clock = 133;
568
569 switch (gcfgc & 0x70) {
570 case 0:
571 display_clock = 190;
572 break;
573 case 4:
574 display_clock = 333;
575 break;
576 }
577 if (gcfgc & (1 << 7))
578 display_clock = 133;
579
580 print_clock("render", render_clock);
581 print_clock("display", display_clock);
582 }
583 }
584
gen6_force_wake_get(struct drm_device * dev)585 static void gen6_force_wake_get(struct drm_device *dev)
586 {
587 struct drm_i915_private *dev_priv = dev->dev_private;
588 int count;
589
590 if (!IS_GEN6(dev))
591 return;
592
593 /* This will probably have undesirable side-effects upon the system. */
594 count = 0;
595 while (count++ < 50 && (I915_READ(FORCEWAKE_ACK) & 1))
596 udelay(10);
597
598 I915_WRITE(FORCEWAKE, 1);
599 POSTING_READ(FORCEWAKE);
600
601 count = 0;
602 while (count++ < 50 && (I915_READ(FORCEWAKE_ACK) & 1) == 0)
603 udelay(10);
604 }
605
gen6_force_wake_put(struct drm_device * dev)606 static void gen6_force_wake_put(struct drm_device *dev)
607 {
608 struct drm_i915_private *dev_priv = dev->dev_private;
609 if (!IS_GEN6(dev))
610 return;
611
612 I915_WRITE(FORCEWAKE, 0);
613 POSTING_READ(FORCEWAKE);
614 }
615
ring_init(struct drm_device * dev,struct ring * ring)616 static void ring_init(struct drm_device *dev, struct ring *ring)
617 {
618 struct drm_i915_private *dev_priv = dev->dev_private;
619 gen6_force_wake_get(dev);
620 ring->size = (((ring_read(ring, _RING_LEN) & RING_NR_PAGES) >> 12) + 1) * 4096;
621 gen6_force_wake_put(dev);
622 }
623
ring_reset(struct ring * ring)624 static void ring_reset(struct ring *ring)
625 {
626 ring->idle = ring->full = 0;
627 }
628
ring_sample(struct drm_device * dev,struct ring * ring)629 static void ring_sample(struct drm_device *dev, struct ring *ring)
630 {
631 struct drm_i915_private *dev_priv = dev->dev_private;
632 int full;
633
634 if (!ring->size)
635 return;
636
637 gen6_force_wake_get(dev);
638 ring->head = ring_read(ring, _RING_HEAD) & HEAD_ADDR;
639 ring->tail = ring_read(ring, _RING_TAIL) & TAIL_ADDR;
640 gen6_force_wake_put(dev);
641
642 if (ring->tail == ring->head)
643 ring->idle++;
644
645 full = ring->tail - ring->head;
646 if (full < 0)
647 full += ring->size;
648 ring->full += full;
649 }
650
ring_print(struct ring * ring,unsigned long samples_per_sec)651 static void ring_print(struct ring *ring, unsigned long samples_per_sec)
652 {
653 int samples_to_percent_ratio, percent;
654
655 /* Calculate current value of samples_to_percent_ratio */
656 samples_to_percent_ratio = (ring->idle * 100) / samples_per_sec;
657 percent = 100 - samples_to_percent_ratio;
658
659 if (!ring->size)
660 return;
661
662 DRM_ERROR("%25s busy: %3d%%: ", ring->name, percent);
663 DRM_ERROR("%24s space: %d/%d (%d%%)",
664 ring->name,
665 (int)(ring->full / samples_per_sec),
666 ring->size,
667 (int)((ring->full / samples_to_percent_ratio) / ring->size));
668 }
669
670
i915_gpu_top(struct drm_device * dev)671 void i915_gpu_top(struct drm_device *dev)
672 {
673 struct ring render_ring = {
674 .name = "render",
675 .mmio = 0x2030,
676 }, bsd_ring = {
677 .name = "bitstream",
678 .mmio = 0x4030,
679 }, bsd6_ring = {
680 .name = "bitstream",
681 .mmio = 0x12030,
682 }, blt_ring = {
683 .name = "blitter",
684 .mmio = 0x22030,
685 };
686 struct drm_i915_private *dev_priv = dev->dev_private;
687 uint32_t samples_per_sec = SAMPLES_PER_SEC;
688 struct timeval elapsed_time;
689 int i,j, k;
690 struct timeval t1, ti, tf, t2;
691 uint64_t def_sleep;
692 uint64_t last_samples_per_sec;
693 int percent;
694
695 init_instdone_definitions(dev);
696
697 for (i = 0; i < num_instdone_bits; i++) {
698 top_bits[i].bit = &instdone_bits[i];
699 top_bits[i].count = 0;
700 top_bits_sorted[i] = &top_bits[i];
701 }
702
703 ring_init(dev, &render_ring);
704 if (IS_GEN4(dev) || IS_GEN5(dev))
705 ring_init(dev, &bsd_ring);
706 if (IS_GEN6(dev)) {
707 ring_init(dev, &bsd6_ring);
708 ring_init(dev, &blt_ring);
709 }
710
711 /* Initialize GPU stats */
712 if (HAS_STATS_REGS(dev)) {
713 for (i = 0; i < STATS_COUNT; i++) {
714 uint32_t stats_high, stats_low, stats_high_2;
715
716 do {
717 stats_high = I915_READ(stats_regs[i] + 4);
718 stats_low = I915_READ(stats_regs[i]);
719 stats_high_2 = I915_READ(stats_regs[i] + 4);
720 } while (stats_high != stats_high_2);
721
722 last_stats[i] = (uint64_t)stats_high << 32 |
723 stats_low;
724 }
725 }
726 //start record
727 for (k = 0; k < 200000; k++) {
728 def_sleep = (1000000 / samples_per_sec);
729 last_samples_per_sec = samples_per_sec;
730
731 // t1 = gettime();
732 do_gettimeofday(&t1);
733
734 ring_reset(&render_ring);
735 ring_reset(&bsd_ring);
736 ring_reset(&bsd6_ring);
737 ring_reset(&blt_ring);
738
739 for (i = 0; i < samples_per_sec; i++) {
740 long interval;
741 long t_diff;
742 do_gettimeofday(&ti);
743 if (INTEL_INFO(dev)->gen >= 4) {
744 instdone = I915_READ(INST_DONE_I965);
745 instdone1 = I915_READ(INST_DONE_1);
746 } else
747 instdone = I915_READ(INST_DONE);
748
749 for (j = 0; j < num_instdone_bits; j++)
750 update_idle_bit(&top_bits[j]);
751
752 ring_sample(dev, &render_ring);
753 ring_sample(dev, &bsd_ring);
754 ring_sample(dev, &bsd6_ring);
755 ring_sample(dev, &blt_ring);
756
757 do_gettimeofday(&tf);
758 t_diff = (tf.tv_sec - t1.tv_sec) * 1000000 + tf.tv_usec - t1.tv_usec;
759 if (t_diff >= 1000000) {
760 /* We are out of sync, bail out */
761 last_samples_per_sec = i+1;
762 break;
763 }
764 t_diff = (tf.tv_sec - ti.tv_sec) * 1000000 + tf.tv_usec - ti.tv_usec;
765 interval = def_sleep - t_diff;
766 if (interval > 0)
767 udelay(interval);
768 }
769
770 if (HAS_STATS_REGS(dev)) {
771 for (i = 0; i < STATS_COUNT; i++) {
772 uint32_t stats_high, stats_low, stats_high_2;
773
774 do {
775 stats_high = I915_READ(stats_regs[i] + 4);
776 stats_low = I915_READ(stats_regs[i]);
777 stats_high_2 = I915_READ(stats_regs[i] + 4);
778 } while (stats_high != stats_high_2);
779
780 stats[i] = (uint64_t)stats_high << 32 |
781 stats_low;
782 }
783 }
784
785
786
787 //sort
788 // qsort(top_bits_sorted, num_instdone_bits,
789 // sizeof(struct top_bit *), top_bits_sort);
790 struct top_bit tmp_top;
791 for (i = 0; i < num_instdone_bits; i++) {
792 for (j = i+1; j < num_instdone_bits; j++) {
793 if (top_bits_sort(&top_bits_sorted[i], &top_bits_sorted[j]) == 1) {
794 tmp_top.bit = top_bits_sorted[i]->bit;
795 tmp_top.count = top_bits_sorted[i]->count;
796
797 top_bits_sorted[i]->bit = top_bits_sorted[j]->bit;
798 top_bits_sorted[i]->count = top_bits_sorted[j]->count;
799
800 top_bits_sorted[j]->bit = tmp_top.bit;
801 top_bits_sorted[j]->count = tmp_top.count;
802 }
803 }
804 }
805 //print info
806 int max_lines = -1;
807 max_lines = num_instdone_bits;
808
809 max_lines = 15;
810
811 do_gettimeofday(&t2);
812 timevalsub(&t2, &t1);
813 timevaladd(&elapsed_time, &t2);
814 long ttt = t2.tv_sec * 1000000 + t2.tv_usec;
815 DRM_ERROR("caculate time %ld usec!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!", ttt);
816
817 print_clock_info(dev);
818
819 ring_print(&render_ring, last_samples_per_sec);
820 ring_print(&bsd_ring, last_samples_per_sec);
821 ring_print(&bsd6_ring, last_samples_per_sec);
822 ring_print(&blt_ring, last_samples_per_sec);
823
824 for (i = 0; i < max_lines; i++) {
825 if (top_bits_sorted[i]->count > 0) {
826 percent = (top_bits_sorted[i]->count * 100) /
827 last_samples_per_sec;
828 DRM_ERROR("%30s: %3d%%: ",
829 top_bits_sorted[i]->bit->name,
830 percent);
831 } else {
832 DRM_ERROR(" ");
833 }
834
835 if (i < STATS_COUNT && HAS_STATS_REGS(dev)) {
836 DRM_ERROR("%13s: %lu (%ld/sec)",
837 stats_reg_names[i],
838 stats[i],
839 stats[i] - last_stats[i]);
840 last_stats[i] = stats[i];
841 } else {
842 if (!top_bits_sorted[i]->count)
843 break;
844 }
845 }
846
847 for (i = 0; i < num_instdone_bits; i++) {
848 top_bits_sorted[i]->count = 0;
849
850 if (i < STATS_COUNT)
851 last_stats[i] = stats[i];
852 }
853 udelay(4000000);
854 }
855 }
856
gpu_top_handler(void * data)857 void gpu_top_handler(void *data)
858 {
859 struct drm_device *dev = (struct drm_device *)data;
860 struct timeval t;
861 do_gettimeofday(&t);
862 DRM_ERROR("in %ld", t.tv_sec);
863 i915_gpu_top(dev);
864 /*
865 mod_timer(&dev_priv->gpu_top_timer,
866 jiffies + msecs_to_jiffies(5000));
867 */
868 }
869
ring_dump(struct drm_device * dev,struct intel_ring_buffer * ring)870 void ring_dump(struct drm_device *dev, struct intel_ring_buffer *ring)
871 {
872 struct drm_i915_private *dev_priv = dev->dev_private;
873
874 if (ring) {
875 /* dump ring infor*/
876 unsigned int *virt;
877 u32 tail, head;
878 head = I915_READ_HEAD(ring) & HEAD_ADDR;
879 tail = I915_READ_TAIL(ring) & TAIL_ADDR;
880
881 DRM_ERROR("Dump %s ring", ring->name);
882 DRM_ERROR("HEAD 0x%x TAIL 0x%x", head, tail);
883 DRM_ERROR("seq %d", ring->get_seqno(ring, true));
884
885 if (head == tail)
886 return;
887
888 for (int i = 0; i < 200; i++) {
889 virt = (unsigned int *)((intptr_t)ring->virtual_start + head + (i-180)*4);
890 DRM_ERROR("%s[0x%x]: 0x%x", ring->name, head + (i-180)*4, virt[0]);
891 }
892
893
894 }
895 }
896
gtt_dump(struct drm_device * dev)897 void gtt_dump(struct drm_device *dev)
898 {
899 struct drm_i915_private *dev_priv = dev->dev_private;
900 int ret;
901
902 if (gpu_panic_on_hang) {
903 dev->gtt_dump = kmem_zalloc(gtt_total_entries(dev_priv->gtt) * sizeof (uint32_t), KM_NOSLEEP);
904 ret = drm_agp_rw_gtt(dev, gtt_total_entries(dev_priv->gtt),
905 0, (void *) dev->gtt_dump, 0);
906 if (ret)
907 DRM_ERROR("failed to dump whole gtt");
908 panic("gpu hang");
909 }
910 }
911
register_dump(struct drm_device * dev)912 void register_dump(struct drm_device *dev)
913 {
914 struct drm_i915_private *dev_priv = dev->dev_private;
915
916 DRM_ERROR("PGTBL_ER: 0x%lx", I915_READ(PGTBL_ER));
917 DRM_ERROR("INSTPM: 0x%lx", I915_READ(INSTPM));
918 DRM_ERROR("EIR: 0x%lx", I915_READ(EIR));
919 DRM_ERROR("ERROR_GEN6: 0x%lx", I915_READ(ERROR_GEN6));
920
921 DRM_ERROR("Blitter command stream:");
922 DRM_ERROR(" IPEIR: 0x%08x",
923 I915_READ(0x22064));
924 DRM_ERROR(" IPEHR: 0x%08x",
925 I915_READ(0x22068));
926 DRM_ERROR(" INSTDONE: 0x%08x",
927 I915_READ(0x2206C));
928 DRM_ERROR(" ACTHD: 0x%08x",
929 I915_READ(0x22074));
930 DRM_ERROR("Render command stream:");
931 DRM_ERROR(" IPEIR: 0x%08x",
932 I915_READ(IPEIR_I965));
933 DRM_ERROR(" IPEHR: 0x%08x",
934 I915_READ(IPEHR_I965));
935 DRM_ERROR(" INSTDONE: 0x%08x",
936 I915_READ(INSTDONE_I965));
937 DRM_ERROR(" INSTPS: 0x%08x",
938 I915_READ(INSTPS));
939 DRM_ERROR(" INSTDONE1: 0x%08x",
940 I915_READ(INSTDONE1));
941 DRM_ERROR(" ACTHD: 0x%08x",
942 I915_READ(ACTHD_I965));
943 DRM_ERROR(" DMA_FADD_P: 0x%08x",
944 I915_READ(0x2078));
945
946 DRM_ERROR("Graphics Engine Fault 0x%lx",
947 I915_READ(0x04094));
948 DRM_ERROR("Media Engine Fault 0x%lx",
949 I915_READ(0x04194));
950 DRM_ERROR("Blitter Engine Fault 0x%lx",
951 I915_READ(0x04294));
952 }
953