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Searched defs:val (Results 1 – 25 of 33) sorted by relevance

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/gfx-drm/usr/src/uts/intel/io/i915/
H A Dintel_sideband.c30 u32 port, u32 opcode, u32 addr, u32 *val) in vlv_sideband_rw()
68 u32 val = 0; in vlv_punit_read() local
80 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val) in vlv_punit_write()
92 u32 val = 0; in vlv_nc_read() local
106 u32 val = 0; in vlv_dpio_read() local
114 void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val) in vlv_dpio_write()
H A Dintel_hdmi.c188 u32 val = I915_READ(reg); in ibx_write_infoframe() local
228 u32 val = I915_READ(reg); in cpt_write_infoframe() local
271 u32 val = I915_READ(reg); in vlv_write_infoframe() local
312 u32 val = I915_READ(ctl_reg); in hsw_write_infoframe() local
392 u32 val = I915_READ(reg); in g4x_set_infoframes() local
457 u32 val = I915_READ(reg); in ibx_set_infoframes() local
517 u32 val = I915_READ(reg); in cpt_set_infoframes() local
552 u32 val = I915_READ(reg); in vlv_set_infoframes() local
586 u32 val = I915_READ(reg); in hsw_set_infoframes() local
962 uint64_t val) in intel_hdmi_set_property()
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H A Di915_drv.c1223 u8 val; in i915_read8() local
1244 u16 val; in i915_read16() local
1265 u32 val; in i915_read32() local
1286 u64 val; in i915_read64() local
1306 u8 val) in i915_write8()
1328 u16 val) in i915_write16()
1350 u32 val) in i915_write32()
1372 u64 val) in i915_write64()
H A Ddvo_ch7017.c172 static bool ch7017_read(struct intel_dvo_device *dvo, u8 addr, u8 *val) in ch7017_read()
191 static bool ch7017_write(struct intel_dvo_device *dvo, uint8_t addr, uint8_t val) in ch7017_write()
209 u8 val; in ch7017_init() local
344 uint8_t val; in ch7017_dpms() local
372 uint8_t val; in ch7017_get_hw_state() local
384 uint8_t val; in ch7017_dump_regs() local
H A Dintel_panel.c334 u32 val; in i915_read_blc_pwm_ctl() local
388 static u32 intel_panel_compute_brightness(struct drm_device *dev, u32 val) in intel_panel_compute_brightness()
408 u32 val; in intel_panel_get_backlight() local
439 u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in intel_pch_panel_set_backlight() local
H A Dintel_ringbuffer.h55 #define I915_WRITE_TAIL(ring, val) I915_WRITE(RING_TAIL((ring)->mmio_base), val) argument
58 #define I915_WRITE_START(ring, val) I915_WRITE(RING_START((ring)->mmio_base), val) argument
61 #define I915_WRITE_HEAD(ring, val) I915_WRITE(RING_HEAD((ring)->mmio_base), val) argument
64 #define I915_WRITE_CTL(ring, val) I915_WRITE(RING_CTL((ring)->mmio_base), val) argument
67 #define I915_WRITE_IMR(ring, val) I915_WRITE(RING_IMR((ring)->mmio_base), val) argument
H A Dintel_ddi.c369 uint32_t val; in intel_ddi_put_crtc_pll() local
643 uint32_t reg, val; in intel_ddi_pll_mode_set() local
854 uint32_t val = I915_READ(reg); in intel_ddi_disable_transcoder_func() local
1073 uint32_t val; in intel_ddi_post_disable() local
1180 uint32_t val = I915_READ(LCPLL_CTL); in intel_ddi_pll_init() local
1203 uint32_t val; in intel_ddi_prepare_link_retrain() local
1242 uint32_t val; in intel_ddi_fdi_disable() local
H A Dintel_pm.c1881 u32 val; in sandybridge_update_wm() local
1983 u32 val; in ivybridge_update_wm() local
2521 uint32_t val; in hsw_write_wm_values() local
2737 u32 val; in sandybridge_update_sprite_wm() local
3430 u32 val, rp0; in valleyview_rps_max_freq() local
3443 u32 val, rpe; in valleyview_rps_rpe_freq() local
3522 u32 gtfifodbg, val; in valleyview_enable_rps() local
3802 unsigned long val; in intel_init_emon() local
4008 uint32_t val; in cpt_init_clock_gating() local
5123 int vlv_gpu_freq(int ddr_freq, int val) in vlv_gpu_freq()
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H A Di915_suspend.c54 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable) in i915_write_ar()
63 …atic void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val) in i915_write_indexed()
H A Dintel_display.c895 u32 val; in assert_pll() local
949 u32 val; in assert_fdi_tx() local
975 u32 val; in assert_fdi_rx() local
992 u32 val; in assert_fdi_tx_pll_enabled() local
1012 u32 val; in assert_fdi_rx_pll_enabled() local
1024 u32 val; in assert_panel_unlocked() local
1053 u32 val; in assert_pipe() local
1080 u32 val; in assert_plane() local
1099 u32 val; in assert_planes_disabled() local
1129 u32 val; in assert_sprites_disabled() local
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H A Dintel_i2c.c74 u32 val; in intel_i2c_quirk_set() local
308 u32 val, loop = 0; in gmbus_xfer_read() local
331 u32 val, loop; in gmbus_xfer_write() local
H A Ddvo_ch7xxx.c334 u8 val; in ch7xxx_get_hw_state() local
349 uint8_t val; in ch7xxx_dump_regs() local
H A Ddvo_sil164.c256 uint8_t val; in sil164_dump_regs() local
H A Ddvo_tfp410.c279 uint8_t val, val2; in tfp410_dump_regs() local
H A Di915_dma.c1159 int i915_bridge_dev_read_config_word(struct drm_i915_bridge_dev *bridge_dev, int where, u16 *val) in i915_bridge_dev_read_config_word()
1171 int i915_bridge_dev_write_config_word(struct drm_i915_bridge_dev *bridge_dev, int where, u16 val) in i915_bridge_dev_write_config_word()
H A Ddvo_ivch.c383 uint16_t val; in ivch_dump_regs() local
H A Ddvo_ns2501.c563 uint8_t val; in ns2501_dump_regs() local
H A Dintel_sdvo.c238 static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val) in intel_sdvo_write_sdvox()
776 static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val) in intel_sdvo_set_clock_rate_mult()
1321 u8 val; in intel_sdvo_get_config() local
2008 uint64_t val) in intel_sdvo_set_property()
H A Dintel_lvds.c842 unsigned int val; in compute_is_dual_link_lvds() local
/gfx-drm/usr/src/uts/common/io/drm/
H A Ddrm_sun_pci.c149 void pci_read_config_byte(struct pci_dev *pdev, int where, u8 *val) in pci_read_config_byte()
154 void pci_read_config_word(struct pci_dev *pdev, int where, u16 *val) in pci_read_config_word()
159 void pci_read_config_dword(struct pci_dev *pdev, int where, u32 *val) in pci_read_config_dword()
164 void pci_write_config_byte(struct pci_dev *pdev, int where, u8 val) in pci_write_config_byte()
169 void pci_write_config_word(struct pci_dev *pdev, int where, u16 val) in pci_write_config_word()
174 void pci_write_config_dword(struct pci_dev *pdev, int where, u32 val) in pci_write_config_dword()
/gfx-drm/usr/src/cmd/mdb/i915/
H A Di915.c662 i915_read(struct drm_i915_private *dev_priv, uintptr_t addr, uint32_t *val) in i915_read()
698 uint32_t val; in i915_register_read() local
746 uint32_t val; in i915_error_reg_dump() local
1382 uint32_t val; in i915_interrupt_info() local
1617 uint32_t val; in i915_fbc_status() local
1724 uint32_t val = 0; in i915_sr_status() local
1932 uint32_t val = 0; in i915_swizzle_info() local
2028 uint32_t val = 0; in i915_ppgtt_info() local
/gfx-drm/usr/src/uts/common/drm/
H A Ddrm_linux.h47 #define clamp_int64_t(val) \ argument
126 #define put_user(val,ptr) DRM_COPY_TO_USER(ptr,(&val),sizeof(val)) argument
H A Ddrm_fourcc.h160 #define fourcc_mod_code(vendor, val) \ argument
/gfx-drm/usr/src/uts/intel/io/radeon/
H A Dradeon_drv.h165 #define SET_RING_HEAD(dev_priv, val) \ argument
1008 #define RADEON_WRITE(reg, val) \ argument
1012 #define RADEON_WRITE8(reg, val) \ argument
1015 #define RADEON_WRITE_PLL(addr, val) \ argument
1022 #define RADEON_WRITE_PCIE(addr, val) \ argument
1175 #define OUT_RING_REG(reg, val) do { \ argument
/gfx-drm/usr/src/uts/intel/io/agpmaster/
H A Dagpmaster.c74 #define AGPM_WRITE(x, off, val) \ argument

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