xref: /illumos-gate/usr/src/uts/common/io/sfe/sfe_util.h (revision da14cebe)
1 /*
2  *  sfe_util.h: header to support the gem layer used by Masa Murayama
3  *
4  * Copyright (c) 2002-2008 Masayuki Murayama.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright notice,
10  *    this list of conditions and the following disclaimer.
11  *
12  * 2. Redistributions in binary form must reproduce the above copyright notice,
13  *    this list of conditions and the following disclaimer in the documentation
14  *    and/or other materials provided with the distribution.
15  *
16  * 3. Neither the name of the author nor the names of its contributors may be
17  *    used to endorse or promote products derived from this software without
18  *    specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24  * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
26  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
27  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
28  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
29  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
30  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31  * DAMAGE.
32  */
33 
34 /*
35  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
36  * Use is subject to license terms.
37  */
38 
39 #ifndef _SFE_UTIL_H_
40 #define	_SFE_UTIL_H_
41 #include <sys/mac_provider.h>
42 #include <sys/mac_ether.h>
43 
44 /*
45  * Useful macros and typedefs
46  */
47 
48 #define	GEM_NAME_LEN	32
49 
50 #define	GEM_TX_TIMEOUT		(drv_usectohz(5*1000000))
51 #define	GEM_TX_TIMEOUT_INTERVAL	(drv_usectohz(1*1000000))
52 #define	GEM_LINK_WATCH_INTERVAL	(drv_usectohz(1*1000000))	/* 1 sec */
53 
54 /* general return code */
55 #define	GEM_SUCCESS	0
56 #define	GEM_FAILURE	(-1)
57 
58 /* return code of gem_tx_done */
59 #define	INTR_RESTART_TX	0x80000000
60 
61 typedef	int32_t		seqnum_t;
62 
63 /*
64  * I/O instructions
65  */
66 #define	OUTB(dp, p, v)	\
67 	ddi_put8((dp)->regs_handle, \
68 		(void *)((caddr_t)((dp)->base_addr) + (p)), v)
69 #define	OUTW(dp, p, v)	\
70 	ddi_put16((dp)->regs_handle, \
71 		(void *)((caddr_t)((dp)->base_addr) + (p)), v)
72 #define	OUTL(dp, p, v)  \
73 	ddi_put32((dp)->regs_handle, \
74 	    (void *)((caddr_t)((dp)->base_addr) + (p)), v)
75 #define	OUTLINL(dp, p, v) \
76 	ddi_put32((dp)->regs_handle, \
77 	    (void *)((caddr_t)((dp)->base_addr) + (p)), v); \
78 	(void) INL((dp), (p))
79 #define	INB(dp, p)	\
80 	ddi_get8((dp)->regs_handle, \
81 		(void *)(((caddr_t)(dp)->base_addr) + (p)))
82 #define	INW(dp, p)	\
83 	ddi_get16((dp)->regs_handle, \
84 		(void *)(((caddr_t)(dp)->base_addr) + (p)))
85 #define	INL(dp, p)	\
86 	ddi_get32((dp)->regs_handle, \
87 		(void *)(((caddr_t)(dp)->base_addr) + (p)))
88 
89 struct gem_stats {
90 	uint32_t	intr;
91 
92 	uint32_t	crc;
93 	uint32_t	errrcv;
94 	uint32_t	overflow;
95 	uint32_t	frame;
96 	uint32_t	missed;
97 	uint32_t	runt;
98 	uint32_t	frame_too_long;
99 	uint32_t	norcvbuf;
100 	uint32_t	sqe;
101 
102 	uint32_t	collisions;
103 	uint32_t	first_coll;
104 	uint32_t	multi_coll;
105 	uint32_t	excoll;
106 	uint32_t	xmit_internal_err;
107 	uint32_t	nocarrier;
108 	uint32_t	defer;
109 	uint32_t	errxmt;
110 	uint32_t	underflow;
111 	uint32_t	xmtlatecoll;
112 	uint32_t	noxmtbuf;
113 	uint32_t	jabber;
114 
115 	uint64_t	rbytes;
116 	uint64_t	obytes;
117 	uint64_t	rpackets;
118 	uint64_t	opackets;
119 	uint32_t	rbcast;
120 	uint32_t	obcast;
121 	uint32_t	rmcast;
122 	uint32_t	omcast;
123 	uint32_t	rcv_internal_err;
124 };
125 #define	GEM_MAXTXSEGS		4
126 #define	GEM_MAXRXSEGS		1
127 
128 #define	GEM_MAXTXFRAGS		8
129 #define	GEM_MAXRXFRAGS		4
130 /* TX buffer management */
131 struct txbuf {
132 	struct txbuf		*txb_next;
133 
134 	/* pointer to original mblk */
135 	mblk_t			*txb_mp;
136 
137 	/* dma mapping for current packet */
138 	ddi_dma_cookie_t	txb_dmacookie[GEM_MAXTXFRAGS];
139 	uint_t			txb_nfrags;
140 
141 	/* bounce buffer management */
142 	ddi_dma_handle_t	txb_bdh;
143 	ddi_acc_handle_t	txb_bah;
144 	caddr_t			txb_buf;	/* vaddr of bounce buffer */
145 	uint64_t		txb_buf_dma;	/* paddr of bounce buffer */
146 
147 	/* timeout management */
148 	clock_t			txb_stime;
149 
150 	/* Hardware descriptor info */
151 	seqnum_t		txb_desc;
152 	int			txb_ndescs;
153 	uint64_t		txb_flag;
154 };
155 
156 
157 /* RX buffer management */
158 struct rxbuf {
159 	/* Hardware independent section */
160 	struct rxbuf		*rxb_next;
161 	struct gem_dev		*rxb_devp;
162 
163 	/* dma mapping management */
164 	ddi_dma_handle_t	rxb_dh;
165 	caddr_t			rxb_buf;
166 	size_t			rxb_buf_len;
167 	ddi_dma_cookie_t	rxb_dmacookie[GEM_MAXRXFRAGS];
168 	uint_t			rxb_nfrags;
169 
170 	/* bounce buffer management */
171 	ddi_acc_handle_t	rxb_bah;
172 };
173 
174 struct mcast_addr {
175 	struct ether_addr	addr;
176 	uint32_t		hash;
177 };
178 
179 #define	GEM_MAXMC		64
180 #define	GEM_MCALLOC		(sizeof (struct mcast_addr) * GEM_MAXMC)
181 
182 #define	SUB(x, y)		((seqnum_t)((x) - (y)))
183 #define	SLOT(seqnum, size)	(((unsigned int)(seqnum)) & ((size)-1))
184 
185 /*
186  * mac soft state
187  */
188 struct gem_dev {
189 	dev_info_t		*dip;
190 	mac_handle_t		mh;
191 	char			name[GEM_NAME_LEN];
192 	void			*base_addr;
193 	ddi_acc_handle_t	regs_handle;
194 	ddi_iblock_cookie_t	iblock_cookie;
195 
196 	/* MAC address information */
197 	struct ether_addr	cur_addr;
198 	struct ether_addr	dev_addr;
199 
200 	/* Descriptor rings, io area */
201 	ddi_dma_handle_t	desc_dma_handle;
202 	ddi_acc_handle_t	desc_acc_handle;
203 	caddr_t			rx_ring;
204 	caddr_t			tx_ring;
205 	caddr_t			io_area;
206 	/* caddr_t			rx_buf; */
207 
208 	uint64_t		rx_ring_dma;
209 	uint64_t		tx_ring_dma;
210 	uint64_t		io_area_dma;
211 
212 	/* RX slot ring management */
213 	kmutex_t		intrlock;
214 	boolean_t		intr_busy;
215 	seqnum_t		rx_active_head;
216 	seqnum_t		rx_active_tail;
217 	mac_resource_handle_t	mac_rx_ring_ha;
218 	/* Rx buffer management */
219 	struct rxbuf		*rx_buf_head;
220 	struct rxbuf		*rx_buf_tail;
221 	struct rxbuf		*rx_buf_freelist;
222 	int			rx_buf_allocated;
223 	int			rx_buf_freecnt;
224 	int			rx_buf_len;
225 
226 	/* TX descriptor ring management */
227 	seqnum_t		tx_desc_head;
228 	seqnum_t		tx_desc_tail;
229 	seqnum_t		tx_desc_intr;
230 
231 	/* TX buffur ring management */
232 	kmutex_t		xmitlock;
233 	kcondvar_t		tx_drain_cv;
234 	seqnum_t		tx_active_head;
235 	seqnum_t		tx_active_tail;
236 	seqnum_t		tx_softq_head;
237 	seqnum_t		tx_softq_tail;
238 	seqnum_t		tx_free_head;
239 	seqnum_t		tx_free_tail;
240 	int			tx_max_packets;
241 
242 	/* TX buffer resource management */
243 	struct txbuf		*tx_buf;
244 	seqnum_t		tx_slots_base;
245 
246 	/* TX state management */
247 	int			tx_busy;
248 	int			tx_reclaim_busy;
249 	clock_t			tx_blocked;
250 
251 	/* NIC state */
252 	volatile boolean_t	mac_active;	/* tx and rx are running */
253 	volatile int		nic_state;	/* logical driver state */
254 #define	NIC_STATE_STOPPED	0
255 #define	NIC_STATE_INITIALIZED	1
256 #define	NIC_STATE_ONLINE	2
257 	volatile boolean_t	mac_suspended;
258 
259 	/* robustness: timer and watchdog */
260 	volatile timeout_id_t	timeout_id;
261 
262 
263 	/* MII management */
264 	boolean_t		anadv_autoneg:1;
265 	boolean_t		anadv_1000fdx:1;
266 	boolean_t		anadv_1000hdx:1;
267 	boolean_t		anadv_100t4:1;
268 	boolean_t		anadv_100fdx:1;
269 	boolean_t		anadv_100hdx:1;
270 	boolean_t		anadv_10fdx:1;
271 	boolean_t		anadv_10hdx:1;
272 	boolean_t		anadv_flow_control:2;
273 	boolean_t		mii_advert_ro:1;
274 
275 	boolean_t		full_duplex:1;
276 	int			speed:3;
277 #define		GEM_SPD_10	0
278 #define		GEM_SPD_100	1
279 #define		GEM_SPD_1000	2
280 #define		GEM_SPD_NUM	3
281 	unsigned int		flow_control:2;
282 #define		FLOW_CONTROL_NONE	0
283 #define		FLOW_CONTROL_SYMMETRIC	1
284 #define		FLOW_CONTROL_TX_PAUSE	2
285 #define		FLOW_CONTROL_RX_PAUSE	3
286 
287 	boolean_t		mii_supress_msg:1;
288 
289 	uint32_t		mii_phy_id;
290 	uint16_t		mii_status;
291 	uint16_t		mii_advert;
292 	uint16_t		mii_lpable;
293 	uint16_t		mii_exp;
294 	uint16_t		mii_ctl1000;
295 	uint16_t		mii_stat1000;
296 	uint16_t		mii_xstatus;
297 	int8_t			mii_phy_addr;	/* must be signed */
298 
299 	uint8_t			mii_state;
300 #define		MII_STATE_UNKNOWN		0
301 #define		MII_STATE_RESETTING		1
302 #define		MII_STATE_AUTONEGOTIATING	2
303 #define		MII_STATE_AN_DONE		3
304 #define		MII_STATE_MEDIA_SETUP		4
305 #define		MII_STATE_LINKUP		5
306 #define		MII_STATE_LINKDOWN		6
307 
308 	clock_t			mii_last_check;	/* in tick */
309 	clock_t			mii_timer;	/* in tick */
310 #define		MII_RESET_TIMEOUT	drv_usectohz(1000*1000)
311 #define		MII_AN_TIMEOUT		drv_usectohz(5000*1000)
312 #define		MII_LINKDOWN_TIMEOUT	drv_usectohz(10000*1000)
313 	clock_t			mii_interval;	/* in tick */
314 	clock_t			linkup_delay;	/* in tick */
315 
316 	volatile timeout_id_t	link_watcher_id;
317 
318 	ddi_softintr_t		soft_id;
319 
320 	/* multcast list management */
321 	int16_t			mc_count;
322 	int16_t			mc_count_req;
323 	struct mcast_addr	*mc_list;
324 	uint32_t		rxmode;
325 #define		RXMODE_PROMISC		0x01
326 #define		RXMODE_ALLMULTI_REQ	0x02
327 #define		RXMODE_MULTI_OVF	0x04
328 #define		RXMODE_ENABLE		0x08
329 #define		RXMODE_ALLMULTI		(RXMODE_ALLMULTI_REQ | RXMODE_MULTI_OVF)
330 #define		RXMODE_BITS	\
331 			"\020"	\
332 			"\004ENABLE"	\
333 			"\003MULTI_OVF"	\
334 			"\002ALLMULTI_REQ"	\
335 			"\001PROMISC"
336 
337 	/* statistcs */
338 	struct gem_stats		stats;
339 
340 	/* pointer to local structure */
341 	void			*private;
342 	int			priv_size;
343 
344 	/* polling mode */
345 	int			poll_pkt_delay;	/* in number of packets */
346 
347 	/* descriptor area */
348 	int			tx_desc_size;
349 	int			rx_desc_size;
350 
351 	/* configuration */
352 	struct gem_conf {
353 		/* name */
354 		char	gc_name[GEM_NAME_LEN];
355 
356 		/* specification on tx and rx dma engine */
357 		long	gc_tx_buf_align;
358 		int	gc_tx_max_frags;
359 		int	gc_tx_max_descs_per_pkt;
360 		int	gc_tx_buf_size;
361 		int	gc_tx_buf_limit;
362 		int	gc_tx_desc_unit_shift;
363 		int	gc_tx_ring_size;
364 		int	gc_tx_ring_limit;
365 		int	gc_tx_copy_thresh;
366 		boolean_t gc_tx_auto_pad;
367 		boolean_t gc_tx_desc_write_oo;
368 
369 		long	gc_rx_buf_align;
370 		int	gc_rx_max_frags;
371 		int	gc_rx_desc_unit_shift;
372 		int	gc_rx_ring_size;
373 		int	gc_rx_copy_thresh;
374 		int	gc_rx_buf_max;
375 		int	gc_rx_header_len;
376 
377 		int	gc_io_area_size;
378 
379 		/* memory mapping attributes */
380 		struct ddi_device_acc_attr	gc_dev_attr;
381 		struct ddi_device_acc_attr	gc_buf_attr;
382 		struct ddi_device_acc_attr	gc_desc_attr;
383 
384 		/* dma attributes */
385 		ddi_dma_attr_t		gc_dma_attr_desc;
386 		ddi_dma_attr_t		gc_dma_attr_txbuf;
387 		ddi_dma_attr_t		gc_dma_attr_rxbuf;
388 
389 		/* tx time out parameters */
390 		clock_t	gc_tx_timeout;
391 		clock_t	gc_tx_timeout_interval;
392 
393 		/* auto negotiation capability */
394 		int		gc_flow_control;
395 
396 		/* MII mode */
397 		int	gc_mii_mode;
398 #define		GEM_MODE_100BASETX	0
399 #define		GEM_MODE_1000BASET	1
400 #define		GEM_MODE_1000BASETX	2
401 
402 		/* MII link state watch parameters */
403 		clock_t	gc_mii_linkdown_timeout;
404 		clock_t	gc_mii_link_watch_interval;
405 		clock_t	gc_mii_reset_timeout;
406 
407 		clock_t	gc_mii_an_watch_interval;
408 		clock_t	gc_mii_an_timeout;
409 		clock_t	gc_mii_an_wait;
410 		clock_t	gc_mii_an_delay;
411 
412 		/* MII configuration */
413 		int	gc_mii_addr_min;
414 		int	gc_mii_linkdown_action;
415 		int	gc_mii_linkdown_timeout_action;
416 #define		MII_ACTION_NONE		0
417 #define		MII_ACTION_RESET	1
418 #define		MII_ACTION_RSA		2
419 		boolean_t	gc_mii_dont_reset;
420 		boolean_t	gc_mii_an_oneshot;
421 		boolean_t	gc_mii_hw_link_detection;
422 		boolean_t	gc_mii_stop_mac_on_linkdown;
423 
424 		/* I/O methods */
425 
426 		/* mac operation */
427 		int	(*gc_attach_chip)(struct gem_dev *dp);
428 		int	(*gc_reset_chip)(struct gem_dev *dp);
429 		int	(*gc_init_chip)(struct gem_dev *dp);
430 		int	(*gc_start_chip)(struct gem_dev *dp);
431 		int	(*gc_stop_chip)(struct gem_dev *dp);
432 		uint32_t (*gc_multicast_hash)(struct gem_dev *dp, uint8_t *);
433 		int	(*gc_set_rx_filter)(struct gem_dev *dp);
434 		int	(*gc_set_media)(struct gem_dev *dp);
435 		int	(*gc_get_stats)(struct gem_dev *dp);
436 		uint_t	(*gc_interrupt)(struct gem_dev *dp);
437 
438 		/* descriptor operation */
439 		int	(*gc_tx_desc_write)(struct gem_dev *dp, int slot,
440 				ddi_dma_cookie_t *dmacookie,
441 				int frags, uint64_t flag);
442 #define			GEM_TXFLAG_INTR		0x00000001ull
443 #define			GEM_TXFLAG_TCP		0x00000002ull
444 #define				GEM_TXFLAG_TCP_SHIFT		1ull
445 #define			GEM_TXFLAG_UDP		0x00000004ull
446 #define				GEM_TXFLAG_UDP_SHIFT		2ull
447 #define			GEM_TXFLAG_IPv4		0x00000008ull
448 #define				GEM_TXFLAG_IPv4_SHIFT		3ull
449 #define			GEM_TXFLAG_IPv6		0x00000010ull
450 #define				GEM_TXFLAG_IPv6_SHIFT		4ull
451 #define			GEM_TXFLAG_HEAD		0x00000020ull
452 #define			GEM_TXFLAG_TAIL		0x00000040ull
453 #define			GEM_TXFLAG_SWVTAG	0x00000080ull
454 #define			GEM_TXFLAG_PRIVATE	0x0000ff00ull
455 #define				GEM_TXFLAG_PRIVATE_SHIFT	8ull
456 #define				GEM_TXFLAG_PRIVATE_MASK	0xffull
457 #define			GEM_TXFLAG_VID		0x0fff0000ull
458 #define				GEM_TXFLAG_VID_SHIFT		16ull
459 #define				GEM_TXFLAG_VID_MASK		0xfffull
460 #define			GEM_TXFLAG_CFI		0x10000000ull
461 #define			GEM_TXFLAG_PRI		0xe0000000ull
462 #define				GEM_TXFLAG_PRI_SHIFT		29ull
463 #define				GEM_TXFLAG_PRI_MASK		0x7ull
464 #define			GEM_TXFLAG_VTAG		0xffff0000ull
465 #define				GEM_TXFLAG_VTAG_SHIFT		16ull
466 #define			GEM_TXFLAG_HCKSTART	0x000000ff00000000ull
467 #define				GEM_TXFLAG_HCKSTART_SHIFT	32ull
468 #define			GEM_TXFLAG_HCKSTUFF	0x0000ff0000000000ull
469 #define				GEM_TXFLAG_HCKSTUFF_SHIFT	40ull
470 #define			GEM_TXFLAG_TCPHLEN	0x0000ff0000000000ull
471 #define				GEM_TXFLAG_TCPHLEN_SHIFT	40ull
472 #define			GEM_TXFLAG_MSS		0xffff000000000000ull
473 #define				GEM_TXFLAG_MSS_SHIFT	48ull
474 
475 		void (*gc_tx_start) (struct gem_dev *dp, int slot, int frags);
476 		void	(*gc_rx_desc_write)(struct gem_dev *dp, int slot,
477 			    ddi_dma_cookie_t *dmacookie, int frags);
478 		void	(*gc_rx_start)(struct gem_dev *dp, int slot, int frags);
479 
480 		uint_t	(*gc_tx_desc_stat)
481 			(struct gem_dev *dp, int slot, int descs);
482 #define			GEM_TX_DONE	0x00010000
483 #define			GEM_TX_ERR	0x00020000
484 
485 
486 		uint64_t (*gc_rx_desc_stat)
487 				(struct gem_dev *dp, int slot, int frags);
488 
489 #define			GEM_RX_CKSUM		0xffff000000000000ull
490 #define			GEM_RX_CKSUM_SHIFT	48
491 #define			GEM_RX_PRI		0x0000e00000000000ull
492 #define			GEM_RX_PRI_SHIFT	45
493 #define			GEM_RX_CFI		0x0000100000000000ull
494 #define			GEM_RX_VID		0x00000fff00000000ull
495 #define			GEM_RX_VID_SHIFT	32
496 #define			GEM_RX_VTAG		0x0000ffff00000000ull
497 #define			GEM_RX_VTAG_SHIFT	32
498 
499 #define			GEM_RX_CKSUM_IPv6	0x00080000ul
500 #define			GEM_RX_CKSUM_IPv6_SHIFT	19
501 #define			GEM_RX_CKSUM_IPv4	0x00040000ul
502 #define			GEM_RX_CKSUM_IPv4_SHIFT	18
503 #define			GEM_RX_CKSUM_UDP	0x00020000ul
504 #define			GEM_RX_CKSUM_UDP_SHIFT	17
505 #define			GEM_RX_CKSUM_TCP	0x00010000ul
506 #define			GEM_RX_CKSUM_TCP_SHIFT	16
507 #define			GEM_RX_ERR		0x00008000ul
508 #define			GEM_RX_DONE		0x00004000ul
509 #define			GEM_RX_LEN		0x00003ffful	/* 16KB - 1 */
510 
511 		void	(*gc_tx_desc_init)(struct gem_dev *dp, int slot);
512 		void	(*gc_rx_desc_init)(struct gem_dev *dp, int slot);
513 		void	(*gc_tx_desc_clean)(struct gem_dev *dp, int slot);
514 		void	(*gc_rx_desc_clean)(struct gem_dev *dp, int slot);
515 
516 		/* mii operations */
517 		int	(*gc_mii_probe)(struct gem_dev *dp);
518 		int	(*gc_mii_init)(struct gem_dev *dp);
519 		int	(*gc_mii_config)(struct gem_dev *dp);
520 		void	(*gc_mii_sync)(struct gem_dev *dp);
521 		uint16_t (*gc_mii_read)(struct gem_dev *dp, uint_t reg);
522 		void (*gc_mii_write)(struct gem_dev *dp,
523 			uint_t reg, uint16_t val);
524 		void (*gc_mii_tune_phy)(struct gem_dev *dp);
525 
526 		/* packet in/out operation for copy-style  */
527 		void (*gc_put_packet)(struct gem_dev *dp,
528 			mblk_t *, void *, size_t);
529 		mblk_t	*(*gc_get_packet)(struct gem_dev *dp,
530 			struct rxbuf *, size_t);
531 		int	gc_nports;
532 
533 		/* hw checksum */
534 		uint32_t	gc_hck_rx_start;
535 	} gc;
536 
537 	uint32_t	misc_flag;
538 #define		GEM_LSO			0x00000400
539 #define		GEM_CTRL_PKT		0x00000200
540 #define		GEM_SOFTINTR		0x00000100
541 #define		GEM_POLL_RXONLY		0x00000080
542 #define		GEM_VLAN_HARD		0x00000040
543 #define		GEM_VLAN_SOFT		0x00000020
544 #define		GEM_VLAN		(GEM_VLAN_HARD | GEM_VLAN_SOFT)
545 #define		GEM_CKSUM_HEADER_IPv4	0x00000010
546 #define		GEM_CKSUM_PARTIAL	0x00000008
547 #define		GEM_CKSUM_FULL_IPv6	0x00000004
548 #define		GEM_CKSUM_FULL_IPv4	0x00000002
549 #define		GEM_NOINTR		0x00000001
550 
551 	volatile timeout_id_t	intr_watcher_id;
552 
553 	uint_t	mtu;
554 
555 	/* performance tuning parameters */
556 	uint_t	txthr;		/* tx fifo threshoold */
557 	uint_t	txmaxdma;	/* tx max dma burst size */
558 	uint_t	rxthr;		/* rx fifo threshoold */
559 	uint_t	rxmaxdma;	/* tx max dma burst size */
560 
561 	/* kstat stuff */
562 	kstat_t	*ksp;
563 
564 	/* multiple port device support */
565 	struct	gem_dev	*next;	/* pointer to next port on the same device */
566 	int		port;
567 
568 	/* ndd stuff */
569 	caddr_t	nd_data_p;
570 	caddr_t	nd_arg_p;
571 
572 #ifdef GEM_DEBUG_LEVEL
573 	int	tx_cnt;
574 #endif
575 };
576 
577 /*
578  * Exported functions
579  */
580 boolean_t gem_get_mac_addr_conf(struct gem_dev *);
581 int gem_mii_probe_default(struct gem_dev *);
582 int gem_mii_config_default(struct gem_dev *);
583 boolean_t gem_mii_link_check(struct gem_dev *dp);
584 uint16_t gem_mii_read(struct gem_dev *, uint_t);
585 void gem_mii_write(struct gem_dev *, uint_t, uint16_t);
586 int gem_reclaim_txbuf(struct gem_dev *dp);
587 int gem_restart_nic(struct gem_dev *dp, uint_t flags);
588 #define	GEM_RESTART_NOWAIT	0x00000002
589 #define	GEM_RESTART_KEEP_BUF	0x00000001
590 boolean_t gem_tx_done(struct gem_dev *);
591 int gem_receive(struct gem_dev *);
592 int gem_receive_copy(struct gem_dev *);
593 struct gem_dev *gem_do_attach(dev_info_t *, int,
594 		struct gem_conf *, void *, ddi_acc_handle_t *, void *, int);
595 
596 mblk_t *gem_send_common(struct gem_dev *, mblk_t *, uint32_t);
597 #define	GEM_SEND_COPY	0x00008000
598 #define	GEM_SEND_CTRL	0x000000ff	/* private flags for control packets */
599 #define	GEM_SEND_VTAG	0xffff0000
600 #define	GEM_SEND_VTAG_SHIFT	16
601 
602 mblk_t *gem_get_packet_default(struct gem_dev *, struct rxbuf *, size_t);
603 
604 uint32_t gem_ether_crc_le(const uint8_t *addr, int len);
605 uint32_t gem_ether_crc_be(const uint8_t *addr, int len);
606 int gem_do_detach(dev_info_t *);
607 
608 int gem_getlongprop_buf(dev_t dev, dev_info_t *dip,
609 	int flags, char *name, void *buf, int *lenp);
610 int gem_getprop(dev_t dev, dev_info_t *dip,
611 	int flags, char *name, int defvalue);
612 
613 struct rxbuf *gem_get_rxbuf(struct gem_dev *, int);
614 
615 void gem_rx_desc_dma_sync(struct gem_dev *, int, int, int);
616 void gem_tx_desc_dma_sync(struct gem_dev *, int, int, int);
617 
618 int gem_resume(dev_info_t *);
619 int gem_suspend(dev_info_t *);
620 uint8_t gem_search_pci_cap(dev_info_t *dip, ddi_acc_handle_t, uint8_t);
621 int gem_pci_set_power_state(dev_info_t *, ddi_acc_handle_t, uint_t);
622 int gem_pci_regs_map_setup(dev_info_t *, uint32_t, uint32_t,
623 	struct ddi_device_acc_attr *, caddr_t *, ddi_acc_handle_t *);
624 void gem_mod_init(struct dev_ops *, char *);
625 void gem_mod_fini(struct dev_ops *);
626 
627 #define	GEM_GET_DEV(dip) \
628 	((struct gem_dev *)(ddi_get_driver_private(dip)))
629 #endif /* _SFE_UTIL_H_ */
630