xref: /illumos-gate/usr/src/cmd/bhyve/pci_emul.h (revision 32640292)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright (c) 2011 NetApp, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  *
16  * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19  * ARE DISCLAIMED.  IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26  * SUCH DAMAGE.
27  */
28 /*
29  * Copyright 2018 Joyent, Inc.
30  */
31 
32 #ifndef _PCI_EMUL_H_
33 #define _PCI_EMUL_H_
34 
35 #include <sys/types.h>
36 #include <sys/queue.h>
37 #include <sys/kernel.h>
38 #include <sys/nv.h>
39 #include <sys/pciio.h>
40 #include <sys/_pthreadtypes.h>
41 
42 #include <dev/pci/pcireg.h>
43 
44 #include <assert.h>
45 
46 #define	PCI_BARMAX	PCIR_MAX_BAR_0	/* BAR registers in a Type 0 header */
47 #define PCI_BARMAX_WITH_ROM (PCI_BARMAX + 1)
48 #define PCI_ROM_IDX (PCI_BARMAX + 1)
49 
50 struct vmctx;
51 struct pci_devinst;
52 struct memory_region;
53 
54 struct pci_devemu {
55 	const char      *pe_emu;	/* Name of device emulation */
56 
57 	/* instance creation */
58 	int       (*pe_init)(struct pci_devinst *, nvlist_t *);
59 	int	(*pe_legacy_config)(nvlist_t *, const char *);
60 	const char *pe_alias;
61 
62 	/* ACPI DSDT enumeration */
63 	void	(*pe_write_dsdt)(struct pci_devinst *);
64 
65 	/* config space read/write callbacks */
66 	int	(*pe_cfgwrite)(struct pci_devinst *pi, int offset,
67 			       int bytes, uint32_t val);
68 	int	(*pe_cfgread)(struct pci_devinst *pi, int offset,
69 			      int bytes, uint32_t *retval);
70 
71 	/* BAR read/write callbacks */
72 	void      (*pe_barwrite)(struct pci_devinst *pi, int baridx,
73 				 uint64_t offset, int size, uint64_t value);
74 	uint64_t  (*pe_barread)(struct pci_devinst *pi, int baridx,
75 				uint64_t offset, int size);
76 
77 	void	(*pe_baraddr)(struct pci_devinst *pi,
78 			      int baridx, int enabled, uint64_t address);
79 #ifndef __FreeBSD__
80 	void	(*pe_lintrupdate)(struct pci_devinst *pi);
81 #endif /* __FreeBSD__ */
82 };
83 #define PCI_EMUL_SET(x)   DATA_SET(pci_devemu_set, x)
84 
85 enum pcibar_type {
86 	PCIBAR_NONE,
87 	PCIBAR_IO,
88 	PCIBAR_MEM32,
89 	PCIBAR_MEM64,
90 	PCIBAR_MEMHI64,
91 	PCIBAR_ROM,
92 };
93 
94 struct pcibar {
95 	enum pcibar_type	type;		/* io or memory */
96 	uint64_t		size;
97 	uint64_t		addr;
98 	uint8_t			lobits;
99 };
100 
101 #define PI_NAMESZ	40
102 
103 struct msix_table_entry {
104 	uint64_t	addr;
105 	uint32_t	msg_data;
106 	uint32_t	vector_control;
107 } __packed;
108 
109 /*
110  * In case the structure is modified to hold extra information, use a define
111  * for the size that should be emulated.
112  */
113 #define	MSIX_TABLE_ENTRY_SIZE	16
114 #define MAX_MSIX_TABLE_ENTRIES	2048
115 #define	PBA_SIZE(msgnum)	(roundup2((msgnum), 64) / 8)
116 
117 enum lintr_stat {
118 	IDLE,
119 	ASSERTED,
120 	PENDING
121 };
122 
123 struct pci_devinst {
124 	struct pci_devemu *pi_d;
125 	struct vmctx *pi_vmctx;
126 	uint8_t	  pi_bus, pi_slot, pi_func;
127 	char	  pi_name[PI_NAMESZ];
128 	int	  pi_bar_getsize;
129 	int	  pi_prevcap;
130 	int	  pi_capend;
131 
132 	struct {
133 		int8_t    	pin;
134 		enum lintr_stat	state;
135 		int		pirq_pin;
136 		int	  	ioapic_irq;
137 		pthread_mutex_t	lock;
138 	} pi_lintr;
139 
140 	struct {
141 		int		enabled;
142 		uint64_t	addr;
143 		uint64_t	msg_data;
144 		int		maxmsgnum;
145 	} pi_msi;
146 
147 	struct {
148 		int	enabled;
149 		int	table_bar;
150 		int	pba_bar;
151 		uint32_t table_offset;
152 		int	table_count;
153 		uint32_t pba_offset;
154 		int	pba_size;
155 		int	function_mask;
156 		struct msix_table_entry *table;	/* allocated at runtime */
157 		void	*pba_page;
158 		int	pba_page_offset;
159 		uint8_t *mapped_addr;
160 		size_t	mapped_size;
161 	} pi_msix;
162 
163 	void      *pi_arg;		/* devemu-private data */
164 
165 	u_char	  pi_cfgdata[PCI_REGMAX + 1];
166 	/* ROM is handled like a BAR */
167 	struct pcibar pi_bar[PCI_BARMAX_WITH_ROM + 1];
168 	uint64_t pi_romoffset;
169 };
170 
171 struct msicap {
172 	uint8_t		capid;
173 	uint8_t		nextptr;
174 	uint16_t	msgctrl;
175 	uint32_t	addrlo;
176 	uint32_t	addrhi;
177 	uint16_t	msgdata;
178 } __packed;
179 static_assert(sizeof(struct msicap) == 14, "compile-time assertion failed");
180 
181 struct msixcap {
182 	uint8_t		capid;
183 	uint8_t		nextptr;
184 	uint16_t	msgctrl;
185 	uint32_t	table_info;	/* bar index and offset within it */
186 	uint32_t	pba_info;	/* bar index and offset within it */
187 } __packed;
188 static_assert(sizeof(struct msixcap) == 12, "compile-time assertion failed");
189 
190 struct pciecap {
191 	uint8_t		capid;
192 	uint8_t		nextptr;
193 	uint16_t	pcie_capabilities;
194 
195 	uint32_t	dev_capabilities;	/* all devices */
196 	uint16_t	dev_control;
197 	uint16_t	dev_status;
198 
199 	uint32_t	link_capabilities;	/* devices with links */
200 	uint16_t	link_control;
201 	uint16_t	link_status;
202 
203 	uint32_t	slot_capabilities;	/* ports with slots */
204 	uint16_t	slot_control;
205 	uint16_t	slot_status;
206 
207 	uint16_t	root_control;		/* root ports */
208 	uint16_t	root_capabilities;
209 	uint32_t	root_status;
210 
211 	uint32_t	dev_capabilities2;	/* all devices */
212 	uint16_t	dev_control2;
213 	uint16_t	dev_status2;
214 
215 	uint32_t	link_capabilities2;	/* devices with links */
216 	uint16_t	link_control2;
217 	uint16_t	link_status2;
218 
219 	uint32_t	slot_capabilities2;	/* ports with slots */
220 	uint16_t	slot_control2;
221 	uint16_t	slot_status2;
222 } __packed;
223 static_assert(sizeof(struct pciecap) == 60, "compile-time assertion failed");
224 
225 typedef void (*pci_lintr_cb)(int b, int s, int pin, int pirq_pin,
226     int ioapic_irq, void *arg);
227 
228 int	init_pci(struct vmctx *ctx);
229 void	pci_callback(void);
230 uint32_t pci_config_read_reg(const struct pcisel *host_sel, nvlist_t *nvl,
231 	    uint32_t reg, uint8_t size, uint32_t def);
232 int	pci_emul_alloc_bar(struct pci_devinst *pdi, int idx,
233 	    enum pcibar_type type, uint64_t size);
234 int 	pci_emul_alloc_rom(struct pci_devinst *const pdi, const uint64_t size,
235     	    void **const addr);
236 int 	pci_emul_add_boot_device(struct pci_devinst *const pi,
237 	    const int bootindex);
238 int	pci_emul_add_msicap(struct pci_devinst *pi, int msgnum);
239 int	pci_emul_add_pciecap(struct pci_devinst *pi, int pcie_device_type);
240 void	pci_emul_capwrite(struct pci_devinst *pi, int offset, int bytes,
241 	    uint32_t val, uint8_t capoff, int capid);
242 void	pci_emul_cmd_changed(struct pci_devinst *pi, uint16_t old);
243 void	pci_generate_msi(struct pci_devinst *pi, int msgnum);
244 void	pci_generate_msix(struct pci_devinst *pi, int msgnum);
245 void	pci_lintr_assert(struct pci_devinst *pi);
246 void	pci_lintr_deassert(struct pci_devinst *pi);
247 void	pci_lintr_request(struct pci_devinst *pi);
248 int	pci_msi_enabled(struct pci_devinst *pi);
249 int	pci_msix_enabled(struct pci_devinst *pi);
250 int	pci_msix_table_bar(struct pci_devinst *pi);
251 int	pci_msix_pba_bar(struct pci_devinst *pi);
252 int	pci_msi_maxmsgnum(struct pci_devinst *pi);
253 int	pci_parse_legacy_config(nvlist_t *nvl, const char *opt);
254 int	pci_parse_slot(char *opt);
255 void    pci_print_supported_devices(void);
256 void	pci_populate_msicap(struct msicap *cap, int msgs, int nextptr);
257 int	pci_emul_add_msixcap(struct pci_devinst *pi, int msgnum, int barnum);
258 int	pci_emul_msix_twrite(struct pci_devinst *pi, uint64_t offset, int size,
259 			     uint64_t value);
260 uint64_t pci_emul_msix_tread(struct pci_devinst *pi, uint64_t offset, int size);
261 int	pci_count_lintr(int bus);
262 void	pci_walk_lintr(int bus, pci_lintr_cb cb, void *arg);
263 void	pci_write_dsdt(void);
264 uint64_t pci_ecfg_base(void);
265 int	pci_bus_configured(int bus);
266 
267 static __inline void
pci_set_cfgdata8(struct pci_devinst * pi,int offset,uint8_t val)268 pci_set_cfgdata8(struct pci_devinst *pi, int offset, uint8_t val)
269 {
270 	assert(offset <= PCI_REGMAX);
271 	*(uint8_t *)(pi->pi_cfgdata + offset) = val;
272 }
273 
274 static __inline void
pci_set_cfgdata16(struct pci_devinst * pi,int offset,uint16_t val)275 pci_set_cfgdata16(struct pci_devinst *pi, int offset, uint16_t val)
276 {
277 	assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
278 	*(uint16_t *)(pi->pi_cfgdata + offset) = val;
279 }
280 
281 static __inline void
pci_set_cfgdata32(struct pci_devinst * pi,int offset,uint32_t val)282 pci_set_cfgdata32(struct pci_devinst *pi, int offset, uint32_t val)
283 {
284 	assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
285 	*(uint32_t *)(pi->pi_cfgdata + offset) = val;
286 }
287 
288 static __inline uint8_t
pci_get_cfgdata8(struct pci_devinst * pi,int offset)289 pci_get_cfgdata8(struct pci_devinst *pi, int offset)
290 {
291 	assert(offset <= PCI_REGMAX);
292 	return (*(uint8_t *)(pi->pi_cfgdata + offset));
293 }
294 
295 static __inline uint16_t
pci_get_cfgdata16(struct pci_devinst * pi,int offset)296 pci_get_cfgdata16(struct pci_devinst *pi, int offset)
297 {
298 	assert(offset <= (PCI_REGMAX - 1) && (offset & 1) == 0);
299 	return (*(uint16_t *)(pi->pi_cfgdata + offset));
300 }
301 
302 static __inline uint32_t
pci_get_cfgdata32(struct pci_devinst * pi,int offset)303 pci_get_cfgdata32(struct pci_devinst *pi, int offset)
304 {
305 	assert(offset <= (PCI_REGMAX - 3) && (offset & 3) == 0);
306 	return (*(uint32_t *)(pi->pi_cfgdata + offset));
307 }
308 
309 #endif /* _PCI_EMUL_H_ */
310