1 /*
2  * This file and its contents are supplied under the terms of the
3  * Common Development and Distribution License ("CDDL"), version 1.0.
4  * You may only use this file in accordance with the terms of version
5  * 1.0 of the CDDL.
6  *
7  * A full copy of the text of the CDDL should have accompanied this
8  * source. A copy of the CDDL is also available via the Internet at
9  * http://www.illumos.org/license/CDDL.
10  */
11 
12 /*
13  * This file is part of the Chelsio T4/T5/T6 Ethernet driver.
14  *
15  * Copyright (C) 2009-2019 Chelsio Communications.  All rights reserved.
16  *
17  * This program is distributed in the hope that it will be useful, but WITHOUT
18  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19  * FITNESS FOR A PARTICULAR PURPOSE.  See the LICENSE file included in this
20  * release for licensing terms and conditions.
21  */
22 
23 #ifndef __T4_HW_H
24 #define __T4_HW_H
25 
26 #include "osdep.h"
27 
28 enum {
29 	NCHAN           = 4,     /* # of HW channels */
30 	MAX_MTU         = 9600,  /* max MAC MTU, excluding header + FCS */
31 	EEPROMSIZE      = 17408, /* Serial EEPROM physical size */
32 	EEPROMVSIZE     = 32768, /* Serial EEPROM virtual address space size */
33 	EEPROMPFSIZE    = 1024,  /* EEPROM writable area size for PFn, n>0 */
34 	RSS_NENTRIES    = 2048,  /* # of entries in RSS mapping table */
35 	T6_RSS_NENTRIES = 4096,  /* # of entries in RSS mapping table */
36 	TCB_SIZE        = 128,   /* TCB size */
37 	NMTUS           = 16,    /* size of MTU table */
38 	NCCTRL_WIN      = 32,    /* # of congestion control windows */
39 	NTX_SCHED       = 8,     /* # of HW Tx scheduling queues */
40 	PM_NSTATS       = 5,     /* # of PM stats */
41 	T6_PM_NSTATS    = 7,     /* # of PM stats in T6 */
42 	MBOX_LEN        = 64,    /* mailbox size in bytes */
43 	TRACE_LEN       = 112,   /* length of trace data and mask */
44 	FILTER_OPT_LEN  = 36,    /* filter tuple width of optional components */
45 	UDBS_SEG_SIZE   = 128,   /* segment size for BAR2 user doorbells */
46 };
47 
48 enum {
49 	CIM_NUM_IBQ    = 6,     /* # of CIM IBQs */
50 	CIM_NUM_OBQ    = 6,     /* # of CIM OBQs */
51 	CIM_NUM_OBQ_T5 = 8,     /* # of CIM OBQs for T5 adapter */
52 	CIMLA_SIZE     = 2048,  /* # of 32-bit words in CIM LA */
53 	CIM_PIFLA_SIZE = 64,    /* # of 192-bit words in CIM PIF LA */
54 	CIM_MALA_SIZE  = 64,    /* # of 160-bit words in CIM MA LA */
55 	CIM_IBQ_SIZE   = 128,   /* # of 128-bit words in a CIM IBQ */
56 	CIM_OBQ_SIZE   = 128,   /* # of 128-bit words in a CIM OBQ */
57 	TPLA_SIZE      = 128,   /* # of 64-bit words in TP LA */
58 	ULPRX_LA_SIZE  = 512,   /* # of 256-bit words in ULP_RX LA */
59 };
60 
61 enum {
62 	SF_PAGE_SIZE = 256,           /* serial flash page size */
63 	SF_SEC_SIZE = 64 * 1024,      /* serial flash sector size */
64 };
65 
66 /* SGE context types */
67 enum ctxt_type { CTXT_EGRESS, CTXT_INGRESS, CTXT_FLM, CTXT_CNM };
68 
69 enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */
70 
71 enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV };    /* mailbox owners */
72 
73 enum {
74 	SGE_MAX_WR_LEN = 512,     /* max WR size in bytes */
75 	SGE_CTXT_SIZE = 24,       /* size of SGE context */
76 	SGE_NTIMERS = 6,          /* # of interrupt holdoff timer values */
77 	SGE_NCOUNTERS = 4,        /* # of interrupt packet counter values */
78 	SGE_NDBQTIMERS = 8,       /* # of Doorbell Queue Timer values */
79 	SGE_MAX_IQ_SIZE = 65520,
80 };
81 
82 /* PCI-e memory window access */
83 enum pcie_memwin {
84 	MEMWIN_NIC      = 0,
85 	MEMWIN_RSVD1    = 1,
86 	MEMWIN_RSVD2    = 2,
87 	MEMWIN_RDMA     = 3,
88 	MEMWIN_RSVD4    = 4,
89 	MEMWIN_FOISCSI  = 5,
90 	MEMWIN_CSIOSTOR = 6,
91 	MEMWIN_RSVD7    = 7,
92 };
93 
94 struct sge_qstat {                /* data written to SGE queue status entries */
95 	__be32 qid;
96 	__be16 cidx;
97 	__be16 pidx;
98 };
99 
100 #define S_QSTAT_PIDX    0
101 #define M_QSTAT_PIDX    0xffff
102 #define G_QSTAT_PIDX(x) (((x) >> S_QSTAT_PIDX) & M_QSTAT_PIDX)
103 
104 #define S_QSTAT_CIDX    16
105 #define M_QSTAT_CIDX    0xffff
106 #define G_QSTAT_CIDX(x) (((x) >> S_QSTAT_CIDX) & M_QSTAT_CIDX)
107 
108 /*
109  * Structure for last 128 bits of response descriptors
110  */
111 struct rsp_ctrl {
112 	__be32 hdrbuflen_pidx;
113 	__be32 pldbuflen_qid;
114 	union {
115 		u8 type_gen;
116 		__be64 last_flit;
117 	} u;
118 };
119 
120 #define S_RSPD_NEWBUF    31
121 #define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF)
122 #define F_RSPD_NEWBUF    V_RSPD_NEWBUF(1U)
123 
124 #define S_RSPD_LEN    0
125 #define M_RSPD_LEN    0x7fffffff
126 #define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
127 #define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)
128 
129 #define S_RSPD_QID    S_RSPD_LEN
130 #define M_RSPD_QID    M_RSPD_LEN
131 #define V_RSPD_QID(x) V_RSPD_LEN(x)
132 #define G_RSPD_QID(x) G_RSPD_LEN(x)
133 
134 #define S_RSPD_GEN    7
135 #define V_RSPD_GEN(x) ((x) << S_RSPD_GEN)
136 #define F_RSPD_GEN    V_RSPD_GEN(1U)
137 
138 #define S_RSPD_QOVFL    6
139 #define V_RSPD_QOVFL(x) ((x) << S_RSPD_QOVFL)
140 #define F_RSPD_QOVFL    V_RSPD_QOVFL(1U)
141 
142 #define S_RSPD_TYPE    4
143 #define M_RSPD_TYPE    0x3
144 #define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE)
145 #define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE)
146 
147 /* Rx queue interrupt deferral fields: counter enable and timer index */
148 #define S_QINTR_CNT_EN    0
149 #define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN)
150 #define F_QINTR_CNT_EN    V_QINTR_CNT_EN(1U)
151 
152 #define S_QINTR_TIMER_IDX    1
153 #define M_QINTR_TIMER_IDX    0x7
154 #define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX)
155 #define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX)
156 
157 /* # of pages a pagepod can hold without needing another pagepod */
158 #define PPOD_PAGES 4U
159 
160 struct pagepod {
161 	__be64 vld_tid_pgsz_tag_color;
162 	__be64 len_offset;
163 	__be64 rsvd;
164 	__be64 addr[PPOD_PAGES + 1];
165 };
166 
167 #define S_PPOD_COLOR    0
168 #define M_PPOD_COLOR    0x3F
169 #define V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR)
170 
171 #define S_PPOD_TAG    6
172 #define M_PPOD_TAG    0xFFFFFF
173 #define V_PPOD_TAG(x) ((x) << S_PPOD_TAG)
174 
175 #define S_PPOD_PGSZ    30
176 #define M_PPOD_PGSZ    0x3
177 #define V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ)
178 
179 #define S_PPOD_TID    32
180 #define M_PPOD_TID    0xFFFFFF
181 #define V_PPOD_TID(x) ((__u64)(x) << S_PPOD_TID)
182 
183 #define S_PPOD_VALID    56
184 #define V_PPOD_VALID(x) ((__u64)(x) << S_PPOD_VALID)
185 #define F_PPOD_VALID    V_PPOD_VALID(1ULL)
186 
187 #define S_PPOD_LEN    32
188 #define M_PPOD_LEN    0xFFFFFFFF
189 #define V_PPOD_LEN(x) ((__u64)(x) << S_PPOD_LEN)
190 
191 #define S_PPOD_OFST    0
192 #define M_PPOD_OFST    0xFFFFFFFF
193 #define V_PPOD_OFST(x) ((x) << S_PPOD_OFST)
194 
195 /*
196  * Flash layout.
197  */
198 #define FLASH_START(start)	((start) * SF_SEC_SIZE)
199 #define FLASH_MAX_SIZE(nsecs)	((nsecs) * SF_SEC_SIZE)
200 
201 enum {
202 	/*
203 	 * Various Expansion-ROM boot images, etc.
204 	 */
205 	FLASH_EXP_ROM_START_SEC = 0,
206 	FLASH_EXP_ROM_NSECS = 6,
207 	FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
208 	FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
209 
210 	/*
211 	 * iSCSI Boot Firmware Table (iBFT) and other driver-related
212 	 * parameters ...
213 	 */
214 	FLASH_IBFT_START_SEC = 6,
215 	FLASH_IBFT_NSECS = 1,
216 	FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),
217 	FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),
218 
219 	/*
220 	 * Boot configuration data.
221 	 */
222 	FLASH_BOOTCFG_START_SEC = 7,
223 	FLASH_BOOTCFG_NSECS = 1,
224 	FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),
225 	FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),
226 
227 	/*
228 	 * Location of firmware image in FLASH.
229 	 */
230 	FLASH_FW_START_SEC = 8,
231 	FLASH_FW_NSECS = 16,
232 	FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
233 	FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
234 
235 	/*
236 	 * Location of bootstrap firmware image in FLASH.
237 	 */
238 	FLASH_FWBOOTSTRAP_START_SEC = 27,
239 	FLASH_FWBOOTSTRAP_NSECS = 1,
240 	FLASH_FWBOOTSTRAP_START = FLASH_START(FLASH_FWBOOTSTRAP_START_SEC),
241 	FLASH_FWBOOTSTRAP_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FWBOOTSTRAP_NSECS),
242 
243 	/*
244 	 * iSCSI persistent/crash information.
245 	 */
246 	FLASH_ISCSI_CRASH_START_SEC = 29,
247 	FLASH_ISCSI_CRASH_NSECS = 1,
248 	FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),
249 	FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),
250 
251 	/*
252 	 * FCoE persistent/crash information.
253 	 */
254 	FLASH_FCOE_CRASH_START_SEC = 30,
255 	FLASH_FCOE_CRASH_NSECS = 1,
256 	FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
257 	FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
258 
259 	/*
260 	 * Location of Firmware Configuration File in FLASH.
261 	 */
262 	FLASH_CFG_START_SEC = 31,
263 	FLASH_CFG_NSECS = 1,
264 	FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
265 	FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
266 
267 	/*
268 	 * We don't support FLASH devices which can't support the full
269 	 * standard set of sections which we need for normal operations.
270 	 */
271 	FLASH_MIN_SIZE = FLASH_CFG_START + FLASH_CFG_MAX_SIZE,
272 
273 	/*
274 	 * Sectors 32-63 for CUDBG.
275 	 */
276 	FLASH_CUDBG_START_SEC = 32,
277 	FLASH_CUDBG_NSECS = 32,
278 	FLASH_CUDBG_START = FLASH_START(FLASH_CUDBG_START_SEC),
279 	FLASH_CUDBG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CUDBG_NSECS),
280 
281 	/*
282 	 * Size of defined FLASH regions.
283 	 */
284 	FLASH_END_SEC = 64,
285 };
286 
287 #undef FLASH_START
288 #undef FLASH_MAX_SIZE
289 
290 #define S_SGE_TIMESTAMP 0
291 #define M_SGE_TIMESTAMP 0xfffffffffffffffULL
292 #define V_SGE_TIMESTAMP(x) ((__u64)(x) << S_SGE_TIMESTAMP)
293 #define G_SGE_TIMESTAMP(x) (((__u64)(x) >> S_SGE_TIMESTAMP) & M_SGE_TIMESTAMP)
294 
295 #define I2C_DEV_ADDR_A0		0xa0
296 #define I2C_DEV_ADDR_A2		0xa2
297 #define I2C_PAGE_SIZE		0x100
298 #define SFP_DIAG_TYPE_ADDR	0x5c
299 #define SFP_DIAG_TYPE_LEN	0x1
300 #define SFF_8472_COMP_ADDR	0x5e
301 #define SFF_8472_COMP_LEN	0x1
302 #define SFF_REV_ADDR		0x1
303 #define SFF_REV_LEN		0x1
304 
305 #endif /* __T4_HW_H */
306