1 /*
2  * Copyright (c) 2015 Solarflare Communications Inc.
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions are met:
7  *
8  * 1. Redistributions of source code must retain the above copyright notice,
9  *    this list of conditions and the following disclaimer.
10  * 2. Redistributions in binary form must reproduce the above copyright notice,
11  *    this list of conditions and the following disclaimer in the documentation
12  *    and/or other materials provided with the distribution.
13  *
14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25  *
26  * The views and conclusions contained in the software and documentation are
27  * those of the authors and should not be interpreted as representing official
28  * policies, either expressed or implied, of the FreeBSD Project.
29  */
30 
31 #include "efx.h"
32 #include "efx_impl.h"
33 
34 
35 #if EFSYS_OPT_MEDFORD
36 
37 static	__checkReturn	efx_rc_t
efx_mcdi_get_rxdp_config(__in efx_nic_t * enp,__out uint32_t * end_paddingp)38 efx_mcdi_get_rxdp_config(
39 	__in		efx_nic_t *enp,
40 	__out		uint32_t *end_paddingp)
41 {
42 	efx_mcdi_req_t req;
43 	uint8_t payload[MAX(MC_CMD_GET_RXDP_CONFIG_IN_LEN,
44 			    MC_CMD_GET_RXDP_CONFIG_OUT_LEN)];
45 	uint32_t end_padding;
46 	efx_rc_t rc;
47 
48 	(void) memset(payload, 0, sizeof (payload));
49 	req.emr_cmd = MC_CMD_GET_RXDP_CONFIG;
50 	req.emr_in_buf = payload;
51 	req.emr_in_length = MC_CMD_GET_RXDP_CONFIG_IN_LEN;
52 	req.emr_out_buf = payload;
53 	req.emr_out_length = MC_CMD_GET_RXDP_CONFIG_OUT_LEN;
54 
55 	efx_mcdi_execute(enp, &req);
56 	if (req.emr_rc != 0) {
57 		rc = req.emr_rc;
58 		goto fail1;
59 	}
60 
61 	if (MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
62 				    GET_RXDP_CONFIG_OUT_PAD_HOST_DMA) == 0) {
63 		/* RX DMA end padding is disabled */
64 		end_padding = 0;
65 	} else {
66 		switch(MCDI_OUT_DWORD_FIELD(req, GET_RXDP_CONFIG_OUT_DATA,
67 					    GET_RXDP_CONFIG_OUT_PAD_HOST_LEN)) {
68 		case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_64:
69 			end_padding = 64;
70 			break;
71 		case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_128:
72 			end_padding = 128;
73 			break;
74 		case MC_CMD_SET_RXDP_CONFIG_IN_PAD_HOST_256:
75 			end_padding = 256;
76 			break;
77 		default:
78 			rc = ENOTSUP;
79 			goto fail2;
80 		}
81 	}
82 
83 	*end_paddingp = end_padding;
84 
85 	return (0);
86 
87 fail2:
88 	EFSYS_PROBE(fail2);
89 fail1:
90 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
91 
92 	return (rc);
93 }
94 
95 	__checkReturn	efx_rc_t
medford_board_cfg(__in efx_nic_t * enp)96 medford_board_cfg(
97 	__in		efx_nic_t *enp)
98 {
99 	efx_mcdi_iface_t *emip = &(enp->en_mcdi.em_emip);
100 	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
101 	uint8_t mac_addr[6] = { 0 };
102 	uint32_t board_type = 0;
103 	ef10_link_state_t els;
104 	efx_port_t *epp = &(enp->en_port);
105 	uint32_t port;
106 	uint32_t pf;
107 	uint32_t vf;
108 	uint32_t mask;
109 	uint32_t sysclk;
110 	uint32_t base, nvec;
111 	uint32_t end_padding;
112 	efx_rc_t rc;
113 
114 	/*
115 	 * FIXME: Likely to be incomplete and incorrect.
116 	 * Parts of this should be shared with Huntington.
117 	 */
118 
119 	if ((rc = efx_mcdi_get_port_assignment(enp, &port)) != 0)
120 		goto fail1;
121 
122 	/*
123 	 * NOTE: The MCDI protocol numbers ports from zero.
124 	 * The common code MCDI interface numbers ports from one.
125 	 */
126 	emip->emi_port = port + 1;
127 
128 	if ((rc = ef10_external_port_mapping(enp, port,
129 		    &encp->enc_external_port)) != 0)
130 		goto fail2;
131 
132 	/*
133 	 * Get PCIe function number from firmware (used for
134 	 * per-function privilege and dynamic config info).
135 	 *  - PCIe PF: pf = PF number, vf = 0xffff.
136 	 *  - PCIe VF: pf = parent PF, vf = VF number.
137 	 */
138 	if ((rc = efx_mcdi_get_function_info(enp, &pf, &vf)) != 0)
139 		goto fail3;
140 
141 	encp->enc_pf = pf;
142 	encp->enc_vf = vf;
143 
144 	/* MAC address for this function */
145 	if (EFX_PCI_FUNCTION_IS_PF(encp)) {
146 		rc = efx_mcdi_get_mac_address_pf(enp, mac_addr);
147 		if ((rc == 0) && (mac_addr[0] & 0x02)) {
148 			/*
149 			 * If the static config does not include a global MAC
150 			 * address pool then the board may return a locally
151 			 * administered MAC address (this should only happen on
152 			 * incorrectly programmed boards).
153 			 */
154 			rc = EINVAL;
155 		}
156 	} else {
157 		rc = efx_mcdi_get_mac_address_vf(enp, mac_addr);
158 	}
159 	if (rc != 0)
160 		goto fail4;
161 
162 	EFX_MAC_ADDR_COPY(encp->enc_mac_addr, mac_addr);
163 
164 	/* Board configuration */
165 	rc = efx_mcdi_get_board_cfg(enp, &board_type, NULL, NULL);
166 	if (rc != 0) {
167 		/* Unprivileged functions may not be able to read board cfg */
168 		if (rc == EACCES)
169 			board_type = 0;
170 		else
171 			goto fail5;
172 	}
173 
174 	encp->enc_board_type = board_type;
175 	encp->enc_clk_mult = 1; /* not used for Medford */
176 
177 	/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
178 	if ((rc = efx_mcdi_get_phy_cfg(enp)) != 0)
179 		goto fail6;
180 
181 	/* Obtain the default PHY advertised capabilities */
182 	if ((rc = ef10_phy_get_link(enp, &els)) != 0)
183 		goto fail7;
184 	epp->ep_default_adv_cap_mask = els.els_adv_cap_mask;
185 	epp->ep_adv_cap_mask = els.els_adv_cap_mask;
186 
187 	if (EFX_PCI_FUNCTION_IS_VF(encp)) {
188 		/*
189 		 * Interrupt testing does not work for VFs. See bug50084.
190 		 * FIXME: Does this still  apply to Medford?
191 		 */
192 		encp->enc_bug41750_workaround = B_TRUE;
193 	}
194 
195 	/* Chained multicast is always enabled on Medford */
196 	encp->enc_bug26807_workaround = B_TRUE;
197 
198 	/* Get sysclk frequency (in MHz). */
199 	if ((rc = efx_mcdi_get_clock(enp, &sysclk)) != 0)
200 		goto fail8;
201 
202 	/*
203 	 * The timer quantum is 1536 sysclk cycles, documented for the
204 	 * EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
205 	 */
206 	encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
207 	encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
208 		    FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
209 
210 	/* Check capabilities of running datapath firmware */
211 	if ((rc = ef10_get_datapath_caps(enp)) != 0)
212 	    goto fail9;
213 
214 	/* Alignment for receive packet DMA buffers */
215 	encp->enc_rx_buf_align_start = 1;
216 
217 	/* Get the RX DMA end padding alignment configuration */
218 	if ((rc = efx_mcdi_get_rxdp_config(enp, &end_padding)) != 0)
219 		goto fail10;
220 	encp->enc_rx_buf_align_end = end_padding;
221 
222 	/* Alignment for WPTR updates */
223 	encp->enc_rx_push_align = EF10_RX_WPTR_ALIGN;
224 
225 	/*
226 	 * Set resource limits for MC_CMD_ALLOC_VIS. Note that we cannot use
227 	 * MC_CMD_GET_RESOURCE_LIMITS here as that reports the available
228 	 * resources (allocated to this PCIe function), which is zero until
229 	 * after we have allocated VIs.
230 	 */
231 	encp->enc_evq_limit = 1024;
232 	encp->enc_rxq_limit = EFX_RXQ_LIMIT_TARGET;
233 	encp->enc_txq_limit = EFX_TXQ_LIMIT_TARGET;
234 
235 	encp->enc_buftbl_limit = 0xFFFFFFFF;
236 
237 	encp->enc_piobuf_limit = MEDFORD_PIOBUF_NBUFS;
238 	encp->enc_piobuf_size = MEDFORD_PIOBUF_SIZE;
239 	encp->enc_piobuf_min_alloc_size = MEDFORD_MIN_PIO_ALLOC_SIZE;
240 
241 	/*
242 	 * Get the current privilege mask. Note that this may be modified
243 	 * dynamically, so this value is informational only. DO NOT use
244 	 * the privilege mask to check for sufficient privileges, as that
245 	 * can result in time-of-check/time-of-use bugs.
246 	 */
247 	if ((rc = ef10_get_privilege_mask(enp, &mask)) != 0)
248 		goto fail11;
249 	encp->enc_privilege_mask = mask;
250 
251 	/* Get interrupt vector limits */
252 	if ((rc = efx_mcdi_get_vector_cfg(enp, &base, &nvec, NULL)) != 0) {
253 		if (EFX_PCI_FUNCTION_IS_PF(encp))
254 			goto fail12;
255 
256 		/* Ignore error (cannot query vector limits from a VF). */
257 		base = 0;
258 		nvec = 1024;
259 	}
260 	encp->enc_intr_vec_base = base;
261 	encp->enc_intr_limit = nvec;
262 
263 	/*
264 	 * Maximum number of bytes into the frame the TCP header can start for
265 	 * firmware assisted TSO to work.
266 	 */
267 	encp->enc_tx_tso_tcp_header_offset_limit = EF10_TCP_HEADER_OFFSET_LIMIT;
268 
269 	/*
270 	 * Medford stores a single global copy of VPD, not per-PF as on
271 	 * Huntington.
272 	 */
273 	encp->enc_vpd_is_global = B_TRUE;
274 
275 	return (0);
276 
277 fail12:
278 	EFSYS_PROBE(fail12);
279 fail11:
280 	EFSYS_PROBE(fail11);
281 fail10:
282 	EFSYS_PROBE(fail10);
283 fail9:
284 	EFSYS_PROBE(fail9);
285 fail8:
286 	EFSYS_PROBE(fail8);
287 fail7:
288 	EFSYS_PROBE(fail7);
289 fail6:
290 	EFSYS_PROBE(fail6);
291 fail5:
292 	EFSYS_PROBE(fail5);
293 fail4:
294 	EFSYS_PROBE(fail4);
295 fail3:
296 	EFSYS_PROBE(fail3);
297 fail2:
298 	EFSYS_PROBE(fail2);
299 fail1:
300 	EFSYS_PROBE1(fail1, efx_rc_t, rc);
301 
302 	return (rc);
303 }
304 
305 #endif	/* EFSYS_OPT_MEDFORD */
306