xref: /illumos-gate/usr/src/uts/i86pc/sys/apic.h (revision bd97c7ce)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
23  * Copyright 2018 Joyent, Inc.
24  * Copyright (c) 2017 by Delphix. All rights reserved.
25  */
26 /*
27  * Copyright (c) 2010, Intel Corporation.
28  * All rights reserved.
29  */
30 
31 #ifndef _SYS_APIC_APIC_H
32 #define	_SYS_APIC_APIC_H
33 
34 #include <sys/psm_types.h>
35 #include <sys/avintr.h>
36 #include <sys/pci.h>
37 
38 #ifdef	__cplusplus
39 extern "C" {
40 #endif
41 
42 #include <sys/psm_common.h>
43 
44 #define	APIC_PCPLUSMP_NAME	"pcplusmp"
45 #define	APIC_APIX_NAME		"apix"
46 
47 #define	APIC_IO_ADDR	0xfec00000
48 #define	APIC_LOCAL_ADDR	0xfee00000
49 #define	APIC_IO_MEMLEN	0xf
50 #define	APIC_LOCAL_MEMLEN	0xfffff
51 
52 /* Local Unit ID register */
53 #define	APIC_LID_REG		0x8
54 
55 /* I/o Unit Version Register */
56 #define	APIC_VERS_REG		0xc
57 
58 /* Task Priority register */
59 #define	APIC_TASK_REG		0x20
60 
61 /* EOI register */
62 #define	APIC_EOI_REG		0x2c
63 
64 /* Remote Read register		*/
65 #define	APIC_REMOTE_READ	0x30
66 
67 /* Logical Destination register */
68 #define	APIC_DEST_REG		0x34
69 
70 /* Destination Format register */
71 #define	APIC_FORMAT_REG		0x38
72 
73 /* Spurious Interrupt Vector register */
74 #define	APIC_SPUR_INT_REG	0x3c
75 
76 /* Error Status Register */
77 #define	APIC_ERROR_STATUS	0xa0
78 
79 /* Interrupt Command registers */
80 #define	APIC_INT_CMD1		0xc0
81 #define	APIC_INT_CMD2		0xc4
82 
83 /* Local Interrupt Vector registers */
84 #define	APIC_CMCI_VECT		0xbc
85 #define	APIC_THERM_VECT		0xcc
86 #define	APIC_PCINT_VECT		0xd0
87 #define	APIC_INT_VECT0		0xd4
88 #define	APIC_INT_VECT1		0xd8
89 #define	APIC_ERR_VECT		0xdc
90 
91 /* IPL for performance counter interrupts */
92 #define	APIC_PCINT_IPL		0xe
93 #define	APIC_LVT_MASK		0x10000		/* Mask bit (16) in LVT */
94 
95 /* Initial Count register */
96 #define	APIC_INIT_COUNT		0xe0
97 
98 /* Current Count Register */
99 #define	APIC_CURR_COUNT		0xe4
100 #define	APIC_CURR_ADD		0x39	/* used for remote read command */
101 #define	CURR_COUNT_OFFSET	(sizeof (int32_t) * APIC_CURR_COUNT)
102 
103 /* Divider Configuration Register */
104 #define	APIC_DIVIDE_REG		0xf8
105 
106 /* Various mode for local APIC. Modes are mutually exclusive  */
107 typedef enum apic_mode {
108 	APIC_IS_DISABLED = 0,
109 	APIC_MODE_NOTSET,
110 	LOCAL_APIC,
111 	LOCAL_X2APIC
112 } apic_mode_t;
113 
114 /* x2APIC SELF IPI Register */
115 #define	X2APIC_SELF_IPI		0xFC
116 
117 /* General x2APIC constants used at various places */
118 #define	APIC_SVR_SUPPRESS_BROADCAST_EOI		0x1000
119 #define	APIC_DIRECTED_EOI_BIT			0x1000000
120 
121 /* x2APIC enable bit in REG_APIC_BASE_MSR */
122 #define	X2APIC_ENABLE_BIT	10
123 
124 /* IRR register	*/
125 #define	APIC_IRR_REG		0x80
126 
127 /* ISR register	*/
128 #define	APIC_ISR_REG		0x40
129 
130 #define	APIC_IO_REG		0x0
131 #define	APIC_IO_DATA		0x4
132 #define	APIC_IO_EOI		0x10
133 
134 /* Bit offset of APIC ID in LID_REG, INT_CMD and in DEST_REG */
135 #define	APIC_ID_BIT_OFFSET	24
136 #define	APIC_ICR_ID_BIT_OFFSET	24
137 #define	APIC_LDR_ID_BIT_OFFSET	24
138 
139 /*
140  * Choose between flat and clustered models by writing the following to the
141  * FORMAT_REG. 82489 DX documentation seemed to suggest that writing 0 will
142  * disable logical destination mode.
143  * Does not seem to be in the docs for local APICs on the processors.
144  */
145 #define	APIC_FLAT_MODEL		0xFFFFFFFFUL
146 #define	APIC_CLUSTER_MODEL	0x0FFFFFFF
147 
148 /*
149  * The commands which follow are window selectors written to APIC_IO_REG
150  * before data can be read/written from/to APIC_IO_DATA
151  */
152 
153 #define	APIC_ID_CMD		0x0
154 #define	APIC_VERS_CMD		0x1
155 #define	APIC_RDT_CMD		0x10
156 #define	APIC_RDT_CMD2		0x11
157 
158 #define	APIC_INTEGRATED_VERS	0x10	/* 0x10 & above indicates integrated */
159 #define	IOAPIC_VER_82489DX	0x01	/* Version ID: 82489DX External APIC */
160 
161 #define	APIC_INT_SPURIOUS	-1
162 
163 #define	APIC_IMCR_P1	0x22		/* int mode conf register port 1 */
164 #define	APIC_IMCR_P2	0x23		/* int mode conf register port 2 */
165 #define	APIC_IMCR_SELECT 0x70		/* select imcr by writing into P1 */
166 #define	APIC_IMCR_PIC	0x0		/* selects PIC mode (8259-> BSP) */
167 #define	APIC_IMCR_APIC	0x1		/* selects APIC mode (8259->APIC) */
168 
169 #define	APIC_CT_VECT	0x4ac		/* conf table vector		*/
170 #define	APIC_CT_SIZE	1024		/* conf table size		*/
171 
172 #define	APIC_ID		'MPAT'		/* conf table signature		*/
173 
174 #define	VENID_AMD		0x1022
175 #define	DEVID_8131_IOAPIC	0x7451
176 #define	DEVID_8132_IOAPIC	0x7459
177 
178 #define	IOAPICS_NODE_NAME	"ioapics"
179 #define	IOAPICS_CHILD_NAME	"ioapic"
180 #define	IOAPICS_DEV_TYPE	"ioapic"
181 #define	IOAPICS_PROP_VENID	"vendor-id"
182 #define	IOAPICS_PROP_DEVID	"device-id"
183 
184 /*
185  * These macros are used in frequently called routines like
186  * apic_intr_enter().
187  */
188 #define	X2APIC_WRITE(reg, v) \
189 	wrmsr((REG_X2APIC_BASE_MSR + (reg >> 2)), v)
190 
191 #define	LOCAL_APIC_WRITE_REG(reg, v) \
192 	apicadr[reg] = v
193 
194 /*
195  * MP floating pointer structure defined in Intel MP Spec 1.1
196  */
197 struct apic_mpfps_hdr {
198 	uint32_t	mpfps_sig;	/* _MP_ (0x5F4D505F)		*/
199 	uint32_t	mpfps_mpct_paddr; /* paddr of MP configuration tbl */
200 	uchar_t	mpfps_length;		/* in paragraph (16-bytes units) */
201 	uchar_t	mpfps_spec_rev;		/* version number of MP spec	 */
202 	uchar_t	mpfps_checksum;		/* checksum of complete structure */
203 	uchar_t	mpfps_featinfo1;	/* mp feature info bytes 1	 */
204 	uchar_t	mpfps_featinfo2;	/* mp feature info bytes 2	 */
205 	uchar_t	mpfps_featinfo3;	/* mp feature info bytes 3	 */
206 	uchar_t	mpfps_featinfo4;	/* mp feature info bytes 4	 */
207 	uchar_t	mpfps_featinfo5;	/* mp feature info bytes 5	 */
208 };
209 
210 #define	MPFPS_FEATINFO2_IMCRP		0x80	/* IMCRP presence bit	*/
211 
212 #define	APIC_MPS_OEM_ID_LEN		8
213 #define	APIC_MPS_PROD_ID_LEN		12
214 
215 struct apic_mp_cnf_hdr {
216 	uint_t	mpcnf_sig;
217 
218 	uint_t	mpcnf_tbl_length:	16,
219 		mpcnf_spec:		8,
220 		mpcnf_cksum:		8;
221 
222 	char	mpcnf_oem_str[APIC_MPS_OEM_ID_LEN];
223 
224 	char	mpcnf_prod_str[APIC_MPS_PROD_ID_LEN];
225 
226 	uint_t	mpcnf_oem_ptr;
227 
228 	uint_t	mpcnf_oem_tbl_size:	16,
229 		mpcnf_entry_cnt:	16;
230 
231 	uint_t	mpcnf_local_apic;
232 
233 	uint_t	mpcnf_resv;
234 };
235 
236 struct apic_procent {
237 	uint_t	proc_entry:		8,
238 		proc_apicid:		8,
239 		proc_version:		8,
240 		proc_cpuflags:		8;
241 
242 	uint_t	proc_stepping:		4,
243 		proc_model:		4,
244 		proc_family:		4,
245 		proc_type:		2,	/* undocumented feature */
246 		proc_resv1:		18;
247 
248 	uint_t	proc_feature;
249 
250 	uint_t	proc_resv2;
251 
252 	uint_t	proc_resv3;
253 };
254 
255 /*
256  * proc_cpuflags definitions
257  */
258 #define	CPUFLAGS_EN	1	/* if not set, this processor is unusable */
259 #define	CPUFLAGS_BP	2	/* set if this is the bootstrap processor */
260 
261 
262 struct apic_bus {
263 	uchar_t	bus_entry;
264 	uchar_t	bus_id;
265 	ushort_t	bus_str1;
266 	uint_t	bus_str2;
267 };
268 
269 struct apic_io_entry {
270 	uint_t	io_entry:		8,
271 		io_apicid:		8,
272 		io_version:		8,
273 		io_flags:		8;
274 
275 	uint_t	io_apic_addr;
276 };
277 
278 #define	IOAPIC_FLAGS_EN		0x01	/* this I/O apic is enable or not */
279 
280 #define	MAX_IO_APIC		32	/* maximum # of IOAPICs supported */
281 
282 struct apic_io_intr {
283 	uint_t	intr_entry:		8,
284 		intr_type:		8,
285 		intr_po:		2,
286 		intr_el:		2,
287 		intr_resv:		12;
288 
289 	uint_t	intr_busid:		8,
290 		intr_irq:		8,
291 		intr_destid:		8,
292 		intr_destintin:		8;
293 };
294 
295 /*
296  * intr_type definitions
297  */
298 #define	IO_INTR_INT	0x00
299 #define	IO_INTR_NMI	0x01
300 #define	IO_INTR_SMI	0x02
301 #define	IO_INTR_EXTINT	0x03
302 
303 /*
304  * destination APIC ID
305  */
306 #define	INTR_ALL_APIC		0xff
307 
308 
309 /* local vector table							*/
310 #define	AV_MASK		0x10000
311 
312 /* interrupt command register 32-63					*/
313 #define	AV_TOALL	0x7fffffff
314 #define	AV_HIGH_ORDER	0x40000000
315 #define	AV_IM_OFF	0x40000000
316 
317 /* interrupt command register 0-31					*/
318 #define	AV_DELIV_MODE	0x700
319 
320 #define	AV_FIXED	0x000
321 #define	AV_LOPRI	0x100
322 #define	AV_SMI		0x200
323 #define	AV_REMOTE	0x300
324 #define	AV_NMI		0x400
325 #define	AV_RESET	0x500
326 #define	AV_STARTUP	0x600
327 #define	AV_EXTINT	0x700
328 
329 #define	AV_PDEST	0x000
330 #define	AV_LDEST	0x800
331 
332 /* IO & Local APIC Bit Definitions */
333 #define	RDT_VECTOR(x)	((uchar_t)((x) & 0xFF))
334 #define	AV_PENDING	0x1000
335 #define	AV_ACTIVE_LOW	0x2000		/* only for integrated APIC */
336 #define	AV_REMOTE_IRR   0x4000		/* IOAPIC RDT-specific */
337 #define	AV_LEVEL	0x8000
338 #define	AV_DEASSERT	AV_LEVEL
339 #define	AV_ASSERT	0xc000
340 
341 #define	AV_READ_PENDING	0x10000
342 #define	AV_REMOTE_STATUS	0x20000	/* 1 = valid, 0 = invalid */
343 
344 #define	AV_SH_SELF		0x40000	/* Short hand for self */
345 #define	AV_SH_ALL_INCSELF	0x80000 /* All processors */
346 #define	AV_SH_ALL_EXCSELF	0xc0000 /* All excluding self */
347 /* spurious interrupt vector register					*/
348 #define	AV_UNIT_ENABLE	0x100
349 
350 #define	APIC_MAXVAL	0xffffffffUL
351 #define	APIC_TIME_MIN	0x5000
352 #define	APIC_TIME_COUNT	0x4000
353 
354 /*
355  * Range of the low byte value in apic_tick before starting calibration
356  */
357 #define	APIC_LB_MIN	0x60
358 #define	APIC_LB_MAX	0xe0
359 
360 #define	APIC_MAX_VECTOR		255
361 #define	APIC_RESV_VECT		0x00
362 #define	APIC_RESV_IRQ		0xfe
363 #define	APIC_BASE_VECT		0x20	/* This will come in as interrupt 0 */
364 #define	APIC_AVAIL_VECTOR	(APIC_MAX_VECTOR+1-APIC_BASE_VECT)
365 #define	APIC_VECTOR_PER_IPL	0x10	/* # of vectors before PRI changes */
366 #define	APIC_VECTOR(ipl)	(apic_ipltopri[ipl] | APIC_RESV_VECT)
367 #define	APIC_VECTOR_MASK	0x0f
368 #define	APIC_HI_PRI_VECTS	2	/* vects reserved for hi pri reqs */
369 #define	APIC_IPL_MASK		0xf0
370 #define	APIC_IPL_SHIFT		4	/* >> to get ipl part of vector */
371 #define	APIC_FIRST_FREE_IRQ	0x10
372 #define	APIC_MAX_ISA_IRQ	15
373 #define	APIC_IPL0		0x0f	/* let IDLE_IPL be the lowest */
374 #define	APIC_IDLE_IPL		0x00
375 
376 #define	APIC_MASK_ALL		0xf0	/* Mask all interrupts */
377 
378 /* spurious interrupt vector						*/
379 #define	APIC_SPUR_INTR		0xFF
380 
381 /* special or reserve vectors */
382 #define	APIC_CHECK_RESERVE_VECTORS(v) \
383 	(((v) == T_FASTTRAP) || ((v) == APIC_SPUR_INTR) || \
384 	((v) == T_SYSCALLINT) || ((v) == T_DTRACE_RET))
385 
386 /* cmos shutdown code for BIOS						*/
387 #define	BIOS_SHUTDOWN		0x0a
388 
389 /* define the entry types for BIOS information tables as defined in PC+MP */
390 #define	APIC_CPU_ENTRY		0
391 #define	APIC_BUS_ENTRY		1
392 #define	APIC_IO_ENTRY		2
393 #define	APIC_IO_INTR_ENTRY	3
394 #define	APIC_LOCAL_INTR_ENTRY	4
395 #define	APIC_MPTBL_ADDR		(639 * 1024)
396 /*
397  * The MP Floating Point structure could be in 1st 1KB of EBDA or last KB
398  * of system base memory or in ROM between 0xF0000 and 0xFFFFF
399  */
400 #define	MPFPS_RAM_WIN_LEN	1024
401 #define	MPFPS_ROM_WIN_START	(uint32_t)0xf0000
402 #define	MPFPS_ROM_WIN_LEN	0x10000
403 
404 #define	EISA_LEVEL_CNTL		0x4D0
405 
406 /* definitions for apic_irq_table */
407 #define	FREE_INDEX		(short)-1	/* empty slot */
408 #define	RESERVE_INDEX		(short)-2	/* ipi, softintr, clkintr */
409 #define	ACPI_INDEX		(short)-3	/* ACPI */
410 #define	MSI_INDEX		(short)-4	/* MSI */
411 #define	MSIX_INDEX		(short)-5	/* MSI-X */
412 #define	DEFAULT_INDEX		(short)0x7FFF
413 	/* biggest positive no. to avoid conflict with actual index */
414 
415 #define	APIC_IS_MSI_OR_MSIX_INDEX(index) \
416 	((index) == MSI_INDEX || (index) == MSIX_INDEX)
417 
418 /*
419  * definitions for MSI Address
420  */
421 #define	MSI_ADDR_HDR		APIC_LOCAL_ADDR
422 #define	MSI_ADDR_DEST_SHIFT	12	/* Destination CPU's apic id */
423 #define	MSI_ADDR_RH_FIXED	0x0	/* Redirection Hint Fixed */
424 #define	MSI_ADDR_RH_LOPRI	0x1	/* Redirection Hint Lowest priority */
425 #define	MSI_ADDR_RH_SHIFT	3
426 #define	MSI_ADDR_DM_PHYSICAL	0x0	/* Physical Destination Mode */
427 #define	MSI_ADDR_DM_LOGICAL	0x1	/* Logical Destination Mode */
428 #define	MSI_ADDR_DM_SHIFT	2
429 
430 /*
431  * TM is either edge or level.
432  */
433 #define	TRIGGER_MODE_EDGE		0x0	/* edge sensitive */
434 #define	TRIGGER_MODE_LEVEL		0x1	/* level sensitive */
435 
436 /*
437  * definitions for MSI Data
438  */
439 #define	MSI_DATA_DELIVERY_FIXED		0x0	/* Fixed delivery */
440 #define	MSI_DATA_DELIVERY_LOPRI		0x1	/* Lowest priority delivery */
441 #define	MSI_DATA_DELIVERY_SMI		0x2
442 #define	MSI_DATA_DELIVERY_NMI		0x4
443 #define	MSI_DATA_DELIVERY_INIT		0x5
444 #define	MSI_DATA_DELIVERY_EXTINT	0x7
445 #define	MSI_DATA_DELIVERY_SHIFT		8
446 #define	MSI_DATA_TM_EDGE		TRIGGER_MODE_EDGE
447 #define	MSI_DATA_TM_LEVEL		TRIGGER_MODE_LEVEL
448 #define	MSI_DATA_TM_SHIFT		15
449 #define	MSI_DATA_LEVEL_DEASSERT		0x0
450 #define	MSI_DATA_LEVEL_ASSERT		0x1	/* Edge always assert */
451 #define	MSI_DATA_LEVEL_SHIFT		14
452 
453 /*
454  * use to define each irq setup by the apic
455  */
456 typedef struct	apic_irq {
457 	short	airq_mps_intr_index;	/* index into mps interrupt entries */
458 					/*  table */
459 	uchar_t	airq_intin_no;
460 	uchar_t	airq_ioapicindex;
461 	dev_info_t	*airq_dip; /* device corresponding to this interrupt */
462 	/*
463 	 * IRQ could be shared (in H/W) in which case dip & major will be
464 	 * for the one that was last added at this level. We cannot keep a
465 	 * linked list as delspl does not tell us which device has just
466 	 * been unloaded. For most servers where we are worried about
467 	 * performance, interrupt should not be shared & should not be
468 	 * a problem. This does not cause any correctness issue - dip is
469 	 * used only as an optimisation to avoid going thru all the tables
470 	 * in translate IRQ (which is always called twice due to brokenness
471 	 * in the way IPLs are determined for devices). major is used only
472 	 * to bind interrupts corresponding to the same device on the same
473 	 * CPU. Not finding major will just cause it to be potentially bound
474 	 * to another CPU.
475 	 */
476 	major_t	airq_major;	/* major number corresponding to the device */
477 	ushort_t airq_rdt_entry;	/* level, polarity & trig mode */
478 	uint32_t airq_cpu;		/* target CPU, non-reserved IRQ only */
479 	uint32_t airq_temp_cpu;   /* non-reserved IRQ only, for disable_intr */
480 	uchar_t	airq_vector;		/* Vector chosen for this irq */
481 	uchar_t	airq_share;		/* number of interrupts at this irq */
482 	uchar_t	airq_share_id;		/* id to identify source from irqno */
483 	uchar_t	airq_ipl;		/* The ipl at which this is handled */
484 	iflag_t airq_iflag;		/* interrupt flag */
485 	uchar_t	airq_origirq;		/* original irq passed in */
486 	uint_t	airq_busy;		/* How frequently did clock find */
487 					/* us in this */
488 	struct apic_irq *airq_next;	/* chain of intpts sharing a vector */
489 	void		*airq_intrmap_private; /* intr remap private data */
490 } apic_irq_t;
491 
492 #define	IRQ_USER_BOUND	0x80000000 /* user requested bind if set in airq_cpu */
493 #define	IRQ_UNBOUND	(uint32_t)-1	/* set in airq_cpu and airq_temp_cpu */
494 #define	IRQ_UNINIT	(uint32_t)-2 /* in airq_temp_cpu till addspl called */
495 
496 /* Macros to help deal with shared interrupts */
497 #define	VIRTIRQ(irqno, share_id)	((irqno) | ((share_id) << 8))
498 #define	IRQINDEX(irq)	((irq) & 0xFF)	/* Mask to get irq from virtual irq */
499 
500 /*
501  * We align apic_cpus_info at 64-byte cache line boundary. Please make sure we
502  * adjust APIC_PADSZ as we add/modify any member of apic_cpus_info. We also
503  * don't want the compiler to optimize apic_cpus_info.
504  */
505 #define	APIC_PADSZ	15
506 
507 #pragma	pack(1)
508 typedef struct apic_cpus_info {
509 	uint32_t aci_local_id;
510 	uchar_t	aci_local_ver;
511 	uchar_t	aci_status;
512 	uchar_t	aci_redistribute;	/* Selected for redistribution */
513 	uint_t	aci_busy;		/* Number of ticks we were in ISR */
514 	uint_t	aci_spur_cnt;		/* # of spurious intpts on this cpu */
515 	uint_t	aci_ISR_in_progress;	/* big enough to hold 1 << MAXIPL */
516 	uchar_t	aci_curipl;		/* IPL of current ISR */
517 	uchar_t	aci_current[MAXIPL];	/* Current IRQ at each IPL */
518 	uint32_t aci_bound;		/* # of user requested binds ? */
519 	uint32_t aci_temp_bound;	/* # of non user IRQ binds */
520 	uint32_t aci_processor_id;	/* Only used in ACPI mode. */
521 	uchar_t	aci_idle;		/* The CPU is idle */
522 	/*
523 	 * Fill to make sure each struct is in separate 64-byte cache line.
524 	 */
525 	uchar_t	aci_pad[APIC_PADSZ];	/* padding for 64-byte cache line */
526 } apic_cpus_info_t;
527 #pragma	pack()
528 
529 #define	APIC_CPU_ONLINE		0x1
530 #define	APIC_CPU_INTR_ENABLE	0x2
531 #define	APIC_CPU_FREE		0x4	/* APIC CPU slot is free */
532 #define	APIC_CPU_DIRTY		0x8	/* Slot was once used */
533 #define	APIC_CPU_SUSPEND	0x10
534 
535 /*
536  * APIC ops to support various flavors of APIC like APIC and x2APIC.
537  */
538 typedef	struct apic_regs_ops {
539 	uint64_t	(*apic_read)(uint32_t);
540 	void		(*apic_write)(uint32_t, uint64_t);
541 	int		(*apic_get_pri)(void);
542 	void		(*apic_write_task_reg)(uint64_t);
543 	void		(*apic_write_int_cmd)(uint32_t, uint32_t);
544 	void		(*apic_send_eoi)(uint32_t);
545 } apic_reg_ops_t;
546 
547 /*
548  * interrupt structure for ioapic and msi
549  */
550 typedef struct ioapic_rdt {
551 	uint32_t	ir_lo;
552 	uint32_t	ir_hi;
553 } ioapic_rdt_t;
554 
555 typedef struct msi_regs {
556 	uint32_t	mr_data;
557 	uint64_t	mr_addr;
558 }msi_regs_t;
559 
560 /*
561  * APIC ops to support intel interrupt remapping
562  */
563 typedef struct apic_intrmap_ops {
564 	int	(*apic_intrmap_init)(int);
565 	void	(*apic_intrmap_enable)(int);
566 	void	(*apic_intrmap_alloc_entry)(void **, dev_info_t *, uint16_t,
567 		    int, uchar_t);
568 	void	(*apic_intrmap_map_entry)(void *, void *, uint16_t, int);
569 	void	(*apic_intrmap_free_entry)(void **);
570 	void	(*apic_intrmap_record_rdt)(void *, ioapic_rdt_t *);
571 	void	(*apic_intrmap_record_msi)(void *, msi_regs_t *);
572 } apic_intrmap_ops_t;
573 
574 /*
575  * Various poweroff methods and ports & bits for them
576  */
577 #define	APIC_POWEROFF_NONE		0
578 #define	APIC_POWEROFF_VIA_RTC		1
579 #define	APIC_POWEROFF_VIA_ASPEN_BMC	2
580 #define	APIC_POWEROFF_VIA_SITKA_BMC	3
581 
582 /* For RTC */
583 #define	RTC_REGA		0x0a
584 #define	PFR_REG			0x4a    /* extended control register */
585 #define	PAB_CBIT		0x08
586 #define	WF_FLAG			0x02
587 #define	KS_FLAG			0x01
588 #define	EXT_BANK		0x10
589 
590 /* For Aspen/Drake BMC */
591 
592 #define	CC_SMS_GET_STATUS	0x40
593 #define	CC_SMS_WR_START		0x41
594 #define	CC_SMS_WR_NEXT		0x42
595 #define	CC_SMS_WR_END		0x43
596 
597 #define	MISMIC_DATA_REGISTER	0x0ca9
598 #define	MISMIC_CNTL_REGISTER	0x0caa
599 #define	MISMIC_FLAG_REGISTER	0x0cab
600 
601 #define	MISMIC_BUSY_MASK	0x01
602 
603 /* For Sitka/Cabrillo BMC */
604 
605 #define	SMS_GET_STATUS		0x60
606 #define	SMS_WRITE_START		0x61
607 #define	SMS_WRITE_END		0x62
608 
609 #define	SMS_DATA_REGISTER	0x0ca2
610 #define	SMS_STATUS_REGISTER	0x0ca3
611 #define	SMS_COMMAND_REGISTER	0x0ca3
612 
613 #define	SMS_IBF_MASK		0x02
614 #define	SMS_STATE_MASK		0xc0
615 
616 #define	SMS_IDLE_STATE		0x00
617 #define	SMS_READ_STATE		0x40
618 #define	SMS_WRITE_STATE		0x80
619 #define	SMS_ERROR_STATE		0xc0
620 
621 extern uint32_t ioapic_read(int ioapic_ix, uint32_t reg);
622 extern void ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value);
623 extern void ioapic_write_eoi(int ioapic_ix, uint32_t value);
624 
625 /* Macros for reading/writing the IOAPIC RDT entries */
626 #define	READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin) \
627 	ioapic_read(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)))
628 
629 #define	READ_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin) \
630 	ioapic_read(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)))
631 
632 #define	WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin, value) \
633 	ioapic_write(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)), value)
634 
635 #define	WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin, value) \
636 	ioapic_write(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)), value)
637 
638 /* Used by PSM_INTR_OP_GET_INTR to return device information. */
639 typedef struct {
640 	uint16_t	avgi_req_flags;	/* request flags - to kernel */
641 	uint8_t		avgi_num_devs;	/* # devs on this ino - from kernel */
642 	uint8_t		avgi_vector;	/* vector */
643 	uint32_t	avgi_cpu_id;	/* cpu of interrupt - from kernel */
644 	dev_info_t	**avgi_dip_list; /* kmem_alloc'ed list of dev_infos. */
645 					/* Contains num_devs elements. */
646 } apic_get_intr_t;
647 
648 /* Used by PSM_INTR_OP_GET_TYPE to return platform information. */
649 typedef struct {
650 	char		*avgi_type;	/*  platform type - from kernel */
651 	uint32_t	avgi_num_intr;	/*  max intr number - from kernel */
652 	uint32_t	avgi_num_cpu;	/*  max cpu number - from kernel */
653 } apic_get_type_t;
654 
655 /* Masks for avgi_req_flags. */
656 #define	PSMGI_REQ_CPUID		0x1	/* Request CPU ID */
657 #define	PSMGI_REQ_NUM_DEVS	0x2	/* Request num of devices on vector */
658 #define	PSMGI_REQ_VECTOR	0x4
659 #define	PSMGI_REQ_GET_DEVS	0x8	/* Request device list */
660 #define	PSMGI_REQ_ALL		0xf	/* Request everything */
661 
662 /* Other flags */
663 #define	PSMGI_INTRBY_VEC	0	/* Vec passed.  xlate to IRQ needed */
664 #define	PSMGI_INTRBY_IRQ	0x8000	/* IRQ passed.  no xlate needed */
665 #define	PSMGI_INTRBY_DEFAULT	0x4000	/* PSM specific default value */
666 #define	PSMGI_INTRBY_FLAGS	0xc000	/* Mask for this flag */
667 
668 extern int	apic_verbose;
669 
670 /* Flag definitions for apic_verbose */
671 #define	APIC_VERBOSE_IOAPIC_FLAG		0x00000001
672 #define	APIC_VERBOSE_IRQ_FLAG			0x00000002
673 #define	APIC_VERBOSE_POWEROFF_FLAG		0x00000004
674 #define	APIC_VERBOSE_POWEROFF_PAUSE_FLAG	0x00000008
675 #define	APIC_VERBOSE_INIT			0x00000010
676 #define	APIC_VERBOSE_REBIND			0x00000020
677 #define	APIC_VERBOSE_ALLOC			0x00000040
678 #define	APIC_VERBOSE_IPI			0x00000080
679 #define	APIC_VERBOSE_INTR			0x00000100
680 
681 /* required test to wait until APIC command is sent on the bus */
682 #define	APIC_AV_PENDING_SET() \
683 	while (apic_reg_ops->apic_read(APIC_INT_CMD1) & AV_PENDING) \
684 		apic_ret();
685 
686 #ifdef	DEBUG
687 
688 #define	DENT		0x0001
689 extern int	apic_debug;
690 /*
691  * set apic_restrict_vector to the # of vectors we want to allow per range
692  * useful in testing shared interrupt logic by setting it to 2 or 3
693  */
694 extern int	apic_restrict_vector;
695 
696 #define	APIC_DEBUG_MSGBUFSIZE	2048
697 extern int	apic_debug_msgbuf[];
698 extern int	apic_debug_msgbufindex;
699 
700 /*
701  * Put "int" info into debug buffer. No MP consistency, but light weight.
702  * Good enough for most debugging.
703  */
704 #define	APIC_DEBUG_BUF_PUT(x) \
705 	apic_debug_msgbuf[apic_debug_msgbufindex++] = x; \
706 	if (apic_debug_msgbufindex >= (APIC_DEBUG_MSGBUFSIZE - NCPU)) \
707 		apic_debug_msgbufindex = 0;
708 
709 #define	APIC_VERBOSE(flag, fmt)			     \
710 	if (apic_verbose & APIC_VERBOSE_##flag) \
711 		cmn_err fmt;
712 
713 #define	APIC_VERBOSE_POWEROFF(fmt) \
714 	if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) \
715 		prom_printf fmt;
716 
717 #else	/* DEBUG */
718 
719 #define	APIC_VERBOSE(flag, fmt)
720 #define	APIC_VERBOSE_POWEROFF(fmt)
721 
722 #endif	/* DEBUG */
723 
724 #define	APIC_VERBOSE_IOAPIC(fmt)	APIC_VERBOSE(IOAPIC_FLAG, fmt)
725 #define	APIC_VERBOSE_IRQ(fmt)		APIC_VERBOSE(IRQ_FLAG, fmt)
726 
727 extern int	apic_error;
728 /* values which apic_error can take. Not catastrophic, but may help debug */
729 #define	APIC_ERR_BOOT_EOI		0x1
730 #define	APIC_ERR_GET_IPIVECT_FAIL	0x2
731 #define	APIC_ERR_INVALID_INDEX		0x4
732 #define	APIC_ERR_MARK_VECTOR_FAIL	0x8
733 #define	APIC_ERR_APIC_ERROR		0x40000000
734 #define	APIC_ERR_NMI			0x80000000
735 
736 /*
737  * ACPI definitions
738  */
739 /* _PIC method arguments */
740 #define	ACPI_PIC_MODE	0
741 #define	ACPI_APIC_MODE	1
742 
743 /* APIC error flags we care about */
744 #define	APIC_SEND_CS_ERROR	0x01
745 #define	APIC_RECV_CS_ERROR	0x02
746 #define	APIC_CS_ERRORS		(APIC_SEND_CS_ERROR|APIC_RECV_CS_ERROR)
747 
748 /* Maximum number of times to retry reprogramming at apic_intr_exit time */
749 #define	APIC_REPROGRAM_MAX_TRIES 10000
750 
751 /* Parameter to ioapic_init_intr(): Should ioapic ints be masked? */
752 #define	IOAPIC_MASK 1
753 #define	IOAPIC_NOMASK 0
754 
755 #define	INTR_ROUND_ROBIN_WITH_AFFINITY	0
756 #define	INTR_ROUND_ROBIN		1
757 #define	INTR_LOWEST_PRIORITY		2
758 
759 struct ioapic_reprogram_data {
760 	boolean_t			done;
761 	apic_irq_t			*irqp;
762 	/* The CPU to which the int will be bound */
763 	int				bindcpu;
764 	/* # times the reprogram timeout was called */
765 	unsigned			tries;
766 };
767 
768 /* The irq # is implicit in the array index: */
769 extern struct ioapic_reprogram_data apic_reprogram_info[];
770 
771 extern void apic_intr_exit(int ipl, int irq);
772 extern void x2apic_intr_exit(int ipl, int irq);
773 extern int apic_probe_common();
774 extern void apic_init_common();
775 extern void ioapic_init_intr();
776 extern void ioapic_disable_redirection();
777 extern int apic_addspl_common(int irqno, int ipl, int min_ipl, int max_ipl);
778 extern int apic_delspl_common(int irqno, int ipl, int min_ipl, int max_ipl);
779 extern void apic_cleanup_busy();
780 extern void apic_intr_redistribute();
781 extern uchar_t apic_xlate_vector(uchar_t vector);
782 extern uchar_t apic_allocate_vector(int ipl, int irq, int pri);
783 extern void apic_free_vector(uchar_t vector);
784 extern int apic_allocate_irq(int irq);
785 extern uint32_t apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid,
786     uchar_t intin);
787 extern int apic_rebind(apic_irq_t *irq_ptr, int bind_cpu,
788     struct ioapic_reprogram_data *drep);
789 extern int apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu);
790 extern int apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type);
791 extern int apic_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp,
792     psm_intr_op_t intr_op, int *result);
793 extern int apic_state(psm_state_request_t *);
794 extern boolean_t apic_cpu_in_range(int cpu);
795 extern int apic_check_msi_support();
796 extern apic_irq_t *apic_find_irq(dev_info_t *dip, struct intrspec *ispec,
797     int type);
798 extern int apic_navail_vector(dev_info_t *dip, int pri);
799 extern int apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count,
800     int pri, int behavior);
801 extern int apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count,
802     int pri, int behavior);
803 extern void  apic_free_vectors(dev_info_t *dip, int inum, int count, int pri,
804     int type);
805 extern int apic_get_vector_intr_info(int vecirq,
806     apic_get_intr_t *intr_params_p);
807 extern uchar_t apic_find_multi_vectors(int pri, int count);
808 extern int apic_setup_io_intr(void *p, int irq, boolean_t deferred);
809 extern uint32_t *mapin_apic(uint32_t addr, size_t len, int flags);
810 extern uint32_t *mapin_ioapic(uint32_t addr, size_t len, int flags);
811 extern void mapout_apic(caddr_t addr, size_t len);
812 extern void mapout_ioapic(caddr_t addr, size_t len);
813 extern uchar_t apic_modify_vector(uchar_t vector, int irq);
814 extern void apic_pci_msi_unconfigure(dev_info_t *rdip, int type, int inum);
815 extern void apic_pci_msi_disable_mode(dev_info_t *rdip, int type);
816 extern void apic_pci_msi_enable_mode(dev_info_t *rdip, int type, int inum);
817 extern void apic_pci_msi_enable_vector(apic_irq_t *, int type, int inum,
818     int vector, int count, int target_apic_id);
819 extern char *apic_get_apic_type();
820 extern uint16_t	apic_get_apic_version();
821 extern void x2apic_send_ipi();
822 extern void apic_ret();
823 extern int apic_detect_x2apic();
824 extern void apic_enable_x2apic();
825 extern int apic_local_mode();
826 extern void apic_change_eoi();
827 extern void apic_send_EOI(uint32_t);
828 extern void apic_send_directed_EOI(uint32_t);
829 extern uint64_t apic_calibrate();
830 extern void x2apic_send_pir_ipi(processorid_t);
831 
832 extern volatile uint32_t *apicadr;	/* virtual addr of local APIC   */
833 extern int apic_forceload;
834 extern apic_cpus_info_t *apic_cpus;
835 #ifdef _MACHDEP
836 extern cpuset_t apic_cpumask;
837 #endif
838 extern uint_t apic_picinit_called;
839 extern uchar_t apic_ipltopri[MAXIPL+1];
840 extern uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1];
841 extern int apic_max_device_irq;
842 extern int apic_min_device_irq;
843 extern apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1];
844 extern volatile uint32_t *apicioadr[MAX_IO_APIC];
845 extern uchar_t apic_io_id[MAX_IO_APIC];
846 extern lock_t apic_ioapic_lock;
847 extern uint32_t apic_physaddr[MAX_IO_APIC];
848 extern kmutex_t airq_mutex;
849 extern int apic_first_avail_irq;
850 extern uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL];
851 extern int apic_imcrp;
852 extern int apic_revector_pending;
853 extern char apic_level_intr[APIC_MAX_VECTOR+1];
854 extern uchar_t apic_resv_vector[MAXIPL+1];
855 extern int apic_sample_factor_redistribution;
856 extern int apic_int_busy_mark;
857 extern int apic_int_free_mark;
858 extern int apic_diff_for_redistribution;
859 extern int apic_poweroff_method;
860 extern int apic_enable_acpi;
861 extern int apic_nproc;
862 extern int apic_max_nproc;
863 extern int apic_next_bind_cpu;
864 extern int apic_redistribute_sample_interval;
865 extern int apic_multi_msi_enable;
866 extern int apic_sci_vect;
867 extern int apic_hpet_vect;
868 extern uchar_t apic_ipls[];
869 extern apic_reg_ops_t *apic_reg_ops;
870 extern apic_reg_ops_t local_apic_regs_ops;
871 extern apic_mode_t apic_mode;
872 extern void x2apic_update_psm();
873 extern void apic_change_ops();
874 extern void apic_common_send_ipi(int, int);
875 extern void apic_set_directed_EOI_handler();
876 extern int apic_directed_EOI_supported();
877 extern void apic_common_send_pir_ipi(processorid_t);
878 
879 extern apic_intrmap_ops_t *apic_vt_ops;
880 
881 #ifdef	__cplusplus
882 }
883 #endif
884 
885 #endif	/* _SYS_APIC_APIC_H */
886