1 /*
2 * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved.
3 */
4
5 /*
6 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
7 * Copyright (c) 2006-2008, 2013, Intel Corporation
8 * Jesse Barnes <jesse.barnes@intel.com>
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a
11 * copy of this software and associated documentation files (the "Software"),
12 * to deal in the Software without restriction, including without limitation
13 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
14 * and/or sell copies of the Software, and to permit persons to whom the
15 * Software is furnished to do so, subject to the following conditions:
16 *
17 * The above copyright notice and this permission notice (including the next
18 * paragraph) shall be included in all copies or substantial portions of the
19 * Software.
20 *
21 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
22 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
23 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
24 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
25 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
26 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
27 * DEALINGS IN THE SOFTWARE.
28 *
29 * Authors:
30 * Eric Anholt <eric@anholt.net>
31 */
32 #include <sys/types.h>
33 #include <sys/ddi.h>
34 #include "drmP.h"
35 #include "drm.h"
36 #include "intel_drv.h"
37 #include "i915_drm.h"
38 #include "i915_drv.h"
39 #include "drm_sun_i2c.h"
40
41 struct gmbus_port {
42 const char *name;
43 int reg;
44 };
45
46 static const struct gmbus_port gmbus_ports[] = {
47 { "ssc", GPIOB },
48 { "vga", GPIOA },
49 { "panel", GPIOC },
50 { "dpc", GPIOD },
51 { "dpb", GPIOE },
52 { "dpd", GPIOF },
53 };
54
55 /* Intel GPIO access functions */
56
57 #define I2C_RISEFALL_TIME 10
58
59 static inline struct intel_gmbus *
to_intel_gmbus(struct i2c_adapter * i2c)60 to_intel_gmbus(struct i2c_adapter *i2c)
61 {
62 return container_of(i2c, struct intel_gmbus, adapter);
63 }
64
65 void
intel_i2c_reset(struct drm_device * dev)66 intel_i2c_reset(struct drm_device *dev)
67 {
68 struct drm_i915_private *dev_priv = dev->dev_private;
69 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
70 }
71
intel_i2c_quirk_set(struct drm_i915_private * dev_priv,bool enable)72 static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
73 {
74 u32 val;
75
76 /* When using bit bashing for I2C, this bit needs to be set to 1 */
77 if (!IS_PINEVIEW(dev_priv->dev))
78 return;
79
80 val = I915_READ(DSPCLK_GATE_D);
81 if (enable)
82 val |= DPCUNIT_CLOCK_GATE_DISABLE;
83 else
84 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
85 I915_WRITE(DSPCLK_GATE_D, val);
86 }
87
get_reserved(struct intel_gmbus * bus)88 static u32 get_reserved(struct intel_gmbus *bus)
89 {
90 struct drm_i915_private *dev_priv = bus->dev_priv;
91 struct drm_device *dev = dev_priv->dev;
92 u32 reserved = 0;
93
94 /* On most chips, these bits must be preserved in software. */
95 if (!IS_I830(dev) && !IS_845G(dev))
96 reserved = I915_READ_NOTRACE(bus->gpio_reg) &
97 (GPIO_DATA_PULLUP_DISABLE |
98 GPIO_CLOCK_PULLUP_DISABLE);
99
100 return reserved;
101 }
102
vga_get_clock(void * data)103 static int vga_get_clock(void *data)
104 {
105 struct intel_gmbus *bus = data;
106 struct drm_i915_private *dev_priv = bus->dev_priv;
107 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
108 }
109
vga_get_data(void * data)110 static int vga_get_data(void *data)
111 {
112 struct intel_gmbus *bus = data;
113 struct drm_i915_private *dev_priv = bus->dev_priv;
114 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
115 }
116
get_clock(void * data)117 static int get_clock(void *data)
118 {
119 struct intel_gmbus *bus = data;
120 struct drm_i915_private *dev_priv = bus->dev_priv;
121 u32 reserved = get_reserved(bus);
122 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
123 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
124 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
125 }
126
get_data(void * data)127 static int get_data(void *data)
128 {
129 struct intel_gmbus *bus = data;
130 struct drm_i915_private *dev_priv = bus->dev_priv;
131 u32 reserved = get_reserved(bus);
132 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
133 I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
134 return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
135 }
136
set_clock(void * data,int state_high)137 static void set_clock(void *data, int state_high)
138 {
139 struct intel_gmbus *bus = data;
140 struct drm_i915_private *dev_priv = bus->dev_priv;
141 u32 reserved = get_reserved(bus);
142 u32 clock_bits;
143
144 if (state_high)
145 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
146 else
147 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
148 GPIO_CLOCK_VAL_MASK;
149
150 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
151 POSTING_READ(bus->gpio_reg);
152 }
153
set_data(void * data,int state_high)154 static void set_data(void *data, int state_high)
155 {
156 struct intel_gmbus *bus = data;
157 struct drm_i915_private *dev_priv = bus->dev_priv;
158 u32 reserved = get_reserved(bus);
159 u32 data_bits;
160
161 if (state_high)
162 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
163 else
164 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
165 GPIO_DATA_VAL_MASK;
166
167 I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
168 POSTING_READ(bus->gpio_reg);
169 }
170
171 static int
intel_gpio_pre_xfer(struct i2c_adapter * adapter)172 intel_gpio_pre_xfer(struct i2c_adapter *adapter)
173 {
174 struct intel_gmbus *bus = container_of(adapter,
175 struct intel_gmbus,
176 adapter);
177 struct drm_i915_private *dev_priv = bus->dev_priv;
178
179 intel_i2c_reset(dev_priv->dev);
180 intel_i2c_quirk_set(dev_priv, true);
181 set_data(bus, 1);
182 set_clock(bus, 1);
183 udelay(I2C_RISEFALL_TIME);
184 return 0;
185 }
186
187 static void
intel_gpio_post_xfer(struct i2c_adapter * adapter)188 intel_gpio_post_xfer(struct i2c_adapter *adapter)
189 {
190 struct intel_gmbus *bus = container_of(adapter,
191 struct intel_gmbus,
192 adapter);
193 struct drm_i915_private *dev_priv = bus->dev_priv;
194
195 set_data(bus, 1);
196 set_clock(bus, 1);
197 intel_i2c_quirk_set(dev_priv, false);
198 }
199
200 static void
intel_gpio_setup(struct intel_gmbus * bus,u32 pin)201 intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
202 {
203 struct drm_i915_private *dev_priv = bus->dev_priv;
204 struct i2c_adapter *algo;
205
206 algo = &bus->adapter;
207
208 /* -1 to map pin pair to gmbus index */
209 bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg;
210
211 bus->adapter.algo_data = algo;
212 /* OSOL_i915 Begin */
213 algo->setsda = set_data;
214 algo->setscl = set_clock;
215 if (pin == 2) {
216 algo->getsda = vga_get_data;
217 algo->getscl = vga_get_clock;
218 } else {
219 algo->getsda = get_data;
220 algo->getscl = get_clock;
221 }
222 algo->udelay = I2C_RISEFALL_TIME;
223 algo->timeout = drv_usectohz(2200);
224 /* OSOL End */
225 algo->data = bus;
226 }
227
228 /*
229 * gmbus on gen4 seems to be able to generate legacy interrupts even when in MSI
230 * mode. This results in spurious interrupt warnings if the legacy irq no. is
231 * shared with another device. The kernel then disables that interrupt source
232 * and so prevents the other device from working properly.
233 */
234 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
235 static int
gmbus_wait_hw_status(struct drm_i915_private * dev_priv,u32 gmbus2_status,u32 gmbus4_irq_en)236 gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
237 u32 gmbus2_status,
238 u32 gmbus4_irq_en)
239 {
240 int reg_offset = dev_priv->gpio_mmio_base;
241 u32 gmbus2 = 0;
242 int ret;
243 if (!HAS_GMBUS_IRQ(dev_priv->dev))
244 gmbus4_irq_en = 0;
245
246 /* Important: The hw handles only the first bit, so set only one! Since
247 * we also need to check for NAKs besides the hw ready/idle signal, we
248 * need to wake up periodically and check that ourselves. */
249 I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
250
251 ret = wait_for((gmbus2 = I915_READ(GMBUS2 + reg_offset))
252 & (GMBUS_SATOER | gmbus2_status), 50);
253
254 I915_WRITE(GMBUS4 + reg_offset, 0);
255
256 if (ret)
257 return -ETIMEDOUT;
258
259 if (gmbus2 & GMBUS_SATOER)
260 return -ENXIO;
261 if (gmbus2 & gmbus2_status)
262 return 0;
263
264 return -ETIMEDOUT;
265 }
266
267 static int
gmbus_wait_idle(struct drm_i915_private * dev_priv)268 gmbus_wait_idle(struct drm_i915_private *dev_priv)
269 {
270 int ret;
271 int reg_offset = dev_priv->gpio_mmio_base;
272
273 #define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)
274
275 if (!HAS_GMBUS_IRQ(dev_priv->dev))
276 return wait_for(C, 10);
277
278 /* Important: The hw handles only the first bit, so set only one! */
279 I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
280
281 ret = wait_for(C, 10);
282
283 I915_WRITE(GMBUS4 + reg_offset, 0);
284
285 if (!ret)
286 return 0;
287 else
288 return -ETIMEDOUT;
289 #undef C
290 }
291
292 static int
gmbus_xfer_read(struct drm_i915_private * dev_priv,struct i2c_msg * msg,u32 gmbus1_index)293 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
294 u32 gmbus1_index)
295 {
296 int reg_offset = dev_priv->gpio_mmio_base;
297 u16 len = msg->len;
298 u8 *buf = msg->buf;
299
300 I915_WRITE(GMBUS1 + reg_offset,
301 gmbus1_index |
302 GMBUS_CYCLE_WAIT |
303 (len << GMBUS_BYTE_COUNT_SHIFT) |
304 (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
305 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
306 while (len) {
307 int ret;
308 u32 val, loop = 0;
309
310 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
311 GMBUS_HW_RDY_EN);
312 if (ret)
313 return ret;
314
315 val = I915_READ(GMBUS3 + reg_offset);
316 do {
317 *buf++ = val & 0xff;
318 val >>= 8;
319 } while (--len && ++loop < 4);
320 }
321
322 return 0;
323 }
324
325 static int
gmbus_xfer_write(struct drm_i915_private * dev_priv,struct i2c_msg * msg)326 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
327 {
328 int reg_offset = dev_priv->gpio_mmio_base;
329 u16 len = msg->len;
330 u8 *buf = msg->buf;
331 u32 val, loop;
332
333 val = loop = 0;
334 while (len && loop < 4) {
335 val |= *buf++ << (8 * loop++);
336 len -= 1;
337 }
338
339 I915_WRITE(GMBUS3 + reg_offset, val);
340 I915_WRITE(GMBUS1 + reg_offset,
341 GMBUS_CYCLE_WAIT |
342 (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
343 (msg->addr << GMBUS_SLAVE_ADDR_SHIFT) |
344 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
345 while (len) {
346 int ret;
347
348 val = loop = 0;
349 do {
350 val |= *buf++ << (8 * loop);
351 } while (--len && ++loop < 4);
352
353 I915_WRITE(GMBUS3 + reg_offset, val);
354
355 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
356 GMBUS_HW_RDY_EN);
357 if (ret)
358 return ret;
359 }
360 return 0;
361 }
362
363 /*
364 * The gmbus controller can combine a 1 or 2 byte write with a read that
365 * immediately follows it by using an "INDEX" cycle.
366 */
367 static bool
gmbus_is_index_read(struct i2c_msg * msgs,int i,int num)368 gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
369 {
370 return (i + 1 < num &&
371 !(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
372 (msgs[i + 1].flags & I2C_M_RD));
373 }
374
375 static int
gmbus_xfer_index_read(struct drm_i915_private * dev_priv,struct i2c_msg * msgs)376 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
377 {
378 int reg_offset = dev_priv->gpio_mmio_base;
379 u32 gmbus1_index = 0;
380 u32 gmbus5 = 0;
381 int ret;
382
383 if (msgs[0].len == 2)
384 gmbus5 = GMBUS_2BYTE_INDEX_EN |
385 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
386 if (msgs[0].len == 1)
387 gmbus1_index = GMBUS_CYCLE_INDEX |
388 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
389
390 /* GMBUS5 holds 16-bit index */
391 if (gmbus5)
392 I915_WRITE(GMBUS5 + reg_offset, gmbus5);
393
394 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
395
396 /* Clear GMBUS5 after each index transfer */
397 if (gmbus5)
398 I915_WRITE(GMBUS5 + reg_offset, 0);
399
400 return ret;
401 }
402
403 static int
gmbus_xfer(struct i2c_adapter * adapter,struct i2c_msg * msgs,int num)404 gmbus_xfer(struct i2c_adapter *adapter,
405 struct i2c_msg *msgs,
406 int num)
407 {
408 struct intel_gmbus *bus = container_of(adapter,
409 struct intel_gmbus,
410 adapter);
411 struct drm_i915_private *dev_priv = bus->dev_priv;
412 int i, reg_offset;
413 int ret = 0;
414
415 mutex_lock(&dev_priv->gmbus_mutex);
416
417 if (bus->force_bit) {
418 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
419 goto out;
420 }
421
422 reg_offset = dev_priv->gpio_mmio_base;
423
424 I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
425
426 for (i = 0; i < num; i++) {
427 if (gmbus_is_index_read(msgs, i, num)) {
428 ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
429 i += 1; /* set i to the index of the read xfer */
430 } else if (msgs[i].flags & I2C_M_RD) {
431 ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
432 } else {
433 ret = gmbus_xfer_write(dev_priv, &msgs[i]);
434 }
435
436 if (ret == -ETIMEDOUT)
437 goto timeout;
438 if (ret == -ENXIO)
439 goto clear_err;
440
441 ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
442 GMBUS_HW_WAIT_EN);
443 if (ret == -ENXIO)
444 goto clear_err;
445 if (ret)
446 goto timeout;
447 }
448
449 /* Generate a STOP condition on the bus. Note that gmbus can't generata
450 * a STOP on the very first cycle. To simplify the code we
451 * unconditionally generate the STOP condition with an additional gmbus
452 * cycle. */
453 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
454
455 /* Mark the GMBUS interface as disabled after waiting for idle.
456 * We will re-enable it at the start of the next xfer,
457 * till then let it sleep.
458 */
459 if (gmbus_wait_idle(dev_priv)) {
460 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
461 adapter->name);
462 ret = -ETIMEDOUT;
463 }
464 I915_WRITE(GMBUS0 + reg_offset, 0);
465 ret = ret ? ret : i;
466 goto out;
467
468 clear_err:
469 /*
470 * Wait for bus to IDLE before clearing NAK.
471 * If we clear the NAK while bus is still active, then it will stay
472 * active and the next transaction may fail.
473 *
474 * If no ACK is received during the address phase of a transaction, the
475 * adapter must report -ENXIO. It is not clear what to return if no ACK
476 * is received at other times. But we have to be careful to not return
477 * spurious -ENXIO because that will prevent i2c and drm edid functions
478 * from retrying. So return -ENXIO only when gmbus properly quiescents -
479 * timing out seems to happen when there _is_ a ddc chip present, but
480 * it's slow responding and only answers on the 2nd retry.
481 */
482 ret = -ENXIO;
483 if (gmbus_wait_idle(dev_priv)) {
484 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
485 adapter->name);
486 ret = -ETIMEDOUT;
487 }
488
489 /* Toggle the Software Clear Interrupt bit. This has the effect
490 * of resetting the GMBUS controller and so clearing the
491 * BUS_ERROR raised by the slave's NAK.
492 */
493 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
494 I915_WRITE(GMBUS1 + reg_offset, 0);
495 I915_WRITE(GMBUS0 + reg_offset, 0);
496
497 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
498 adapter->name, msgs[i].addr,
499 (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
500
501 goto out;
502
503 timeout:
504 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
505 bus->adapter.name, bus->reg0 & 0xff);
506 I915_WRITE(GMBUS0 + reg_offset, 0);
507
508 /* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
509 bus->force_bit = 1;
510 ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
511
512 out:
513 mutex_unlock(&dev_priv->gmbus_mutex);
514 return ret;
515 }
516
gmbus_func(struct i2c_adapter * adapter)517 static u32 gmbus_func(struct i2c_adapter *adapter)
518 {
519 return adapter->algo->functionality(adapter);
520 }
521
522 static struct i2c_algorithm gmbus_algorithm = {
523 .master_xfer = gmbus_xfer,
524 .functionality = gmbus_func
525 };
526
527 /**
528 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
529 * @dev: DRM device
530 */
intel_setup_gmbus(struct drm_device * dev)531 int intel_setup_gmbus(struct drm_device *dev)
532 {
533 struct drm_i915_private *dev_priv = dev->dev_private;
534 int i;
535
536 if (HAS_PCH_NOP(dev))
537 return 0;
538 else if (HAS_PCH_SPLIT(dev))
539 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
540 else if (IS_VALLEYVIEW(dev))
541 dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
542 else
543 dev_priv->gpio_mmio_base = 0;
544
545 mutex_init(&dev_priv->gmbus_mutex, NULL, MUTEX_DRIVER, NULL);
546 DRM_INIT_WAITQUEUE(&dev_priv->gmbus_wait_queue, DRM_INTR_PRI(dev));
547
548 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
549 struct intel_gmbus *bus = &dev_priv->gmbus[i];
550 u32 port = i + 1; /* +1 to map gmbus index to pin pair */
551
552 snprintf(bus->adapter.name,
553 sizeof(bus->adapter.name),
554 "i915 gmbus %s",
555 gmbus_ports[i].name);
556
557 // bus->adapter.dev.parent = &dev->pdev->dev;
558 bus->dev_priv = dev_priv;
559
560 bus->adapter.algo = &gmbus_algorithm;
561
562 /* By default use a conservative clock rate */
563 bus->reg0 = port | GMBUS_RATE_100KHZ;
564
565 /* gmbus seems to be broken on i830 */
566 if (IS_I830(dev))
567 bus->force_bit = 1;
568
569 intel_gpio_setup(bus, port);
570 }
571
572 intel_i2c_reset(dev_priv->dev);
573
574 return 0;
575 }
576
intel_gmbus_get_adapter(struct drm_i915_private * dev_priv,unsigned port)577 struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
578 unsigned port)
579 {
580 WARN_ON(!intel_gmbus_is_port_valid(port));
581 /* -1 to map pin pair to gmbus index */
582 return (intel_gmbus_is_port_valid(port)) ?
583 &dev_priv->gmbus[port - 1].adapter : NULL;
584 }
585
intel_gmbus_set_speed(struct i2c_adapter * adapter,int speed)586 void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
587 {
588 struct intel_gmbus *bus = to_intel_gmbus(adapter);
589
590 bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
591 }
592
intel_gmbus_force_bit(struct i2c_adapter * adapter,bool force_bit)593 void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
594 {
595 struct intel_gmbus *bus = to_intel_gmbus(adapter);
596
597 bus->force_bit += force_bit ? 1 : -1;
598 DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
599 force_bit ? "en" : "dis", adapter->name,
600 bus->force_bit);
601 }
602
intel_teardown_gmbus(struct drm_device * dev)603 void intel_teardown_gmbus(struct drm_device *dev)
604 {
605 /*
606 for (i = 0; i < GMBUS_NUM_PORTS; i++) {
607 struct intel_gmbus *bus = &dev_priv->gmbus[i];
608 // i2c_del_adapter(&bus->adapter);
609 }
610 */
611 }
612
613 /* workaround for fixing hdmi issue */
intel_gmbus_hdmi_set_adapter(struct i2c_adapter * adapter)614 void intel_gmbus_hdmi_set_adapter(struct i2c_adapter *adapter)
615 {
616 adapter->getsda = vga_get_data;
617 adapter->getscl = vga_get_clock;
618 }
619