1 /*
2 * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved.
3 */
4
5 /*
6 *
7 * Copyright 2008, 2013, (c) Intel Corporation
8 * Jesse Barnes <jbarnes@virtuousgeek.org>
9 *
10 * Permission is hereby granted, free of charge, to any person obtaining a
11 * copy of this software and associated documentation files (the
12 * "Software"), to deal in the Software without restriction, including
13 * without limitation the rights to use, copy, modify, merge, publish,
14 * distribute, sub license, and/or sell copies of the Software, and to
15 * permit persons to whom the Software is furnished to do so, subject to
16 * the following conditions:
17 *
18 * The above copyright notice and this permission notice (including the
19 * next paragraph) shall be included in all copies or substantial portions
20 * of the Software.
21 *
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
23 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
25 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
26 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
27 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
28 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 */
30
31 #include "drmP.h"
32 #include "drm.h"
33 #include "i915_drm.h"
34 #include "intel_drv.h"
35 #include "i915_reg.h"
36
i915_read_indexed(struct drm_device * dev,u16 index_port,u16 data_port,u8 reg)37 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg)
38 {
39 struct drm_i915_private *dev_priv = dev->dev_private;
40
41 I915_WRITE8(index_port, reg);
42 return I915_READ8(data_port);
43 }
44
i915_read_ar(struct drm_device * dev,u16 st01,u8 reg,u16 palette_enable)45 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable)
46 {
47 struct drm_i915_private *dev_priv = dev->dev_private;
48
49 I915_READ8(st01);
50 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
51 return I915_READ8(VGA_AR_DATA_READ);
52 }
53
i915_write_ar(struct drm_device * dev,u16 st01,u8 reg,u8 val,u16 palette_enable)54 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable)
55 {
56 struct drm_i915_private *dev_priv = dev->dev_private;
57
58 I915_READ8(st01);
59 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg);
60 I915_WRITE8(VGA_AR_DATA_WRITE, val);
61 }
62
i915_write_indexed(struct drm_device * dev,u16 index_port,u16 data_port,u8 reg,u8 val)63 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 val)
64 {
65 struct drm_i915_private *dev_priv = dev->dev_private;
66
67 I915_WRITE8(index_port, reg);
68 I915_WRITE8(data_port, val);
69 }
70
i915_save_vga(struct drm_device * dev)71 static void i915_save_vga(struct drm_device *dev)
72 {
73 struct drm_i915_private *dev_priv = dev->dev_private;
74 int i;
75 u16 cr_index, cr_data, st01;
76
77 /* VGA state */
78 dev_priv->regfile.saveVGA0 = I915_READ(VGA0);
79 dev_priv->regfile.saveVGA1 = I915_READ(VGA1);
80 dev_priv->regfile.saveVGA_PD = I915_READ(VGA_PD);
81 dev_priv->regfile.saveVGACNTRL = I915_READ(i915_vgacntrl_reg(dev));
82
83 /* VGA color palette registers */
84 dev_priv->regfile.saveDACMASK = I915_READ8(VGA_DACMASK);
85
86 /* MSR bits */
87 dev_priv->regfile.saveMSR = I915_READ8(VGA_MSR_READ);
88 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
89 cr_index = VGA_CR_INDEX_CGA;
90 cr_data = VGA_CR_DATA_CGA;
91 st01 = VGA_ST01_CGA;
92 } else {
93 cr_index = VGA_CR_INDEX_MDA;
94 cr_data = VGA_CR_DATA_MDA;
95 st01 = VGA_ST01_MDA;
96 }
97
98 /* CRT controller regs */
99 i915_write_indexed(dev, cr_index, cr_data, 0x11,
100 i915_read_indexed(dev, cr_index, cr_data, 0x11) &
101 (~0x80));
102 for (i = 0; i <= 0x24; i++)
103 dev_priv->regfile.saveCR[i] =
104 i915_read_indexed(dev, cr_index, cr_data, i);
105 /* Make sure we don't turn off CR group 0 writes */
106 dev_priv->regfile.saveCR[0x11] &= ~0x80;
107
108 /* Attribute controller registers */
109 I915_READ8(st01);
110 dev_priv->regfile.saveAR_INDEX = I915_READ8(VGA_AR_INDEX);
111 for (i = 0; i <= 0x14; i++)
112 dev_priv->regfile.saveAR[i] = i915_read_ar(dev, st01, i, 0);
113 I915_READ8(st01);
114 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX);
115 I915_READ8(st01);
116
117 /* Graphics controller registers */
118 for (i = 0; i < 9; i++)
119 dev_priv->regfile.saveGR[i] =
120 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i);
121
122 dev_priv->regfile.saveGR[0x10] =
123 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10);
124 dev_priv->regfile.saveGR[0x11] =
125 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11);
126 dev_priv->regfile.saveGR[0x18] =
127 i915_read_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18);
128
129 /* Sequencer registers */
130 for (i = 0; i < 8; i++)
131 dev_priv->regfile.saveSR[i] =
132 i915_read_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i);
133 }
134
i915_restore_vga(struct drm_device * dev)135 static void i915_restore_vga(struct drm_device *dev)
136 {
137 struct drm_i915_private *dev_priv = dev->dev_private;
138 int i;
139 u16 cr_index, cr_data, st01;
140
141 /* VGA state */
142 I915_WRITE(i915_vgacntrl_reg(dev), dev_priv->regfile.saveVGACNTRL);
143
144 I915_WRITE(VGA0, dev_priv->regfile.saveVGA0);
145 I915_WRITE(VGA1, dev_priv->regfile.saveVGA1);
146 I915_WRITE(VGA_PD, dev_priv->regfile.saveVGA_PD);
147 POSTING_READ(VGA_PD);
148 udelay(150);
149
150 /* MSR bits */
151 I915_WRITE8(VGA_MSR_WRITE, dev_priv->regfile.saveMSR);
152 if (dev_priv->regfile.saveMSR & VGA_MSR_CGA_MODE) {
153 cr_index = VGA_CR_INDEX_CGA;
154 cr_data = VGA_CR_DATA_CGA;
155 st01 = VGA_ST01_CGA;
156 } else {
157 cr_index = VGA_CR_INDEX_MDA;
158 cr_data = VGA_CR_DATA_MDA;
159 st01 = VGA_ST01_MDA;
160 }
161
162 /* Sequencer registers, don't write SR07 */
163 for (i = 0; i < 7; i++)
164 i915_write_indexed(dev, VGA_SR_INDEX, VGA_SR_DATA, i,
165 dev_priv->regfile.saveSR[i]);
166
167 /* CRT controller regs */
168 /* Enable CR group 0 writes */
169 i915_write_indexed(dev, cr_index, cr_data, 0x11, dev_priv->regfile.saveCR[0x11]);
170 for (i = 0; i <= 0x24; i++)
171 i915_write_indexed(dev, cr_index, cr_data, i, dev_priv->regfile.saveCR[i]);
172
173 /* Graphics controller regs */
174 for (i = 0; i < 9; i++)
175 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, i,
176 dev_priv->regfile.saveGR[i]);
177
178 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x10,
179 dev_priv->regfile.saveGR[0x10]);
180 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x11,
181 dev_priv->regfile.saveGR[0x11]);
182 i915_write_indexed(dev, VGA_GR_INDEX, VGA_GR_DATA, 0x18,
183 dev_priv->regfile.saveGR[0x18]);
184
185 /* Attribute controller registers */
186 I915_READ8(st01); /* switch back to index mode */
187 for (i = 0; i <= 0x14; i++)
188 i915_write_ar(dev, st01, i, dev_priv->regfile.saveAR[i], 0);
189 I915_READ8(st01); /* switch back to index mode */
190 I915_WRITE8(VGA_AR_INDEX, dev_priv->regfile.saveAR_INDEX | 0x20);
191 I915_READ8(st01);
192
193 /* VGA color palette registers */
194 I915_WRITE8(VGA_DACMASK, dev_priv->regfile.saveDACMASK);
195 }
196
i915_save_display(struct drm_device * dev)197 static void i915_save_display(struct drm_device *dev)
198 {
199 struct drm_i915_private *dev_priv = dev->dev_private;
200 unsigned long flags;
201
202 /* Display arbitration control */
203 if (INTEL_INFO(dev)->gen <= 4)
204 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB);
205
206 /* This is only meaningful in non-KMS mode */
207 /* Don't regfile.save them in KMS mode */
208 if (!drm_core_check_feature(dev, DRIVER_MODESET))
209 i915_save_display_reg(dev);
210
211 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
212
213 /* LVDS state */
214 if (HAS_PCH_SPLIT(dev)) {
215 dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
216 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_PCH_CTL1);
217 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_PCH_CTL2);
218 dev_priv->regfile.saveBLC_CPU_PWM_CTL = I915_READ(BLC_PWM_CPU_CTL);
219 dev_priv->regfile.saveBLC_CPU_PWM_CTL2 = I915_READ(BLC_PWM_CPU_CTL2);
220 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
221 dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
222 } else {
223 dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
224 dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
225 dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
226 dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
227 if (INTEL_INFO(dev)->gen >= 4)
228 dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
229 if (IS_MOBILE(dev) && !IS_I830(dev))
230 dev_priv->regfile.saveLVDS = I915_READ(LVDS);
231 }
232
233 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
234
235 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
236 dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
237
238 if (HAS_PCH_SPLIT(dev)) {
239 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
240 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
241 dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
242 } else {
243 dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
244 dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
245 dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
246 }
247
248 /* Only regfile.save FBC state on the platform that supports FBC */
249 if (I915_HAS_FBC(dev)) {
250 if (HAS_PCH_SPLIT(dev)) {
251 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(ILK_DPFC_CB_BASE);
252 } else if (IS_GM45(dev)) {
253 dev_priv->regfile.saveDPFC_CB_BASE = I915_READ(DPFC_CB_BASE);
254 } else {
255 dev_priv->regfile.saveFBC_CFB_BASE = I915_READ(FBC_CFB_BASE);
256 dev_priv->regfile.saveFBC_LL_BASE = I915_READ(FBC_LL_BASE);
257 dev_priv->regfile.saveFBC_CONTROL2 = I915_READ(FBC_CONTROL2);
258 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL);
259 }
260 }
261
262 if (!drm_core_check_feature(dev, DRIVER_MODESET))
263 i915_save_vga(dev);
264 }
265
i915_restore_display(struct drm_device * dev)266 static void i915_restore_display(struct drm_device *dev)
267 {
268 struct drm_i915_private *dev_priv = dev->dev_private;
269 u64 mask = 0xffffffff;
270 unsigned long flags;
271
272 /* Display arbitration */
273 if (INTEL_INFO(dev)->gen <= 4)
274 I915_WRITE(DSPARB, dev_priv->regfile.saveDSPARB);
275
276 if (!drm_core_check_feature(dev, DRIVER_MODESET))
277 i915_restore_display_reg(dev);
278
279 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
280
281 /* LVDS state */
282 if (INTEL_INFO(dev)->gen >= 4 && !HAS_PCH_SPLIT(dev))
283 I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
284
285 if (drm_core_check_feature(dev, DRIVER_MODESET))
286 mask = ~LVDS_PORT_EN;
287
288 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
289 I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);
290 else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
291 I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
292
293 if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
294 I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
295
296 if (HAS_PCH_SPLIT(dev)) {
297 I915_WRITE(BLC_PWM_PCH_CTL1, dev_priv->regfile.saveBLC_PWM_CTL);
298 I915_WRITE(BLC_PWM_PCH_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
299 /* NOTE: BLC_PWM_CPU_CTL must be written after BLC_PWM_CPU_CTL2;
300 * otherwise we get blank eDP screen after S3 on some machines
301 */
302 I915_WRITE(BLC_PWM_CPU_CTL2, dev_priv->regfile.saveBLC_CPU_PWM_CTL2);
303 I915_WRITE(BLC_PWM_CPU_CTL, dev_priv->regfile.saveBLC_CPU_PWM_CTL);
304 I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
305 I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
306 I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
307 I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
308 I915_WRITE(RSTDBYCTL,
309 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
310 } else {
311 I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
312 I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
313 I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
314 I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
315 I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
316 I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
317 I915_WRITE(PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
318 }
319
320 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
321
322 /* only restore FBC info on the platform that supports FBC*/
323 intel_disable_fbc(dev);
324 if (I915_HAS_FBC(dev)) {
325 if (HAS_PCH_SPLIT(dev)) {
326 I915_WRITE(ILK_DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
327 } else if (IS_GM45(dev)) {
328 I915_WRITE(DPFC_CB_BASE, dev_priv->regfile.saveDPFC_CB_BASE);
329 } else {
330 I915_WRITE(FBC_CFB_BASE, dev_priv->regfile.saveFBC_CFB_BASE);
331 I915_WRITE(FBC_LL_BASE, dev_priv->regfile.saveFBC_LL_BASE);
332 I915_WRITE(FBC_CONTROL2, dev_priv->regfile.saveFBC_CONTROL2);
333 I915_WRITE(FBC_CONTROL, dev_priv->regfile.saveFBC_CONTROL);
334 }
335 }
336
337 if (!drm_core_check_feature(dev, DRIVER_MODESET))
338 i915_restore_vga(dev);
339 else
340 i915_redisable_vga(dev);
341 }
342
i915_save_state(struct drm_device * dev)343 int i915_save_state(struct drm_device *dev)
344 {
345 struct drm_i915_private *dev_priv = dev->dev_private;
346 int i;
347
348 pci_read_config_byte(dev->pdev, LBB, &dev_priv->regfile.saveLBB);
349
350 mutex_lock(&dev->struct_mutex);
351
352 i915_save_display(dev);
353
354 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
355 /* Interrupt state */
356 if (HAS_PCH_SPLIT(dev)) {
357 dev_priv->regfile.saveDEIER = I915_READ(DEIER);
358 dev_priv->regfile.saveDEIMR = I915_READ(DEIMR);
359 dev_priv->regfile.saveGTIER = I915_READ(GTIER);
360 dev_priv->regfile.saveGTIMR = I915_READ(GTIMR);
361 dev_priv->regfile.saveFDI_RXA_IMR = I915_READ(_FDI_RXA_IMR);
362 dev_priv->regfile.saveFDI_RXB_IMR = I915_READ(_FDI_RXB_IMR);
363 dev_priv->regfile.saveMCHBAR_RENDER_STANDBY =
364 I915_READ(RSTDBYCTL);
365 dev_priv->regfile.savePCH_PORT_HOTPLUG = I915_READ(PCH_PORT_HOTPLUG);
366 } else {
367 dev_priv->regfile.saveIER = I915_READ(IER);
368 dev_priv->regfile.saveIMR = I915_READ(IMR);
369 }
370 }
371
372 intel_disable_gt_powersave(dev);
373
374 /* Cache mode state */
375 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0);
376
377 /* Memory Arbitration state */
378 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE);
379
380 /* Scratch space */
381 for (i = 0; i < 16; i++) {
382 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF00 + (i << 2));
383 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF10 + (i << 2));
384 }
385 for (i = 0; i < 3; i++)
386 dev_priv->regfile.saveSWF2[i] = I915_READ(SWF30 + (i << 2));
387
388 mutex_unlock(&dev->struct_mutex);
389
390 return 0;
391 }
392
i915_restore_state(struct drm_device * dev)393 int i915_restore_state(struct drm_device *dev)
394 {
395 struct drm_i915_private *dev_priv = dev->dev_private;
396 int i;
397
398 pci_write_config_byte(dev->pdev, LBB, dev_priv->regfile.saveLBB);
399
400 mutex_lock(&dev->struct_mutex);
401
402 i915_gem_restore_fences(dev);
403 i915_restore_display(dev);
404
405 if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
406 /* Interrupt state */
407 if (HAS_PCH_SPLIT(dev)) {
408 I915_WRITE(DEIER, dev_priv->regfile.saveDEIER);
409 I915_WRITE(DEIMR, dev_priv->regfile.saveDEIMR);
410 I915_WRITE(GTIER, dev_priv->regfile.saveGTIER);
411 I915_WRITE(GTIMR, dev_priv->regfile.saveGTIMR);
412 I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
413 I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
414 I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
415 } else {
416 I915_WRITE(IER, dev_priv->regfile.saveIER);
417 I915_WRITE(IMR, dev_priv->regfile.saveIMR);
418 }
419 }
420
421 /* Cache mode state */
422 I915_WRITE(CACHE_MODE_0, dev_priv->regfile.saveCACHE_MODE_0 | 0xffff0000);
423
424 /* Memory arbitration state */
425 I915_WRITE(MI_ARB_STATE, dev_priv->regfile.saveMI_ARB_STATE | 0xffff0000);
426
427 for (i = 0; i < 16; i++) {
428 I915_WRITE(SWF00 + (i << 2), dev_priv->regfile.saveSWF0[i]);
429 I915_WRITE(SWF10 + (i << 2), dev_priv->regfile.saveSWF1[i]);
430 }
431 for (i = 0; i < 3; i++)
432 I915_WRITE(SWF30 + (i << 2), dev_priv->regfile.saveSWF2[i]);
433
434 mutex_unlock(&dev->struct_mutex);
435
436 intel_i2c_reset(dev);
437
438 return 0;
439 }
440