1 /*
2 * Copyright (c) 2012, 2013, Oracle and/or its affiliates. All rights reserved.
3 */
4
5 /*
6 * Copyright © 2008,2010, 2013 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 *
27 * Authors:
28 * Eric Anholt <eric@anholt.net>
29 * Chris Wilson <chris@chris-wilson.co.uk>
30 *
31 */
32
33 #include "drmP.h"
34 #include "drm.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "intel_drv.h"
38
39 struct eb_objects {
40 int and;
41 struct drm_file *file_priv;
42 };
43
44 static struct eb_objects *
eb_create(int size,struct drm_file * file_priv)45 eb_create(int size, struct drm_file *file_priv)
46 {
47 struct eb_objects *eb;
48 eb = kzalloc(sizeof(struct eb_objects), GFP_KERNEL);
49 if (eb == NULL)
50 return eb;
51 eb->file_priv = file_priv;
52 eb->and = size;
53 return eb;
54 }
55
56 static void
eb_reset(struct eb_objects * eb)57 eb_reset(struct eb_objects *eb)
58 {
59 }
60
61 static void
eb_add_object(struct eb_objects * eb,struct drm_i915_gem_object * obj)62 eb_add_object(struct eb_objects *eb, struct drm_i915_gem_object *obj)
63 {
64 }
65
66 static struct drm_i915_gem_object *
eb_get_object(struct eb_objects * eb,unsigned long handle)67 eb_get_object(struct eb_objects *eb, unsigned long handle)
68 {
69 return NULL;
70 }
71
72 static void
eb_destroy(struct eb_objects * eb)73 eb_destroy(struct eb_objects *eb)
74 {
75 kfree(eb, sizeof(struct eb_objects));
76 }
77
use_cpu_reloc(struct drm_i915_gem_object * obj)78 static inline int use_cpu_reloc(struct drm_i915_gem_object *obj)
79 {
80 return (obj->base.write_domain == I915_GEM_DOMAIN_CPU ||
81 !obj->map_and_fenceable ||
82 obj->cache_level != I915_CACHE_NONE);
83 }
84
85 static int
i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object * obj,struct eb_objects * eb,struct drm_i915_gem_relocation_entry * reloc)86 i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj,
87 struct eb_objects *eb,
88 struct drm_i915_gem_relocation_entry *reloc)
89 {
90 struct drm_device *dev = obj->base.dev;
91 struct drm_gem_object *target_obj;
92 struct drm_i915_gem_object *target_i915_obj;
93 uint32_t reloc_val, reloc_offset;
94 uint32_t target_offset;
95 uint32_t *reloc_entry;
96 int ret = -EINVAL;
97
98 target_obj = drm_gem_object_lookup(dev, eb->file_priv,
99 reloc->target_handle);
100 if (target_obj == NULL)
101 return -ENOENT;
102
103 target_i915_obj = to_intel_bo(target_obj);
104 target_offset = target_i915_obj->gtt_offset;
105
106 /* Sandybridge PPGTT errata: We need a global gtt mapping for MI and
107 * pipe_control writes because the gpu doesn't properly redirect them
108 * through the ppgtt for non_secure batchbuffers. */
109 if (IS_GEN6(dev) &&
110 reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION &&
111 !target_i915_obj->has_global_gtt_mapping) {
112 i915_gem_gtt_bind_object(target_i915_obj,
113 target_i915_obj->cache_level);
114 }
115
116 /* Validate that the target is in a valid r/w GPU domain */
117 if (reloc->write_domain & (reloc->write_domain - 1)) {
118 DRM_DEBUG("reloc with multiple write domains: "
119 "obj %p target %d offset %d "
120 "read %08x write %08x",
121 obj, reloc->target_handle,
122 (int) reloc->offset,
123 reloc->read_domains,
124 reloc->write_domain);
125 goto err;
126 }
127 if (unlikely((reloc->write_domain | reloc->read_domains)
128 & ~I915_GEM_GPU_DOMAINS)) {
129 DRM_DEBUG("reloc with read/write non-GPU domains: "
130 "obj %p target %d offset %d "
131 "read %08x write %08x",
132 obj, reloc->target_handle,
133 (int) reloc->offset,
134 reloc->read_domains,
135 reloc->write_domain);
136 goto err;
137 }
138
139 target_obj->pending_read_domains |= reloc->read_domains;
140 target_obj->pending_write_domain |= reloc->write_domain;
141
142 /* If the relocation already has the right value in it, no
143 * more work needs to be done.
144 */
145 if (target_offset == reloc->presumed_offset)
146 goto out;
147
148 /* Check that the relocation address is valid... */
149 if (reloc->offset > obj->base.size - 4) {
150 DRM_ERROR("Relocation beyond object bounds: "
151 "obj %p target %d offset %d size %d.\n",
152 obj, reloc->target_handle,
153 (int) reloc->offset,
154 (int) obj->base.size);
155 goto err;
156 }
157 if (reloc->offset & 3) {
158 DRM_ERROR("Relocation not 4-byte aligned: "
159 "obj %p target %d offset %d.\n",
160 obj, reloc->target_handle,
161 (int) reloc->offset);
162 goto err;
163 }
164
165 ret = i915_gem_object_set_to_gtt_domain(obj, true);
166 if (ret)
167 return ret;
168
169 ret = i915_gem_object_put_fence(obj);
170 if (ret)
171 return ret;
172
173 /* Map the page containing the relocation we're going to
174 * perform.
175 */
176 int reloc_base = (reloc->offset & ~(PAGE_SIZE-1));
177 reloc_offset = reloc->offset & (PAGE_SIZE-1);
178 reloc_entry = (uint32_t *)(uintptr_t)(obj->page_list[reloc_base/PAGE_SIZE] + reloc_offset);
179 reloc_val = target_offset + reloc->delta;
180
181 *reloc_entry = reloc_val;
182
183 /* and update the user's relocation entry */
184 reloc->presumed_offset = target_offset;
185
186 out:
187 ret = 0;
188 err:
189 drm_gem_object_unreference(target_obj);
190 return ret;
191 }
192
193 static int
i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object * obj,struct eb_objects * eb)194 i915_gem_execbuffer_relocate_object(struct drm_i915_gem_object *obj,
195 struct eb_objects *eb)
196 {
197 #define N_RELOC(x) ((x) / sizeof(struct drm_i915_gem_relocation_entry))
198 struct drm_i915_gem_relocation_entry stack_reloc[N_RELOC(512)];
199 struct drm_i915_gem_relocation_entry __user *user_relocs;
200 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
201 int remain, ret;
202
203 user_relocs = (void __user *)(uintptr_t)entry->relocs_ptr;
204
205 remain = entry->relocation_count;
206 while (remain) {
207 struct drm_i915_gem_relocation_entry *r = stack_reloc;
208 int count = remain;
209 if (count > ARRAY_SIZE(stack_reloc))
210 count = ARRAY_SIZE(stack_reloc);
211 remain -= count;
212
213 if (DRM_COPY_FROM_USER(r, user_relocs, count*sizeof(r[0])))
214 return -EFAULT;
215
216 do {
217 u64 offset = r->presumed_offset;
218
219 ret = i915_gem_execbuffer_relocate_entry(obj, eb, r);
220 if (ret)
221 return ret;
222
223 if (r->presumed_offset != offset &&
224 DRM_COPY_TO_USER(&user_relocs->presumed_offset,
225 &r->presumed_offset,
226 sizeof(r->presumed_offset))) {
227 return -EFAULT;
228 }
229
230 user_relocs++;
231 r++;
232 } while (--count);
233 }
234
235 return 0;
236 #undef N_RELOC
237 }
238
239 static int
i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object * obj,struct eb_objects * eb,struct drm_i915_gem_relocation_entry * relocs)240 i915_gem_execbuffer_relocate_object_slow(struct drm_i915_gem_object *obj,
241 struct eb_objects *eb,
242 struct drm_i915_gem_relocation_entry *relocs)
243 {
244 const struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
245 int i, ret;
246
247 for (i = 0; i < entry->relocation_count; i++) {
248 ret = i915_gem_execbuffer_relocate_entry(obj, eb, &relocs[i]);
249 if (ret)
250 return ret;
251 }
252
253 return 0;
254 }
255
256 static int
i915_gem_execbuffer_relocate(struct drm_device * dev,struct eb_objects * eb,struct list_head * objects)257 i915_gem_execbuffer_relocate(struct drm_device *dev,
258 struct eb_objects *eb,
259 struct list_head *objects)
260 {
261 struct drm_i915_gem_object *obj;
262 int ret = 0;
263
264 list_for_each_entry(obj, struct drm_i915_gem_object, objects, exec_list) {
265 ret = i915_gem_execbuffer_relocate_object(obj, eb);
266 if (ret)
267 break;
268 }
269 return ret;
270 }
271
272 #define __EXEC_OBJECT_HAS_PIN (1UL<<31)
273 #define __EXEC_OBJECT_HAS_FENCE (1UL<<30)
274
275 static int
need_reloc_mappable(struct drm_i915_gem_object * obj)276 need_reloc_mappable(struct drm_i915_gem_object *obj)
277 {
278 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
279 return entry->relocation_count && !use_cpu_reloc(obj);
280 }
281
282 static int
i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object * obj,struct intel_ring_buffer * ring,bool * need_reloc)283 i915_gem_execbuffer_reserve_object(struct drm_i915_gem_object *obj,
284 struct intel_ring_buffer *ring,
285 bool *need_reloc)
286 {
287 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
288 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
289 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
290 bool need_fence, need_mappable;
291 int ret;
292
293 need_fence =
294 has_fenced_gpu_access &&
295 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
296 obj->tiling_mode != I915_TILING_NONE;
297
298 /* workaround for GEN5 for gpu hang with ugnx */
299 if (IS_GEN5(ring->dev))
300 need_fence = obj->tiling_mode != I915_TILING_NONE;
301
302 need_mappable = need_fence || need_reloc_mappable(obj);
303
304 ret = i915_gem_object_pin(obj, entry->alignment, need_mappable, false);
305 if (ret)
306 return ret;
307
308 entry->flags |= __EXEC_OBJECT_HAS_PIN;
309
310 if (has_fenced_gpu_access) {
311 if (entry->flags & EXEC_OBJECT_NEEDS_FENCE) {
312 ret = i915_gem_object_get_fence(obj);
313 if (ret)
314 return ret;
315
316 if (i915_gem_object_pin_fence(obj))
317 entry->flags |= __EXEC_OBJECT_HAS_FENCE;
318
319 obj->pending_fenced_gpu_access = true;
320 }
321 }
322
323 /* Ensure ppgtt mapping exists if needed */
324 if (dev_priv->mm.aliasing_ppgtt && !obj->has_aliasing_ppgtt_mapping) {
325 i915_ppgtt_bind_object(dev_priv->mm.aliasing_ppgtt,
326 obj, obj->cache_level);
327
328 obj->has_aliasing_ppgtt_mapping = 1;
329 }
330
331 if (entry->offset != obj->gtt_offset) {
332 entry->offset = obj->gtt_offset;
333 *need_reloc = true;
334 }
335
336 if (entry->flags & EXEC_OBJECT_WRITE) {
337 obj->base.pending_read_domains = I915_GEM_DOMAIN_RENDER;
338 obj->base.pending_write_domain = I915_GEM_DOMAIN_RENDER;
339 }
340
341 if (entry->flags & EXEC_OBJECT_NEEDS_GTT &&
342 !obj->has_global_gtt_mapping)
343 i915_gem_gtt_bind_object(obj, obj->cache_level);
344
345 return 0;
346 }
347
348 static void
i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object * obj)349 i915_gem_execbuffer_unreserve_object(struct drm_i915_gem_object *obj)
350 {
351 struct drm_i915_gem_exec_object2 *entry;
352
353 if (!obj->gtt_space)
354 return;
355
356 entry = obj->exec_entry;
357
358 if (entry->flags & __EXEC_OBJECT_HAS_FENCE)
359 i915_gem_object_unpin_fence(obj);
360
361 if (entry->flags & __EXEC_OBJECT_HAS_PIN)
362 i915_gem_object_unpin(obj);
363
364 entry->flags &= ~(__EXEC_OBJECT_HAS_FENCE | __EXEC_OBJECT_HAS_PIN);
365 }
366
367 static int
i915_gem_execbuffer_reserve(struct intel_ring_buffer * ring,struct drm_file * file,struct list_head * objects,bool * need_relocs)368 i915_gem_execbuffer_reserve(struct intel_ring_buffer *ring,
369 struct drm_file *file,
370 struct list_head *objects,
371 bool *need_relocs)
372 {
373 struct drm_i915_gem_object *obj;
374 struct list_head ordered_objects;
375 struct list_head *tmp;
376 bool has_fenced_gpu_access = INTEL_INFO(ring->dev)->gen < 4;
377 struct drm_i915_gem_object *batch_obj;
378 int retry;
379 batch_obj = list_entry(objects->prev,
380 struct drm_i915_gem_object,
381 exec_list);
382
383 INIT_LIST_HEAD(&ordered_objects);
384 while (!list_empty(objects)) {
385 struct drm_i915_gem_exec_object2 *entry;
386 bool need_fence, need_mappable;
387
388 obj = list_first_entry(objects,
389 struct drm_i915_gem_object,
390 exec_list);
391 entry = obj->exec_entry;
392
393 need_fence =
394 has_fenced_gpu_access &&
395 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
396 obj->tiling_mode != I915_TILING_NONE;
397
398 /* workaround for GEN5 for gpu hang with ugnx */
399 if (IS_GEN5(ring->dev))
400 need_fence = obj->tiling_mode != I915_TILING_NONE;
401 need_mappable = need_fence || need_reloc_mappable(obj);
402
403 if (need_mappable)
404 list_move(&obj->exec_list, &ordered_objects, (caddr_t)obj);
405 else
406 list_move_tail(&obj->exec_list, &ordered_objects, (caddr_t)obj);
407
408 obj->base.pending_read_domains = I915_GEM_GPU_DOMAINS & ~I915_GEM_DOMAIN_COMMAND;
409 obj->base.pending_write_domain = 0;
410 obj->pending_fenced_gpu_access = false;
411
412 if (IS_GEN5(ring->dev) && (batch_obj != obj) && obj->gtt_offset) {
413 int err;
414 if (obj->tiling_mode != I915_TILING_NONE)
415 err = i915_gem_object_get_fence(obj);
416 else
417 err = i915_gem_object_put_fence(obj);
418 if (err)
419 DRM_ERROR("failed to get obj 0x%p fence %d", obj, err);
420 obj->pending_fenced_gpu_access = true;
421 }
422 }
423
424 tmp = objects->next;
425 list_splice(&ordered_objects, objects, tmp);
426
427 /* Attempt to pin all of the buffers into the GTT.
428 * This is done in 3 phases:
429 *
430 * 1a. Unbind all objects that do not match the GTT constraints for
431 * the execbuffer (fenceable, mappable, alignment etc).
432 * 1b. Increment pin count for already bound objects.
433 * 2. Bind new objects.
434 * 3. Decrement pin count.
435 *
436 * This avoid unnecessary unbinding of later objects in order to makr
437 * room for the earlier objects *unless* we need to defragment.
438 */
439 retry = 0;
440 do {
441 int ret = 0;
442
443 /* Unbind any ill-fitting objects or pin. */
444 list_for_each_entry(obj, struct drm_i915_gem_object, objects, exec_list) {
445 struct drm_i915_gem_exec_object2 *entry = obj->exec_entry;
446 bool need_fence, need_mappable;
447 if (!obj->gtt_space)
448 continue;
449 need_fence =
450 has_fenced_gpu_access &&
451 entry->flags & EXEC_OBJECT_NEEDS_FENCE &&
452 obj->tiling_mode != I915_TILING_NONE;
453
454 /* workaround for GEN5 for gpu hang with ugnx */
455 if (IS_GEN5(ring->dev))
456 need_fence = obj->tiling_mode != I915_TILING_NONE;
457 need_mappable = need_fence || need_reloc_mappable(obj);
458
459
460 if ((entry->alignment && obj->gtt_offset & (entry->alignment - 1)) ||
461 (need_mappable && !obj->map_and_fenceable))
462 ret = i915_gem_object_unbind(obj, 1);
463 else
464 ret = i915_gem_execbuffer_reserve_object(obj, ring, need_relocs);
465 if (ret)
466 goto err;
467 }
468
469 /* Bind fresh objects */
470 list_for_each_entry(obj, struct drm_i915_gem_object, objects, exec_list) {
471 if (obj->gtt_space)
472 continue;
473
474 ret = i915_gem_execbuffer_reserve_object(obj, ring, need_relocs);
475 if (ret)
476 goto err;
477 }
478
479 err: /* Decrement pin count for bound objects */
480 list_for_each_entry(obj, struct drm_i915_gem_object, objects, exec_list)
481 i915_gem_execbuffer_unreserve_object(obj);
482
483 if (ret != -ENOSPC || retry++)
484 return ret;
485
486 ret = i915_gem_evict_everything(ring->dev);
487 if (ret)
488 return ret;
489 } while (1);
490 /* LINTED */
491 }
492
493 static int
i915_gem_execbuffer_relocate_slow(struct drm_device * dev,struct drm_i915_gem_execbuffer2 * args,struct drm_file * file,struct intel_ring_buffer * ring,struct list_head * objects,struct eb_objects * eb,struct drm_i915_gem_exec_object2 * exec,int count)494 i915_gem_execbuffer_relocate_slow(struct drm_device *dev,
495 struct drm_i915_gem_execbuffer2 *args,
496 struct drm_file *file,
497 struct intel_ring_buffer *ring,
498 struct list_head *objects,
499 struct eb_objects *eb,
500 struct drm_i915_gem_exec_object2 *exec,
501 int count)
502 {
503 struct drm_i915_gem_relocation_entry *reloc;
504 struct drm_i915_gem_object *obj;
505 bool need_relocs;
506 int *reloc_offset;
507 int i, total, ret;
508
509 /* We may process another execbuffer during the unlock... */
510 while (!list_empty(objects)) {
511 obj = list_first_entry(objects,
512 struct drm_i915_gem_object,
513 exec_list);
514 list_del_init(&obj->exec_list);
515 drm_gem_object_unreference(&obj->base);
516 }
517
518 mutex_unlock(&dev->struct_mutex);
519
520 total = 0;
521 for (i = 0; i < count; i++)
522 total += exec[i].relocation_count;
523
524 reloc_offset = drm_calloc(count, sizeof(*reloc_offset), DRM_MEM_DRIVER);
525 reloc = drm_calloc(total, sizeof(*reloc), DRM_MEM_DRIVER);
526 if (reloc == NULL || reloc_offset == NULL) {
527 drm_free(reloc, total * sizeof(*reloc), DRM_MEM_DRIVER);
528 drm_free(reloc_offset, count * sizeof(*reloc_offset), DRM_MEM_DRIVER);
529 mutex_lock(&dev->struct_mutex);
530 return -ENOMEM;
531 }
532
533 total = 0;
534 for (i = 0; i < count; i++) {
535 struct drm_i915_gem_relocation_entry __user *user_relocs;
536
537 user_relocs = (void __user *)(uintptr_t)exec[i].relocs_ptr;
538
539 if (copy_from_user(reloc+total, user_relocs,
540 exec[i].relocation_count * sizeof(*reloc))) {
541 ret = -EFAULT;
542 mutex_lock(&dev->struct_mutex);
543 goto err;
544 }
545
546 reloc_offset[i] = total;
547 total += exec[i].relocation_count;
548 }
549
550 ret = i915_mutex_lock_interruptible(dev);
551 if (ret) {
552 mutex_lock(&dev->struct_mutex);
553 goto err;
554 }
555
556 /* reacquire the objects */
557 eb_reset(eb);
558 for (i = 0; i < count; i++) {
559 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
560 exec[i].handle));
561 if (&obj->base == NULL) {
562 DRM_DEBUG("Invalid object handle %d at index %d\n",
563 exec[i].handle, i);
564 ret = -ENOENT;
565 goto err;
566 }
567
568 list_add_tail(&obj->exec_list, objects, (caddr_t)obj);
569 obj->exec_handle = exec[i].handle;
570 obj->exec_entry = &exec[i];
571 eb_add_object(eb, obj);
572 }
573
574 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
575
576 ret = i915_gem_execbuffer_reserve(ring, file, objects, &need_relocs);
577 if (ret)
578 goto err;
579
580 list_for_each_entry(obj, struct drm_i915_gem_object, objects, exec_list) {
581 int offset = obj->exec_entry - exec;
582 ret = i915_gem_execbuffer_relocate_object_slow(obj, eb,
583 reloc + reloc_offset[offset]);
584 if (ret)
585 goto err;
586 }
587
588 /* Leave the user relocations as are, this is the painfully slow path,
589 * and we want to avoid the complication of dropping the lock whilst
590 * having buffers reserved in the aperture and so causing spurious
591 * ENOSPC for random operations.
592 */
593
594 err:
595 drm_free(reloc, total * sizeof(*reloc), DRM_MEM_DRIVER);
596 drm_free(reloc_offset, count * sizeof(*reloc_offset), DRM_MEM_DRIVER);
597 return ret;
598 }
599
600 static int
i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer * ring,struct list_head * objects)601 i915_gem_execbuffer_move_to_gpu(struct intel_ring_buffer *ring,
602 struct list_head *objects)
603 {
604 struct drm_i915_gem_object *obj;
605 uint32_t flush_domains = 0;
606 int ret;
607
608 list_for_each_entry(obj, struct drm_i915_gem_object, objects, exec_list) {
609 ret = i915_gem_object_sync(obj, ring);
610 if (ret)
611 return ret;
612
613 if (obj->base.write_domain & I915_GEM_DOMAIN_CPU)
614 i915_gem_clflush_object(obj);
615
616 flush_domains |= obj->base.write_domain;
617 }
618
619 if (flush_domains & I915_GEM_DOMAIN_CPU)
620 i915_gem_chipset_flush(ring->dev);
621
622 if (flush_domains & I915_GEM_DOMAIN_GTT)
623 membar_producer();
624
625 /* Unconditionally invalidate gpu caches and ensure that we do flush
626 * any residual writes from the previous batch.
627 */
628 return intel_ring_invalidate_all_caches(ring);
629 }
630
631 static bool
i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 * exec)632 i915_gem_check_execbuffer(struct drm_i915_gem_execbuffer2 *exec)
633 {
634 return ((exec->batch_start_offset | exec->batch_len) & 0x7) == 0;
635 }
636
637 static int
validate_exec_list(struct drm_i915_gem_exec_object2 * exec,int count)638 validate_exec_list(struct drm_i915_gem_exec_object2 *exec,
639 int count)
640 {
641 int i;
642 int relocs_total = 0;
643 int relocs_max = INT_MAX /
644 sizeof(struct drm_i915_gem_relocation_entry);
645
646 for (i = 0; i < count; i++) {
647 #if 0 /* Should match the if a few lines below */
648 char __user *ptr = (char __user *)(uintptr_t)exec[i].relocs_ptr;
649 int length; /* limited by fault_in_pages_readable() */
650 #endif
651
652 /*
653 * First check for malicious input causing overflow in
654 * the worst case where we need to allocate the entire
655 * relocation tree as a single array.
656 */
657 if (exec[i].relocation_count> relocs_max - relocs_total)
658 return -EINVAL;
659 relocs_total += exec[i].relocation_count;
660 #if 0
661 length = exec[i].relocation_count *
662 sizeof(struct drm_i915_gem_relocation_entry);
663 if (!access_ok(VERIFY_READ, ptr, length))
664 return -EFAULT;
665
666 /* we may also need to update the presumed offsets */
667 if (!access_ok(VERIFY_WRITE, ptr, length))
668 return -EFAULT;
669
670 if (fault_in_pages_readable(ptr, length))
671 return -EFAULT;
672 #endif
673 }
674
675 return 0;
676 }
677
678 static void
i915_gem_execbuffer_move_to_active(struct list_head * objects,struct intel_ring_buffer * ring)679 i915_gem_execbuffer_move_to_active(struct list_head *objects,
680 struct intel_ring_buffer *ring)
681 {
682 struct drm_i915_gem_object *obj;
683
684 list_for_each_entry(obj, struct drm_i915_gem_object, objects, exec_list) {
685 obj->base.write_domain = obj->base.pending_write_domain;
686 if (obj->base.write_domain == 0)
687 obj->base.pending_read_domains |= obj->base.read_domains;
688 obj->base.read_domains = obj->base.pending_read_domains;
689 obj->fenced_gpu_access = obj->pending_fenced_gpu_access;
690
691 i915_gem_object_move_to_active(obj, ring);
692 if (obj->base.write_domain) {
693 obj->dirty = 1;
694 obj->last_write_seqno = intel_ring_get_seqno(ring);
695 if (obj->pin_count) /* check for potential scanout */
696 intel_mark_fb_busy(obj, ring);
697 }
698
699 }
700 }
701
702 static void
i915_gem_execbuffer_retire_commands(struct drm_device * dev,struct drm_file * file,struct intel_ring_buffer * ring,struct drm_i915_gem_object * obj)703 i915_gem_execbuffer_retire_commands(struct drm_device *dev,
704 struct drm_file *file,
705 struct intel_ring_buffer *ring,
706 struct drm_i915_gem_object *obj)
707 {
708 /* Unconditionally force add_request to emit a full flush. */
709 ring->gpu_caches_dirty = true;
710
711 /* Add a breadcrumb for the completion of the batch buffer */
712 (void)__i915_add_request(ring, file, obj, NULL);
713 }
714
715 static int
i915_reset_gen7_sol_offsets(struct drm_device * dev,struct intel_ring_buffer * ring)716 i915_reset_gen7_sol_offsets(struct drm_device *dev,
717 struct intel_ring_buffer *ring)
718 {
719 drm_i915_private_t *dev_priv = dev->dev_private;
720 int ret, i;
721
722 if (!IS_GEN7(dev) || ring != &dev_priv->ring[RCS])
723 return 0;
724
725 ret = intel_ring_begin(ring, 4 * 3);
726 if (ret)
727 return ret;
728
729 for (i = 0; i < 4; i++) {
730 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
731 intel_ring_emit(ring, GEN7_SO_WRITE_OFFSET(i));
732 intel_ring_emit(ring, 0);
733 }
734
735 intel_ring_advance(ring);
736
737 return 0;
738 }
739
740 static int
741 /* LINTED */
i915_gem_do_execbuffer(struct drm_device * dev,void * data,struct drm_file * file,struct drm_i915_gem_execbuffer2 * args,struct drm_i915_gem_exec_object2 * exec)742 i915_gem_do_execbuffer(struct drm_device *dev, void *data,
743 struct drm_file *file,
744 struct drm_i915_gem_execbuffer2 *args,
745 struct drm_i915_gem_exec_object2 *exec)
746 {
747 drm_i915_private_t *dev_priv = dev->dev_private;
748 struct list_head objects;
749 struct eb_objects *eb;
750 struct drm_i915_gem_object *batch_obj;
751 struct drm_clip_rect *cliprects = NULL;
752 struct intel_ring_buffer *ring;
753 u32 ctx_id = i915_execbuffer2_get_context_id(*args);
754 struct batch_info_list *node = NULL;
755 u32 exec_start, exec_len;
756 u32 mask, flags;
757 int ret, mode, i;
758 bool need_relocs;
759
760 if (!i915_gem_check_execbuffer(args)) {
761 DRM_DEBUG("execbuf with invalid offset/length\n");
762 return -EINVAL;
763 }
764
765 ret = validate_exec_list(exec, args->buffer_count);
766 if (ret)
767 return ret;
768
769 flags = 0;
770 if (args->flags & I915_EXEC_SECURE) {
771 if (!file->is_master)
772 return -EPERM;
773
774 flags |= I915_DISPATCH_SECURE;
775 }
776 if (args->flags & I915_EXEC_IS_PINNED)
777 flags |= I915_DISPATCH_PINNED;
778
779 switch (args->flags & I915_EXEC_RING_MASK) {
780 case I915_EXEC_DEFAULT:
781 case I915_EXEC_RENDER:
782 ring = &dev_priv->ring[RCS];
783 break;
784 case I915_EXEC_BSD:
785 ring = &dev_priv->ring[VCS];
786 if (ctx_id != 0) {
787 DRM_DEBUG("Ring %s doesn't support contexts\n",
788 ring->name);
789 return -EPERM;
790 }
791 break;
792 case I915_EXEC_BLT:
793 ring = &dev_priv->ring[BCS];
794 if (ctx_id != 0) {
795 DRM_DEBUG("Ring %s doesn't support contexts\n",
796 ring->name);
797 return -EPERM;
798 }
799 break;
800 case I915_EXEC_VEBOX:
801 ring = &dev_priv->ring[VECS];
802 if (ctx_id != 0) {
803 DRM_DEBUG("Ring %s doesn't support contexts\n",
804 ring->name);
805 return -EPERM;
806 }
807 break;
808
809 default:
810 DRM_DEBUG("execbuf with unknown ring: %d\n",
811 (int)(args->flags & I915_EXEC_RING_MASK));
812 return -EINVAL;
813 }
814 if (!intel_ring_initialized(ring)) {
815 DRM_DEBUG("execbuf with invalid ring: %d\n",
816 (int)(args->flags & I915_EXEC_RING_MASK));
817 return -EINVAL;
818 }
819
820 mode = args->flags & I915_EXEC_CONSTANTS_MASK;
821 mask = I915_EXEC_CONSTANTS_MASK;
822 switch (mode) {
823 case I915_EXEC_CONSTANTS_REL_GENERAL:
824 case I915_EXEC_CONSTANTS_ABSOLUTE:
825 case I915_EXEC_CONSTANTS_REL_SURFACE:
826 if (ring == &dev_priv->ring[RCS] &&
827 mode != dev_priv->relative_constants_mode) {
828 if (INTEL_INFO(dev)->gen < 4)
829 return -EINVAL;
830
831 if (INTEL_INFO(dev)->gen > 5 &&
832 mode == I915_EXEC_CONSTANTS_REL_SURFACE)
833 return -EINVAL;
834
835 /* The HW changed the meaning on this bit on gen6 */
836 if (INTEL_INFO(dev)->gen >= 6)
837 mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE;
838 }
839 break;
840 default:
841 DRM_DEBUG("execbuf with unknown constants: %d\n", mode);
842 return -EINVAL;
843 }
844
845 if (args->buffer_count < 1) {
846 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
847 return -EINVAL;
848 }
849
850 if (args->num_cliprects != 0) {
851 if (ring != &dev_priv->ring[RCS]) {
852 DRM_DEBUG("clip rectangles are only valid with the render ring\n");
853 return -EINVAL;
854 }
855
856 if (INTEL_INFO(dev)->gen >= 5) {
857 DRM_DEBUG("clip rectangles are only valid on pre-gen5\n");
858 return -EINVAL;
859 }
860
861 if (args->num_cliprects > UINT_MAX / sizeof(*cliprects)) {
862 DRM_DEBUG("execbuf with %u cliprects\n",
863 args->num_cliprects);
864 return -EINVAL;
865 }
866
867 cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects),
868 GFP_KERNEL);
869 if (cliprects == NULL) {
870 ret = -ENOMEM;
871 goto pre_mutex_err;
872 }
873
874 if (DRM_COPY_FROM_USER(cliprects,
875 (struct drm_clip_rect __user *)
876 (uintptr_t) args->cliprects_ptr,
877 sizeof(*cliprects) * args->num_cliprects)) {
878 ret = -EFAULT;
879 goto pre_mutex_err;
880 }
881 }
882
883 ret = i915_mutex_lock_interruptible(dev);
884 if (ret)
885 goto pre_mutex_err;
886
887 if (dev_priv->mm.suspended || dev_priv->gpu_hang) {
888 mutex_unlock(&dev->struct_mutex);
889 ret = -EBUSY;
890 goto pre_mutex_err;
891 }
892
893 eb = eb_create(args->buffer_count, file);
894 if (eb == NULL) {
895 mutex_unlock(&dev->struct_mutex);
896 ret = -ENOMEM;
897 goto pre_mutex_err;
898 }
899
900 if (MDB_TRACK_ENABLE) {
901 node = drm_alloc(sizeof (struct batch_info_list), DRM_MEM_MAPS);
902 node->num = args->buffer_count;
903 node->obj_list = drm_alloc(node->num * sizeof(caddr_t), DRM_MEM_MAPS);
904 list_add(&node->head, &dev_priv->batch_list, (caddr_t)node);
905 }
906 /* Look up object handles */
907 INIT_LIST_HEAD(&objects);
908 for (i = 0; i < args->buffer_count; i++) {
909 struct drm_i915_gem_object *obj;
910
911 obj = to_intel_bo(drm_gem_object_lookup(dev, file,
912 exec[i].handle));
913 if (&obj->base == NULL) {
914 DRM_DEBUG("Invalid object handle %d at index %d\n",
915 exec[i].handle, i);
916 /* prevent error path from reading uninitialized data */
917 ret = -ENOENT;
918 goto err;
919 }
920
921 if (!list_empty(&obj->exec_list)) {
922 DRM_DEBUG("Object %p [handle %d, index %d] appears more than once in object list\n",
923 obj, exec[i].handle, i);
924 ret = -EINVAL;
925 goto err;
926 }
927
928 list_add_tail(&obj->exec_list, &objects, (caddr_t)obj);
929 obj->exec_handle = exec[i].handle;
930 obj->exec_entry = &exec[i];
931 eb_add_object(eb, obj);
932
933 /*
934 * The condition here was: if (MDB_TRACK_ENABLE)...
935 * but that caused GCC warnings. This is equivalent.
936 */
937 if (node != NULL)
938 node->obj_list[i] = (caddr_t)obj;
939 TRACE_GEM_OBJ_HISTORY(obj, "prepare emit");
940 }
941
942 /* take note of the batch buffer before we might reorder the lists */
943 batch_obj = list_entry(objects.prev,
944 struct drm_i915_gem_object,
945 exec_list);
946
947 /* Move the objects en-masse into the GTT, evicting if necessary. */
948 need_relocs = (args->flags & I915_EXEC_NO_RELOC) == 0;
949 ret = i915_gem_execbuffer_reserve(ring, file, &objects, &need_relocs);
950 if (ret)
951 goto err;
952
953 /* The objects are in their final locations, apply the relocations. */
954 if (need_relocs)
955 ret = i915_gem_execbuffer_relocate(dev, eb, &objects);
956 if (ret) {
957 if (ret == -EFAULT) {
958 ret = i915_gem_execbuffer_relocate_slow(dev, args, file, ring,
959 &objects, eb,
960 exec,
961 args->buffer_count);
962 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
963 }
964 if (ret)
965 goto err;
966 }
967
968 /* Set the pending read domains for the batch buffer to COMMAND */
969 if (batch_obj->base.pending_write_domain) {
970 DRM_DEBUG("Attempting to use self-modifying batch buffer\n");
971 ret = -EINVAL;
972 goto err;
973 }
974 batch_obj->base.pending_read_domains |= I915_GEM_DOMAIN_COMMAND;
975
976 /* snb/ivb/vlv conflate the "batch in ppgtt" bit with the "non-secure
977 * batch" bit. Hence we need to pin secure batches into the global gtt.
978 * hsw should have this fixed, but let's be paranoid and do it
979 * unconditionally for now. */
980 if (flags & I915_DISPATCH_SECURE && !batch_obj->has_global_gtt_mapping)
981 i915_gem_gtt_bind_object(batch_obj, batch_obj->cache_level);
982
983 ret = i915_gem_execbuffer_move_to_gpu(ring, &objects);
984 if (ret)
985 goto err;
986
987 ret = i915_switch_context(ring, file, ctx_id);
988 if (ret)
989 goto err;
990
991 if (ring == &dev_priv->ring[RCS] &&
992 mode != dev_priv->relative_constants_mode) {
993 ret = intel_ring_begin(ring, 4);
994 if (ret)
995 goto err;
996
997 intel_ring_emit(ring, MI_NOOP);
998 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
999 intel_ring_emit(ring, INSTPM);
1000 intel_ring_emit(ring, mask << 16 | mode);
1001 intel_ring_advance(ring);
1002
1003 dev_priv->relative_constants_mode = mode;
1004 }
1005
1006 if (args->flags & I915_EXEC_GEN7_SOL_RESET) {
1007 ret = i915_reset_gen7_sol_offsets(dev, ring);
1008 if (ret)
1009 goto err;
1010 }
1011
1012 exec_start = batch_obj->gtt_offset + args->batch_start_offset;
1013 exec_len = args->batch_len;
1014 if (cliprects) {
1015 for (i = 0; i < args->num_cliprects; i++) {
1016 ret = i915_emit_box(dev, &cliprects[i],
1017 args->DR1, args->DR4);
1018 if (ret)
1019 goto err;
1020
1021 ret = ring->dispatch_execbuffer(ring,
1022 exec_start, exec_len,
1023 flags);
1024 if (ret)
1025 goto err;
1026 }
1027 } else {
1028 ret = ring->dispatch_execbuffer(ring,
1029 exec_start, exec_len,
1030 flags);
1031 if (ret)
1032 goto err;
1033 }
1034
1035 i915_gem_execbuffer_move_to_active(&objects, ring);
1036 i915_gem_execbuffer_retire_commands(dev, file, ring, batch_obj);
1037
1038 err:
1039 eb_destroy(eb);
1040 while (!list_empty(&objects)) {
1041 struct drm_i915_gem_object *obj;
1042
1043 obj = list_first_entry(&objects,
1044 struct drm_i915_gem_object,
1045 exec_list);
1046 TRACE_GEM_OBJ_HISTORY(obj, "finish emit");
1047 list_del_init(&obj->exec_list);
1048 drm_gem_object_unreference(&obj->base);
1049 }
1050
1051 mutex_unlock(&dev->struct_mutex);
1052
1053 pre_mutex_err:
1054
1055 drm_free(cliprects, args->num_cliprects * sizeof(*cliprects),
1056 DRM_MEM_DRIVER);
1057 return ret;
1058 }
1059
1060
1061 /*
1062 * Legacy execbuffer just creates an exec2 list from the original exec object
1063 * list array and passes it to the real function.
1064 */
1065 int
1066 /* LINTED */
i915_gem_execbuffer(DRM_IOCTL_ARGS)1067 i915_gem_execbuffer(DRM_IOCTL_ARGS)
1068 {
1069 struct drm_i915_gem_execbuffer *args = data;
1070 struct drm_i915_gem_execbuffer2 exec2;
1071 struct drm_i915_gem_exec_object *exec_list = NULL;
1072 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1073 int ret, i;
1074
1075 if (args->buffer_count < 1) {
1076 DRM_DEBUG("execbuf with %d buffers\n", args->buffer_count);
1077 return -EINVAL;
1078 }
1079
1080 /* Copy in the exec list from userland */
1081 exec_list = drm_calloc(sizeof(*exec_list), args->buffer_count, DRM_MEM_DRIVER);
1082 exec2_list = drm_calloc(sizeof(*exec2_list), args->buffer_count, DRM_MEM_DRIVER);
1083 if (exec_list == NULL || exec2_list == NULL) {
1084 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1085 args->buffer_count);
1086 drm_free(exec_list, args->buffer_count * sizeof(*exec_list), DRM_MEM_DRIVER);
1087 drm_free(exec2_list, args->buffer_count * sizeof(*exec2_list), DRM_MEM_DRIVER);
1088 return -ENOMEM;
1089 }
1090 ret = copy_from_user(exec_list,
1091 (struct drm_i915_relocation_entry __user *)
1092 (uintptr_t) args->buffers_ptr,
1093 sizeof(*exec_list) * args->buffer_count);
1094 if (ret != 0) {
1095 DRM_DEBUG("copy %d exec entries failed %d\n",
1096 args->buffer_count, ret);
1097 drm_free(exec_list, args->buffer_count * sizeof(*exec_list), DRM_MEM_DRIVER);
1098 drm_free(exec2_list, args->buffer_count * sizeof(*exec2_list), DRM_MEM_DRIVER);
1099 return -EFAULT;
1100 }
1101
1102 for (i = 0; i < args->buffer_count; i++) {
1103 exec2_list[i].handle = exec_list[i].handle;
1104 exec2_list[i].relocation_count = exec_list[i].relocation_count;
1105 exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr;
1106 exec2_list[i].alignment = exec_list[i].alignment;
1107 exec2_list[i].offset = exec_list[i].offset;
1108 if (INTEL_INFO(dev)->gen < 4)
1109 exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE;
1110 else
1111 exec2_list[i].flags = 0;
1112 }
1113
1114 exec2.buffers_ptr = args->buffers_ptr;
1115 exec2.buffer_count = args->buffer_count;
1116 exec2.batch_start_offset = args->batch_start_offset;
1117 exec2.batch_len = args->batch_len;
1118 exec2.DR1 = args->DR1;
1119 exec2.DR4 = args->DR4;
1120 exec2.num_cliprects = args->num_cliprects;
1121 exec2.cliprects_ptr = args->cliprects_ptr;
1122 exec2.flags = I915_EXEC_RENDER;
1123 i915_execbuffer2_set_context_id(exec2, 0);
1124
1125 ret = i915_gem_do_execbuffer(dev, data, file, &exec2, exec2_list);
1126 if (!ret) {
1127 /* Copy the new buffer offsets back to the user's exec list. */
1128 for (i = 0; i < args->buffer_count; i++)
1129 exec_list[i].offset = exec2_list[i].offset;
1130 /* ... and back out to userspace */
1131 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1132 (uintptr_t) args->buffers_ptr,
1133 exec_list,
1134 sizeof(*exec_list) * args->buffer_count);
1135 if (ret) {
1136 ret = -EFAULT;
1137 DRM_DEBUG("failed to copy %d exec entries "
1138 "back to user (%d)\n",
1139 args->buffer_count, ret);
1140 }
1141 }
1142
1143 drm_free(exec_list, args->buffer_count * sizeof(*exec_list), DRM_MEM_DRIVER);
1144 drm_free(exec2_list, args->buffer_count * sizeof(*exec2_list), DRM_MEM_DRIVER);
1145 return ret;
1146 }
1147
1148 int
1149 /* LINTED */
i915_gem_execbuffer2(DRM_IOCTL_ARGS)1150 i915_gem_execbuffer2(DRM_IOCTL_ARGS)
1151 {
1152 struct drm_i915_gem_execbuffer2 *args = data;
1153 struct drm_i915_gem_exec_object2 *exec2_list = NULL;
1154 int ret;
1155
1156 if (args->buffer_count < 1 ||
1157 args->buffer_count > UINT_MAX / sizeof(*exec2_list)) {
1158 DRM_DEBUG("execbuf2 with %d buffers\n", args->buffer_count);
1159 return -EINVAL;
1160 }
1161
1162 exec2_list = drm_calloc(sizeof(*exec2_list), args->buffer_count, DRM_MEM_DRIVER);
1163 if (exec2_list == NULL) {
1164 DRM_DEBUG("Failed to allocate exec list for %d buffers\n",
1165 args->buffer_count);
1166 return -ENOMEM;
1167 }
1168 ret = copy_from_user(exec2_list,
1169 (struct drm_i915_relocation_entry __user *)
1170 (uintptr_t) args->buffers_ptr,
1171 sizeof(*exec2_list) * args->buffer_count);
1172 if (ret != 0) {
1173 DRM_DEBUG("copy %d exec entries failed %d\n",
1174 args->buffer_count, ret);
1175 drm_free(exec2_list, args->buffer_count * sizeof(*exec2_list), DRM_MEM_DRIVER);
1176 return -EFAULT;
1177 }
1178
1179 ret = i915_gem_do_execbuffer(dev, data, file, args, exec2_list);
1180 if (!ret) {
1181 /* Copy the new buffer offsets back to the user's exec list. */
1182 ret = copy_to_user((struct drm_i915_relocation_entry __user *)
1183 (uintptr_t) args->buffers_ptr,
1184 exec2_list,
1185 sizeof(*exec2_list) * args->buffer_count);
1186 if (ret) {
1187 ret = -EFAULT;
1188 DRM_DEBUG("failed to copy %d exec entries "
1189 "back to user (%d)\n",
1190 args->buffer_count, ret);
1191 }
1192 }
1193
1194 drm_free(exec2_list, args->buffer_count * sizeof(*exec2_list), DRM_MEM_DRIVER);
1195 return ret;
1196 }
1197