1 /*
2 * Copyright (c) 2006, 2013, Oracle and/or its affiliates. All rights reserved.
3 */
4
5 /*
6 * Copyright (c) 2009, 2013, Intel Corporation.
7 * All Rights Reserved.
8 *
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
18 * Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
25 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 * IN THE SOFTWARE.
27 *
28 * Authors:
29 * Eric Anholt <eric@anholt.net>
30 *
31 */
32
33 #include "drmP.h"
34 #include "drm.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37
38 /** @file i915_gem_tiling.c
39 *
40 * Support for managing tiling state of buffer objects.
41 *
42 * The idea behind tiling is to increase cache hit rates by rearranging
43 * pixel data so that a group of pixel accesses are in the same cacheline.
44 * Performance improvement from doing this on the back/depth buffer are on
45 * the order of 30%.
46 *
47 * Intel architectures make this somewhat more complicated, though, by
48 * adjustments made to addressing of data when the memory is in interleaved
49 * mode (matched pairs of DIMMS) to improve memory bandwidth.
50 * For interleaved memory, the CPU sends every sequential 64 bytes
51 * to an alternate memory channel so it can get the bandwidth from both.
52 *
53 * The GPU also rearranges its accesses for increased bandwidth to interleaved
54 * memory, and it matches what the CPU does for non-tiled. However, when tiled
55 * it does it a little differently, since one walks addresses not just in the
56 * X direction but also Y. So, along with alternating channels when bit
57 * 6 of the address flips, it also alternates when other bits flip -- Bits 9
58 * (every 512 bytes, an X tile scanline) and 10 (every two X tile scanlines)
59 * are common to both the 915 and 965-class hardware.
60 *
61 * The CPU also sometimes XORs in higher bits as well, to improve
62 * bandwidth doing strided access like we do so frequently in graphics. This
63 * is called "Channel XOR Randomization" in the MCH documentation. The result
64 * is that the CPU is XORing in either bit 11 or bit 17 to bit 6 of its address
65 * decode.
66 *
67 * All of this bit 6 XORing has an effect on our memory management,
68 * as we need to make sure that the 3d driver can correctly address object
69 * contents.
70 *
71 * If we don't have interleaved memory, all tiling is safe and no swizzling is
72 * required.
73 *
74 * When bit 17 is XORed in, we simply refuse to tile at all. Bit
75 * 17 is not just a page offset, so as we page an objet out and back in,
76 * individual pages in it will have different bit 17 addresses, resulting in
77 * each 64 bytes being swapped with its neighbor!
78 *
79 * Otherwise, if interleaved, we have to tell the 3d driver what the address
80 * swizzling it needs to do is, since it's writing with the CPU to the pages
81 * (bit 6 and potentially bit 11 XORed in), and the GPU is reading from the
82 * pages (bit 6, 9, and 10 XORed in), resulting in a cumulative bit swizzling
83 * required by the CPU of XORing in bit 6, 9, 10, and potentially 11, in order
84 * to match what the GPU expects.
85 */
86
87 /**
88 * Detects bit 6 swizzling of address lookup between IGD access and CPU
89 * access through main memory.
90 */
91 void
i915_gem_detect_bit_6_swizzle(struct drm_device * dev)92 i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
93 {
94 drm_i915_private_t *dev_priv = dev->dev_private;
95 uint32_t swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
96 uint32_t swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
97
98 if (IS_VALLEYVIEW(dev)) {
99 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
100 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
101 } else if (INTEL_INFO(dev)->gen >= 6) {
102 uint32_t dimm_c0, dimm_c1;
103 dimm_c0 = I915_READ(MAD_DIMM_C0);
104 dimm_c1 = I915_READ(MAD_DIMM_C1);
105 dimm_c0 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
106 dimm_c1 &= MAD_DIMM_A_SIZE_MASK | MAD_DIMM_B_SIZE_MASK;
107 /* Enable swizzling when the channels are populated with
108 * identically sized dimms. We don't need to check the 3rd
109 * channel because no cpu with gpu attached ships in that
110 * configuration. Also, swizzling only makes sense for 2
111 * channels anyway. */
112 if (dimm_c0 == dimm_c1) {
113 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
114 swizzle_y = I915_BIT_6_SWIZZLE_9;
115 } else {
116 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
117 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
118 }
119 } else if (IS_GEN5(dev)) {
120 /* On IRONLAKE whatever DRAM config, GPU always do
121 * same swizzling setup.
122 */
123 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
124 swizzle_y = I915_BIT_6_SWIZZLE_9;
125 } else if (IS_GEN2(dev)) {
126 /* As far as we know, the 865 doesn't have these bit 6
127 * swizzling issues.
128 */
129 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
130 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
131 } else if (IS_MOBILE(dev) || (IS_GEN3(dev) && !IS_G33(dev))) {
132 uint32_t dcc;
133
134 /* On mobile 9xx chipsets, channel interleave by the CPU is
135 * determined by DCC. For single-channel, neither the CPU
136 * nor the GPU do swizzling. For dual channel interleaved,
137 * the GPU's interleave is bit 9 and 10 for X tiled, and bit
138 * 9 for Y tiled. The CPU's interleave is independent, and
139 * can be based on either bit 11 (haven't seen this yet) or
140 * bit 17 (common).
141 */
142 dcc = I915_READ(DCC);
143 switch (dcc & DCC_ADDRESSING_MODE_MASK) {
144 case DCC_ADDRESSING_MODE_SINGLE_CHANNEL:
145 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_ASYMMETRIC:
146 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
147 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
148 break;
149 case DCC_ADDRESSING_MODE_DUAL_CHANNEL_INTERLEAVED:
150 if (dcc & DCC_CHANNEL_XOR_DISABLE) {
151 /* This is the base swizzling by the GPU for
152 * tiled buffers.
153 */
154 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
155 swizzle_y = I915_BIT_6_SWIZZLE_9;
156 } else if ((dcc & DCC_CHANNEL_XOR_BIT_17) == 0) {
157 /* Work around: for fixing 965GM flickering issue on OpenArena */
158 swizzle_x = I915_BIT_6_SWIZZLE_9_10_11;
159 swizzle_y = I915_BIT_6_SWIZZLE_9_11;
160 } else {
161 /* Bit 17 swizzling by the CPU in addition. */
162 swizzle_x = I915_BIT_6_SWIZZLE_9_10_17;
163 swizzle_y = I915_BIT_6_SWIZZLE_9_17;
164 }
165 break;
166 }
167 if (dcc == 0xffffffff) {
168 DRM_ERROR("Couldn't read from MCHBAR. "
169 "Disabling tiling.\n");
170 swizzle_x = I915_BIT_6_SWIZZLE_UNKNOWN;
171 swizzle_y = I915_BIT_6_SWIZZLE_UNKNOWN;
172 }
173 } else {
174 /* The 965, G33, and newer, have a very flexible memory
175 * configuration. It will enable dual-channel mode
176 * (interleaving) on as much memory as it can, and the GPU
177 * will additionally sometimes enable different bit 6
178 * swizzling for tiled objects from the CPU.
179 *
180 * Here's what I found on the G965:
181 * slot fill memory size swizzling
182 * 0A 0B 1A 1B 1-ch 2-ch
183 * 512 0 0 0 512 0 O
184 * 512 0 512 0 16 1008 X
185 * 512 0 0 512 16 1008 X
186 * 0 512 0 512 16 1008 X
187 * 1024 1024 1024 0 2048 1024 O
188 *
189 * We could probably detect this based on either the DRB
190 * matching, which was the case for the swizzling required in
191 * the table above, or from the 1-ch value being less than
192 * the minimum size of a rank.
193 */
194 if (I915_READ16(C0DRB3) != I915_READ16(C1DRB3)) {
195 swizzle_x = I915_BIT_6_SWIZZLE_NONE;
196 swizzle_y = I915_BIT_6_SWIZZLE_NONE;
197 } else {
198 swizzle_x = I915_BIT_6_SWIZZLE_9_10;
199 swizzle_y = I915_BIT_6_SWIZZLE_9;
200 }
201 }
202
203 dev_priv->mm.bit_6_swizzle_x = swizzle_x;
204 dev_priv->mm.bit_6_swizzle_y = swizzle_y;
205 }
206
207 /* Check pitch constriants for all chips & tiling formats */
208 static bool
i915_tiling_ok(struct drm_device * dev,int stride,int size,int tiling_mode)209 i915_tiling_ok(struct drm_device *dev, int stride, int size, int tiling_mode)
210 {
211 int tile_width;
212
213 /* Linear is always fine */
214 if (tiling_mode == I915_TILING_NONE)
215 return true;
216
217 if (IS_GEN2(dev) ||
218 (tiling_mode == I915_TILING_Y && HAS_128_BYTE_Y_TILING(dev)))
219 tile_width = 128;
220 else
221 tile_width = 512;
222
223 /* check maximum stride & object size */
224 /* i965+ stores the end address of the gtt mapping in the fence
225 * reg, so dont bother to check the size */
226 if (INTEL_INFO(dev)->gen >= 7) {
227 if (stride / 128 > GEN7_FENCE_MAX_PITCH_VAL)
228 return false;
229 } else if (INTEL_INFO(dev)->gen >= 4) {
230 if (stride / 128 > I965_FENCE_MAX_PITCH_VAL)
231 return false;
232 } else {
233 if (stride > 8192)
234 return false;
235
236 if (IS_GEN3(dev)) {
237 if (size > I830_FENCE_MAX_SIZE_VAL << 20)
238 return false;
239 } else {
240 if (size > I830_FENCE_MAX_SIZE_VAL << 19)
241 return false;
242 }
243 }
244
245 if (stride < tile_width)
246 return false;
247
248 /* 965+ just needs multiples of tile width */
249 if (INTEL_INFO(dev)->gen >= 4) {
250 if (stride & (tile_width - 1))
251 return false;
252 return true;
253 }
254
255 /* Pre-965 needs power of two tile widths */
256 if (stride & (stride - 1))
257 return false;
258
259 return true;
260 }
261
262 /* Is the current GTT allocation valid for the change in tiling? */
263 static bool
i915_gem_object_fence_ok(struct drm_i915_gem_object * obj,int tiling_mode)264 i915_gem_object_fence_ok(struct drm_i915_gem_object *obj, int tiling_mode)
265 {
266 u32 size;
267
268 if (tiling_mode == I915_TILING_NONE)
269 return true;
270
271 if (INTEL_INFO(obj->base.dev)->gen >= 4)
272 return true;
273
274 if (INTEL_INFO(obj->base.dev)->gen == 3) {
275 if (obj->gtt_offset & ~I915_FENCE_START_MASK)
276 return false;
277 } else {
278 if (obj->gtt_offset & ~I830_FENCE_START_MASK)
279 return false;
280 }
281
282 size = i915_gem_get_gtt_size(obj->base.dev, obj->base.size, tiling_mode);
283 if (obj->gtt_space->size != size)
284 return false;
285
286 if (obj->gtt_offset & (size - 1))
287 return false;
288
289 return true;
290 }
291
292 /**
293 * Sets the tiling mode of an object, returning the required swizzling of
294 * bit 6 of addresses in the object.
295 */
296 int
297 /* LINTED */
i915_gem_set_tiling(DRM_IOCTL_ARGS)298 i915_gem_set_tiling(DRM_IOCTL_ARGS)
299 {
300 struct drm_i915_gem_set_tiling *args = data;
301 drm_i915_private_t *dev_priv = dev->dev_private;
302 struct drm_i915_gem_object *obj;
303 int ret = 0;
304
305 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
306 if (&obj->base == NULL)
307 return -ENOENT;
308
309 if (!i915_tiling_ok(dev,
310 args->stride, obj->base.size, args->tiling_mode)) {
311 drm_gem_object_unreference_unlocked(&obj->base);
312 return -EINVAL;
313 }
314
315 if (obj->pin_count) {
316 drm_gem_object_unreference_unlocked(&obj->base);
317 return -EBUSY;
318 }
319
320 if (args->tiling_mode == I915_TILING_NONE) {
321 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
322 args->stride = 0;
323 } else {
324 if (args->tiling_mode == I915_TILING_X)
325 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
326 else
327 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
328
329 /* Hide bit 17 swizzling from the user. This prevents old Mesa
330 * from aborting the application on sw fallbacks to bit 17,
331 * and we use the pread/pwrite bit17 paths to swizzle for it.
332 * If there was a user that was relying on the swizzle
333 * information for drm_intel_bo_map()ed reads/writes this would
334 * break it, but we don't have any of those.
335 */
336 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
337 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
338 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
339 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
340
341 /* If we can't handle the swizzling, make it untiled. */
342 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_UNKNOWN) {
343 args->tiling_mode = I915_TILING_NONE;
344 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
345 args->stride = 0;
346 }
347 }
348
349 mutex_lock(&dev->struct_mutex);
350 if (args->tiling_mode != obj->tiling_mode ||
351 args->stride != obj->stride) {
352 /* We need to rebind the object if its current allocation
353 * no longer meets the alignment restrictions for its new
354 * tiling mode. Otherwise we can just leave it alone, but
355 * need to ensure that any fence register is cleared.
356 * the next fenced (either through the GTT or by the BLT unit
357 * on older GPUs) access.
358 *
359 * After updating the tiling parameters, we then flag whether
360 * we need to update an associated fence register. Note this
361 * has to also include the unfenced register the GPU uses
362 * whilst executing a fenced command for an untiled object.
363 */
364
365 obj->map_and_fenceable =
366 obj->gtt_space == NULL ||
367 (obj->gtt_offset + obj->base.size <= dev_priv->gtt.mappable_end &&
368 i915_gem_object_fence_ok(obj, args->tiling_mode));
369
370 /* Rebind if we need a change of alignment */
371 if (!obj->map_and_fenceable) {
372 u32 unfenced_alignment =
373 i915_gem_get_gtt_alignment(dev, obj->base.size,
374 args->tiling_mode,
375 false);
376 if (obj->gtt_offset & (unfenced_alignment - 1))
377 ret = i915_gem_object_unbind(obj, 1);
378 }
379
380 if (ret == 0) {
381 obj->fence_dirty =
382 obj->fenced_gpu_access ||
383 obj->fence_reg != I915_FENCE_REG_NONE;
384
385 obj->tiling_mode = args->tiling_mode;
386 obj->stride = args->stride;
387
388 /* Force the fence to be reacquired for GTT access */
389 i915_gem_release_mmap(obj);
390 }
391 }
392 /* we have to maintain this existing ABI... */
393 args->stride = obj->stride;
394 args->tiling_mode = obj->tiling_mode;
395
396 /* Try to preallocate memory required to save swizzling on put-pages */
397 if (i915_gem_object_needs_bit17_swizzle(obj)) {
398 if (obj->bit_17 == NULL) {
399 obj->bit_17 = kmalloc(BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT) *
400 sizeof(long), GFP_KERNEL);
401 }
402 } else {
403 if (obj->bit_17 != NULL) {
404 kfree(obj->bit_17, BITS_TO_LONGS(obj->base.size >> PAGE_SHIFT) *
405 sizeof(long));
406 obj->bit_17 = NULL;
407 }
408 }
409
410 drm_gem_object_unreference(&obj->base);
411 mutex_unlock(&dev->struct_mutex);
412
413 return ret;
414 }
415
416 /**
417 * Returns the current tiling mode and required bit 6 swizzling for the object.
418 */
419 int
420 /* LINTED */
i915_gem_get_tiling(DRM_IOCTL_ARGS)421 i915_gem_get_tiling(DRM_IOCTL_ARGS)
422 {
423 struct drm_i915_gem_get_tiling *args = data;
424 drm_i915_private_t *dev_priv = dev->dev_private;
425 struct drm_i915_gem_object *obj;
426
427 obj = to_intel_bo(drm_gem_object_lookup(dev, file, args->handle));
428 if (&obj->base == NULL)
429 return -ENOENT;
430
431 mutex_lock(&dev->struct_mutex);
432
433 args->tiling_mode = obj->tiling_mode;
434 switch (obj->tiling_mode) {
435 case I915_TILING_X:
436 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_x;
437 break;
438 case I915_TILING_Y:
439 args->swizzle_mode = dev_priv->mm.bit_6_swizzle_y;
440 break;
441 case I915_TILING_NONE:
442 args->swizzle_mode = I915_BIT_6_SWIZZLE_NONE;
443 break;
444 default:
445 DRM_ERROR("unknown tiling mode\n");
446 }
447
448 /* Hide bit 17 from the user -- see comment in i915_gem_set_tiling */
449 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_17)
450 args->swizzle_mode = I915_BIT_6_SWIZZLE_9;
451 if (args->swizzle_mode == I915_BIT_6_SWIZZLE_9_10_17)
452 args->swizzle_mode = I915_BIT_6_SWIZZLE_9_10;
453
454 drm_gem_object_unreference(&obj->base);
455 mutex_unlock(&dev->struct_mutex);
456
457 return 0;
458 }
459
460 /**
461 * Swap every 64 bytes of this page around, to account for it having a new
462 * bit 17 of its physical address and therefore being interpreted differently
463 * by the GPU.
464 */
465 static void
i915_gem_swizzle_page(caddr_t va)466 i915_gem_swizzle_page(caddr_t va)
467 {
468 char temp[64];
469 char *vaddr;
470 int i;
471
472 vaddr = (char *)(uintptr_t) va;
473
474 for (i = 0; i < PAGE_SIZE; i += 128) {
475 (void) memcpy(temp, &vaddr[i], 64);
476 (void) memcpy(&vaddr[i], &vaddr[i + 64], 64);
477 (void) memcpy(&vaddr[i + 64], temp, 64);
478 }
479
480 }
481
482 void
i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object * obj)483 i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj)
484 {
485 int page_count = obj->base.size >> PAGE_SHIFT;
486 int i;
487
488 if (obj->bit_17 == NULL)
489 return;
490
491 for (i = 0; i < page_count; i++) {
492 char new_bit_17 = (char)(page_to_phys(obj->page_list[i]) >> 17);
493 if ((new_bit_17 & 0x1) !=
494 (test_bit(i, obj->bit_17) != 0)) {
495 i915_gem_swizzle_page(obj->page_list[i]);
496 }
497 }
498 }
499
500 void
i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object * obj)501 i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj)
502 {
503 int page_count = obj->base.size >> PAGE_SHIFT;
504 int i;
505
506 if (obj->bit_17 == NULL) {
507 obj->bit_17 = kmalloc(BITS_TO_LONGS(page_count) *
508 sizeof(long), GFP_KERNEL);
509 if (obj->bit_17 == NULL) {
510 DRM_ERROR("Failed to allocate memory for bit 17 "
511 "record\n");
512 return;
513 }
514 }
515
516 for (i = 0; i < page_count; i++) {
517 if (page_to_phys(obj->page_list[i]) & (1 << 17))
518 set_bit(i, obj->bit_17);
519 else
520 clear_bit(i, obj->bit_17);
521 }
522 }
523