1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_SYS_SCSI_ADAPTERS_FASVAR_H
28 #define	_SYS_SCSI_ADAPTERS_FASVAR_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 /*
33  * QLogic FAS (Enhanced	Scsi Processor)	Definitions,
34  * Software && Hardware.
35  */
36 
37 #ifdef	__cplusplus
38 extern "C" {
39 #endif
40 
41 #include <sys/note.h>
42 
43 /*
44  * Compile options
45  */
46 #if DEBUG
47 #define	FASDEBUG		/* turn	on debugging code */
48 #define	FASTEST
49 #endif /* DEBUG	*/
50 
51 /*
52  * Software Definitions
53  */
54 #define	POLL_TIMEOUT		(2 * SCSI_POLL_TIMEOUT * 1000000)
55 #define	SHORT_POLL_TIMEOUT	(1000000) /* in	usec, about 1 secs */
56 #define	FAS_MUTEX(fas)		(&(fas)->f_mutex)
57 #define	FAS_CV(fas)		(&(fas)->f_cv)
58 #define	FAS_INITIAL_SOFT_SPACE	4	/* Used	for the	softstate_init func */
59 #define	FAS_QUIESCE_TIMEOUT	1	/* 1 sec */
60 
61 /*
62  * Data	Structure for this Host	Adapter.
63  *
64  * structure to	hold active outstanding	cmds
65  */
66 struct f_slots {
67 	ushort_t		f_dups;
68 	ushort_t		f_tags;
69 	int			f_timeout;
70 	int			f_timebase;
71 				/* t_slot size is 1 for	non-tagged, and	*/
72 				/* 256 for tagged targets		*/
73 	ushort_t		f_n_slots; /* number of	a_slots		*/
74 	ushort_t		f_size;
75 	struct fas_cmd		*f_slot[1];	/* may be for 256 for TQ */
76 };
77 
78 #define	FAS_F_SLOTS_SIZE_TQ	(sizeof	(struct	f_slots) + \
79 			(sizeof	(struct	fas_cmd	*) * (NTAGS -1)))
80 #define	FAS_F_SLOT_SIZE		(sizeof	(struct	f_slots))
81 
82 /*
83  * HBA interface macros
84  */
85 #define	SDEV2TRAN(sd)		((sd)->sd_address.a_hba_tran)
86 #define	SDEV2ADDR(sd)		(&((sd)->sd_address))
87 #define	PKT2TRAN(pkt)		((pkt)->pkt_address.a_hba_tran)
88 #define	ADDR2TRAN(ap)		((ap)->a_hba_tran)
89 
90 #define	TRAN2FAS(tran)		((struct fas *)(tran)->tran_hba_private)
91 #define	SDEV2FAS(sd)		(TRAN2FAS(SDEV2TRAN(sd)))
92 #define	PKT2FAS(pkt)		(TRAN2FAS(PKT2TRAN(pkt)))
93 #define	ADDR2FAS(ap)		(TRAN2FAS(ADDR2TRAN(ap)))
94 
95 
96 /*
97  * soft	state information for this host	adapter
98  */
99 #define	N_SLOTS			(NTARGETS_WIDE*NLUNS_PER_TARGET)
100 #define	REG_TRACE_BUF_SIZE	1024
101 
102 struct fas {
103 	int		f_instance;
104 	/*
105 	 * Transport structure for this	instance of the	hba
106 	 */
107 	scsi_hba_tran_t	*f_tran;
108 
109 	/*
110 	 * dev_info_t reference
111 	 */
112 	dev_info_t	*f_dev;
113 
114 	/*
115 	 * mutex to protect softstate and hw regs
116 	 */
117 	kmutex_t	f_mutex;
118 
119 	/*
120 	 * Interrupt block cookie
121 	 */
122 	ddi_iblock_cookie_t	f_iblock;
123 
124 	/*
125 	 * Next	in a linked list of host adapters
126 	 */
127 	struct fas	*f_next;
128 
129 	/*
130 	 * Type	byte for this host adapter
131 	 * and rev of the FEPS chip
132 	 */
133 	uchar_t		f_type;
134 	uchar_t		f_hm_rev;
135 
136 	/*
137 	 * value for configuration register 1.
138 	 * Also	contains Initiator Id.
139 	 */
140 	uint8_t		f_fasconf;
141 
142 	/*
143 	 * value for configuration register 2
144 	 */
145 	uint8_t		f_fasconf2;
146 
147 	/*
148 	 * value for configuration register 3
149 	 */
150 	uint8_t		f_fasconf3[NTARGETS_WIDE];
151 	uint8_t		f_fasconf3_reg_last;
152 
153 	/*
154 	 * clock conversion register value for this host adapter.
155 	 * clock cycle value * 1000 for	this host adapter,
156 	 * to retain 5 significant digits.
157 	 */
158 	uchar_t		f_clock_conv;
159 	ushort_t	f_clock_cycle;
160 
161 	/*
162 	 * selection timeout register value
163 	 */
164 	uint8_t		f_stval;
165 
166 	/*
167 	 * State of the	host adapter
168 	 */
169 	uchar_t	f_sdtr_sent;	/* Count of sync data negotiation messages: */
170 				/* zeroed for every selection attempt, */
171 				/* every reconnection, and every disconnect */
172 				/* interrupt. Each SYNCHRONOUS DATA TRANSFER */
173 				/* message, both coming	from the target, and */
174 				/* sent	to the target, causes this tag to be */
175 				/* incremented.	This allows the	received */
176 				/* message handling to determine whether */
177 				/* a received SYNCHRONOUS DATA TRANSFER	*/
178 				/* message is in response to one that we */
179 				/* sent. */
180 	uchar_t	f_wdtr_sent;	/* same	for wide negotations */
181 	uchar_t	f_stat;		/* soft	copy of	status register	*/
182 	uchar_t	f_stat2;	/* soft	copy of	status2	register */
183 	uchar_t	f_intr;		/* soft	copy of	interrupt register */
184 	uchar_t	f_step;		/* soft	copy of	step register */
185 	uchar_t	f_abort_msg_sent; /* indicates that abort message went out */
186 	uchar_t	f_reset_msg_sent; /* indicates that device reset message */
187 				/* went	out */
188 	uchar_t	f_last_cmd;	/* last	cmd sent to fas	chip */
189 
190 	ushort_t f_state;	/* state of the	driver */
191 	ushort_t f_laststate;	/* last	state of the driver */
192 	uchar_t	f_suspended;	/* true	if driver is suspended */
193 	uchar_t	f_dslot;	/* delta to next slot */
194 	uchar_t	f_idcode;	/* chips idcode	*/
195 	uchar_t	f_polled_intr;	/* current interrupt was polled. */
196 
197 	/*
198 	 * Message handling: enough space is reserved for the expected length
199 	 * of all messages we could either send	or receive.
200 	 *
201 	 * For sending,	we expect to send only SYNCHRONOUS extended messages
202 	 * (5 bytes). We keep a	history	of the last message sent, and in order
203 	 * to control which message to send, an	output message length is set
204 	 * to indicate whether and how much of the message area	is to be used
205 	 * in sending a	message. If a target shifts to message out phase
206 	 * unexpectedly, the default action will be to send a MSG_NOP message.
207 	 *
208 	 * After the successful	transmission of	a message, the initial message
209 	 * byte	is moved to the	f_last_msgout area for tracking	what was the
210 	 * last	message	sent.
211 	 */
212 
213 #define	OMSGSIZE	12
214 	uchar_t		f_cur_msgout[OMSGSIZE];
215 	uchar_t		f_last_msgout;
216 	uchar_t		f_omsglen;
217 
218 
219 	/*
220 	 * We expect, at, most,	to receive a maximum of	7 bytes
221 	 * of an incoming extended message (MODIFY DATA	POINTER),
222 	 * and thus reserve enough space for that.
223 	 */
224 #define	IMSGSIZE	8
225 	uchar_t		f_imsgarea[IMSGSIZE];
226 
227 	/*
228 	 * These are used to index how far we've
229 	 * gone	in receiving incoming  messages.
230 	 */
231 	uchar_t		f_imsglen;
232 	uchar_t		f_imsgindex;
233 
234 	/*
235 	 * Saved last msgin.
236 	 */
237 	uchar_t		f_last_msgin;
238 
239 	/*
240 	 * round robin scheduling of requests in fas_ustart()
241 	 */
242 	uchar_t		f_next_slot;
243 
244 	/*
245 	 * save	reselecting slot when waiting for tag bytes
246 	 */
247 	uchar_t		f_resel_slot;
248 
249 	/*
250 	 * Target information
251 	 *	Synchronous SCSI Information,
252 	 *	Disconnect/reconnect capabilities
253 	 *	Noise Susceptibility
254 	 */
255 	uchar_t	f_offset[NTARGETS_WIDE]; /* synch offset + req-ack delay */
256 	uchar_t	f_sync_period[NTARGETS_WIDE]; /* synch period reg val */
257 	uchar_t	f_neg_period[NTARGETS_WIDE]; /*	synch periods (negotiated) */
258 	ushort_t f_backoff;		/* sync/wide backoff bit mask */
259 	uchar_t	f_req_ack_delay;	/* req ack delay in offset reg */
260 	uchar_t	f_offset_reg_last;	/* save	last offset value */
261 	uchar_t	f_period_reg_last;	/* save	last period value */
262 
263 	/*
264 	 * fifo	length and fifo	contents stored	here before reading intr reg
265 	 */
266 	uchar_t		f_fifolen;
267 	uchar_t		f_fifo[2*FIFOSIZE];
268 
269 	/*
270 	 * These ushort_t's are  bit maps	for targets
271 	 */
272 	ushort_t	f_wide_known;	/* wide	negotiate on	next cmd */
273 	ushort_t	f_nowide;	/* no wide for this target */
274 	ushort_t	f_wide_enabled;	/* wide	enabled	for this target	*/
275 
276 	ushort_t	f_sync_known;	/* sync	negotiate on next cmd */
277 	ushort_t	f_nosync;	/* no sync for this target */
278 	ushort_t	f_sync_enabled;	/* sync	enabled	for this target	*/
279 
280 	/*
281 	 * This ushort_t is a bit map for targets to
282 	 * disable sync on request from the target driver
283 	 */
284 	ushort_t	f_force_async;
285 	ushort_t	f_force_narrow;
286 
287 	/*
288 	 * This	ushort_t is a bit map for targets who don't appear
289 	 * to be able to support tagged	commands.
290 	 */
291 	ushort_t	f_notag;
292 
293 	/*
294 	 * This ushort_t is a bit map for targets who need to have
295 	 * their properties update deferred.
296 	 */
297 	ushort_t	f_props_update;
298 
299 	/*
300 	 * scsi_options	for bus	and per	target
301 	 */
302 	int		f_target_scsi_options_defined;
303 	int		f_scsi_options;
304 	int		f_target_scsi_options[NTARGETS_WIDE];
305 
306 	/*
307 	 * tag age limit per bus
308 	 */
309 	int		f_scsi_tag_age_limit;
310 
311 	/*
312 	 * scsi	reset delay per	bus
313 	 */
314 	uint_t		f_scsi_reset_delay;
315 
316 	/*
317 	 * Scratch Buffer, allocated out of iopbmap for	commands
318 	 * The same size as the	FAS's fifo.
319 	 */
320 	uchar_t		*f_cmdarea;
321 
322 	/*
323 	 * shadow copy of dma_csr to avoid unnecessary I/O reads which are
324 	 * expensive
325 	 */
326 	uint32_t	f_dma_csr;
327 
328 	/*
329 	 * Scratch Buffer DMA cookie and handle	for cmdarea
330 	 */
331 	ddi_dma_cookie_t	f_dmacookie;
332 	ddi_dma_handle_t	f_dmahandle;
333 
334 	/*
335 	 * dma attrs for fas scsi engine
336 	 */
337 	ddi_dma_attr_t		*f_dma_attr;
338 
339 	/*
340 	 * critical counters
341 	 */
342 	short	f_ncmds;	/* number of commands stored here at present */
343 	short	f_ndisc;	/* number of disconnected cmds at present */
344 
345 	/*
346 	 * Hardware pointers
347 	 *
348 	 * Pointer to mapped in	FAS registers
349 	 */
350 	volatile struct	fasreg *f_reg;
351 
352 	/*
353 	 * Pointer to mapped in	DMA Gate Array registers
354 	 */
355 
356 	volatile struct	dma    *f_dma;
357 
358 	/*
359 	 * last	and current state, queues
360 	 */
361 	uint32_t		f_lastdma;	/* last	dma address */
362 	uint32_t		f_lastcount;	/* last	dma count */
363 
364 	struct fas_cmd		*f_current_sp;	/* currently active cmd	*/
365 	struct f_slots		*f_active[N_SLOTS]; /* outstanding cmds	*/
366 
367 	struct fas_cmd		*f_readyf[N_SLOTS]; /* waiting cmds */
368 	struct fas_cmd		*f_readyb[N_SLOTS];
369 
370 				/*
371 				 * if throttle >= 0 then
372 				 * continue submitting cmds
373 				 * if throttle == 0 then hold cmds
374 				 * if throttle == -1 then drain
375 				 * if throttle == -2 do special handling
376 				 * for queue full
377 				 * f_throttle and f_tcmds are not part of
378 				 * f_active so fas_ustart() can	walk thru
379 				 * these more efficiently
380 				 */
381 	short			f_throttle[N_SLOTS];
382 
383 				/*
384 				 * number of disconnected + active commands
385 				 * (i.e. stored in the f_active list) for
386 				 * the slot
387 				 */
388 	short			f_tcmds[N_SLOTS];
389 
390 				/*
391 				 * if a	device reset has been performed, a
392 				 * delay is required before accessing the target
393 				 * again; reset	delays are in milli secs
394 				 * (assuming that reset	watchdog runs every
395 				 * scsi-watchdog-tick  milli secs;
396 				 * the watchdog	decrements the reset delay)
397 				 */
398 	int			f_reset_delay[NTARGETS_WIDE];
399 
400 	/*
401 	 * list	for auto request sense packets
402 	 */
403 	struct fas_cmd		*f_arq_pkt[N_SLOTS];
404 
405 	/*
406 	 * queue of packets that need callback and other callback info
407 	 */
408 	struct fas_cmd		*f_c_qf;
409 	struct fas_cmd		*f_c_qb;
410 	kmutex_t		f_c_mutex;
411 	int			f_c_in_callback;
412 
413 	/*
414 	 * a queue for packets in case the fas mutex is	locked
415 	 */
416 	kmutex_t		f_waitQ_mutex;
417 	struct fas_cmd		*f_waitf;
418 	struct fas_cmd		*f_waitb;
419 
420 	/*
421 	 * list	of reset notification requests
422 	 */
423 	struct scsi_reset_notify_entry	 *f_reset_notify_listf;
424 
425 	/*
426 	 * qfull handling
427 	 */
428 	uchar_t			f_qfull_retries[NTARGETS_WIDE];
429 	ushort_t		f_qfull_retry_interval[NTARGETS_WIDE];
430 	timeout_id_t		f_restart_cmd_timeid;
431 
432 	/*
433 	 * kmem	cache for packets
434 	 */
435 	struct kmem_cache	*f_kmem_cache;
436 
437 	/*
438 	 * data access handle for register mapping
439 	 */
440 	ddi_acc_handle_t	f_regs_acc_handle;
441 	/*
442 	 * data access handle for cmd area
443 	 */
444 	ddi_acc_handle_t	f_cmdarea_acc_handle;
445 	/*
446 	 * data access handle for dma
447 	 */
448 	ddi_acc_handle_t	f_dmar_acc_handle;
449 
450 	/*
451 	 * state flags
452 	 */
453 	uint_t			f_flags;
454 
455 	/*
456 	 * cv for bus quiesce/unquiesce
457 	 */
458 	kcondvar_t		f_cv;
459 
460 	/*
461 	 * soft state flags
462 	 */
463 	uint_t			f_softstate;
464 
465 	/*
466 	 * quiesce timeout ID
467 	 */
468 	timeout_id_t		f_quiesce_timeid;
469 
470 	/*
471 	 * kstat_intr support
472 	 */
473 	struct kstat		*f_intr_kstat;
474 
475 #ifdef FASDEBUG
476 	/*
477 	 * register trace for debugging
478 	 */
479 	uint_t			f_reg_trace_index;
480 	uint_t			f_reg_trace[REG_TRACE_BUF_SIZE+1];
481 
482 	uint_t			f_reserved[256];
483 
484 	uint_t			f_reg_reads;
485 	uint_t			f_reg_dma_reads;
486 	uint_t			f_reg_writes;
487 	uint_t			f_reg_dma_writes;
488 	uint_t			f_reg_cmds;
489 	uint_t			f_total_cmds;
490 #endif
491 };
492 _NOTE(MUTEX_PROTECTS_DATA(fas::f_mutex,	fas))
493 _NOTE(MUTEX_PROTECTS_DATA(fas::f_waitQ_mutex, fas::f_waitf fas::f_waitb))
494 _NOTE(MUTEX_PROTECTS_DATA(fas::f_c_mutex, fas::f_c_qf fas::f_c_qb
495 	fas::f_c_in_callback))
496 _NOTE(DATA_READABLE_WITHOUT_LOCK(fas::f_flags))
497 
498 _NOTE(SCHEME_PROTECTS_DATA("unique per packet or safe sharing",
499     scsi_cdb scsi_status scsi_pkt buf))
500 _NOTE(SCHEME_PROTECTS_DATA("stable data", scsi_device scsi_address))
501 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", fas::f_next fas::f_state))
502 _NOTE(SCHEME_PROTECTS_DATA("safe sharing",
503 	fas::f_dma fas::f_dma_attr fas::f_hm_rev))
504 _NOTE(SCHEME_PROTECTS_DATA("stable data",
505 	fas::f_target_scsi_options fas::f_scsi_options))
506 _NOTE(SCHEME_PROTECTS_DATA("stable data", fas::f_instance))
507 _NOTE(SCHEME_PROTECTS_DATA("only debugging",
508 	fas::f_reg_trace_index fas::f_reg_trace))
509 _NOTE(SCHEME_PROTECTS_DATA("protected by kmem lock", fas::f_kmem_cache))
510 _NOTE(SCHEME_PROTECTS_DATA("safe sharing",
511 	fas::f_notag fas::f_suspended fas::f_ndisc))
512 _NOTE(SCHEME_PROTECTS_DATA("stable data", fas::f_dev fas::f_tran))
513 _NOTE(SCHEME_PROTECTS_DATA("only debugging", fas::f_reg_dma_reads))
514 _NOTE(SCHEME_PROTECTS_DATA("safe sharing", fas::f_quiesce_timeid))
515 
516 /*
517  * kstat_intr support
518  */
519 
520 #define	FAS_KSTAT_INTR(fas)  KSTAT_INTR_PTR(fas->f_intr_kstat)->\
521 					intrs[KSTAT_INTR_HARD]++
522 
523 /*
524  * defaults for	the global properties
525  */
526 #define	DEFAULT_SCSI_OPTIONS	SCSI_OPTIONS_DR
527 #define	DEFAULT_TAG_AGE_LIMIT	2
528 #define	DEFAULT_WD_TICK		10
529 
530 /*
531  * define for f_flags
532  */
533 #define	FAS_FLG_NOTIMEOUTS	0x0001	/* disallow timeout rescheduling */
534 
535 #define	FAS_CAN_SCHED	((fas->f_flags & FAS_FLG_NOTIMEOUTS) == 0)
536 
537 /*
538  * f_req_ack_delay:
539  */
540 #define	DEFAULT_REQ_ACK_DELAY	0x50	/* delay assert	period by 1/2 cycle */
541 
542 /*
543  * Representations of Driver states (stored in tags f_state && f_laststate).
544  *
545  * Totally idle. There may or may not disconnected commands still
546  * running on targets.
547  */
548 #define	STATE_FREE	0x00
549 
550 /*
551  * Selecting States. These states represent a selection	attempt
552  * for a target.
553  */
554 #define	STATE_SELECT_NORMAL	0x0100
555 #define	STATE_SELECT_N_STOP	0x0200
556 #define	STATE_SELECT_N_SENDMSG	0x0400
557 #define	STATE_SYNC_ASKING	0x0800
558 #define	STATE_SELECT_N_TAG	0x1000
559 #define	STATE_SELECTING		0xFF00	/* Select mask */
560 
561 
562 /*
563  * When	the driver is neither idle nor selecting, it is	in one of
564  * the information transfer phases. These states are not unique
565  * bit patterns- they are simple numbers used to mark transitions.
566  * They	must start at 1	and proceed sequentially upwards and
567  * match the indexing of function vectors declared in the function
568  * fas_phasemanage().
569  */
570 #define	STATE_ITPHASES		0x00FF	/* Phase mask */
571 
572 /*
573  * These states	cover finishing	sending	a command out (if it wasn't
574  * sent	as a side-effect of selecting),	or the case of starting
575  * a command that was linked to	the previous command (i.e., no
576  * selection phase for this particular command as the target
577  * remained connected when the previous	command	completed).
578  */
579 #define	ACTS_CMD_START		0x01
580 #define	ACTS_CMD_DONE		0x02
581 
582 /*
583  * These states	are the	begin and end of sending out a message.
584  * The message to be sent is stored in the field f_msgout (see above).
585  */
586 #define	ACTS_MSG_OUT		0x03
587 #define	ACTS_MSG_OUT_DONE	0x04
588 
589 /*
590  * These states	are the	beginning, middle, and end of incoming messages.
591  *
592  */
593 #define	ACTS_MSG_IN		0x05
594 #define	ACTS_MSG_IN_MORE	0x06
595 #define	ACTS_MSG_IN_DONE	0x07
596 
597 /*
598  * This	state is reached when the target may be	getting
599  * ready to clear the bus (disconnect or command complete).
600  */
601 #define	ACTS_CLEARING		0x08
602 
603 /*
604  * These states	elide the begin	and end	of a DATA phase
605  */
606 #define	ACTS_DATA		0x09
607 #define	ACTS_DATA_DONE		0x0A
608 
609 /*
610  * This	state indicates	that we	were in	status phase. We handle	status
611  * phase by issuing the	FAS command 'CMD_COMP_SEQ' which causes	the
612  * FAS to read the status byte,	and then to read a message in (presumably
613  * one of COMMAND COMPLETE, LINKED COMMAND COMPLETE or LINKED COMMAND
614  * COMPLETE WITH FLAG).
615  *
616  * This	state is what is expected to follow after the issuance of the
617  * FAS command 'CMD_COMP_SEQ'.
618  */
619 #define	ACTS_C_CMPLT		0x0B
620 
621 /*
622  * This	state is used by the driver to indicate	that it
623  * is in the middle of processing a reselection	attempt.
624  */
625 #define	ACTS_RESEL		0x0C
626 
627 /*
628  * This	state is used by the driver to indicate	that it	doesn't	know
629  * what	the next state is, and that it should look at the FAS's	status
630  * register to find out	what SCSI bus phase we are in in order to select
631  * the next state to transition	to.
632  */
633 #define	ACTS_UNKNOWN		0x0D
634 
635 /*
636  * This	state is used by the driver to indicate	that a self-inititated
637  * Bus reset is	in progress.
638  */
639 #define	ACTS_RESET		0x0E
640 
641 /*
642  * Hiwater mark	of vectored states
643  */
644 #define	ACTS_ENDVEC		0x0E
645 
646 /*
647  * XXX - needs to distinguish between bus states and internal states
648  */
649 
650 /*
651  * This	state is used by the driver to indicate	to itself that it is
652  * in the middle of aborting things.
653  */
654 #define	ACTS_ABORTING		0x1D
655 
656 /*
657  * This	state is used by the driver to just hold the state of
658  * the softc structure while it	is either aborting or resetting
659  * everything.
660  */
661 #define	ACTS_FROZEN		0x1F
662 
663 
664 /*
665  * Interrupt dispatch actions
666  */
667 #define	ACTION_RETURN		-1	/* return from interrupt */
668 #define	ACTION_FINSEL		0x00	/* finish selection */
669 #define	ACTION_RESEL		0x01	/* handle reselection */
670 #define	ACTION_PHASEMANAGE	0x02	/* manage phases */
671 #define	ACTION_FINISH		0x03	/* this	command	done */
672 #define	ACTION_FINRST		0x04	/* finish reset	recovery */
673 #define	ACTION_SEARCH		0x05	/* search for new command to start */
674 #define	ACTION_ABORT_CURCMD	0x06	/* abort current command */
675 #define	ACTION_ABORT_ALLCMDS	0x07	/* abort all commands */
676 #define	ACTION_RESET		0x08	/* reset bus */
677 #define	ACTION_SELECT		0x09	/* handle selection */
678 
679 /*
680  * Proxy command definitions.
681  *
682  * At certain times, we	need to	run a proxy command for	a target
683  * (if only to select a	target and send	a message).
684  *
685  * We use the tail end of the cdb that is internal to the fas_cmd
686  * structure to	store the proxy	code, the proxy	data (e.g., the
687  * message to send).
688  *
689  * We also store a boolean result code in this area so that the
690  * user	of a proxy command knows whether it succeeded.
691  */
692 
693 /*
694  * Offsets into	the cmd_cdb[] array (in fas_cmd) for proxy data
695  */
696 #define	FAS_PROXY_TYPE		CDB_GROUP0
697 #define	FAS_PROXY_RESULT	FAS_PROXY_TYPE+1
698 #define	FAS_PROXY_DATA		FAS_PROXY_RESULT+1
699 
700 /*
701  * Currently supported proxy types
702  */
703 
704 #define	FAS_PROXY_SNDMSG	1
705 
706 /*
707  * Reset actions
708  */
709 #define	FAS_RESET_FAS		0x1	/* reset FAS chip */
710 #define	FAS_RESET_DMA		0x2	/* reset DMA gate array	*/
711 #define	FAS_RESET_BRESET	0x4	/* reset SCSI bus */
712 #define	FAS_RESET_IGNORE_BRESET	0x8	/* ignore SCSI Bus RESET interrupt */
713 					/* while resetting bus.	*/
714 #define	FAS_RESET_SCSIBUS	(FAS_RESET_BRESET|FAS_RESET_IGNORE_BRESET)
715 #define	FAS_RESET_SOFTC		0x10	/* reset SOFTC structure */
716 
717 #define	FAS_RESET_HW		(FAS_RESET_FAS|FAS_RESET_DMA|FAS_RESET_SCSIBUS)
718 #define	FAS_RESET_ALL		(FAS_RESET_HW|FAS_RESET_SOFTC)
719 
720 #define	FAS_RESET_MSG		0x20
721 
722 #define	FAS_RESET_SPIN_DELAY_USEC	20
723 #define	FAS_RESET_SPIN_MAX_LOOP		1000
724 
725 /*
726  * f_softstate flags
727  */
728 #define	FAS_SS_DRAINING		0x02
729 #define	FAS_SS_QUIESCED		0x04
730 
731 /*
732  * Debugging macros and	defines
733  */
734 #ifdef	FASDEBUG
735 /*PRINTFLIKE2*/
736 extern void fas_dprintf(struct fas *fas, const char *fmt, ...)
737 	__KPRINTFLIKE(2);
738 
739 #define	INFORMATIVE	(fasdebug)
740 #define	IDEBUGGING	((fasdebug) && \
741 			((fas->f_instance == fasdebug_instance)	|| \
742 			(fasdebug_instance == -1)))
743 #define	DDEBUGGING	((fasdebug > 1)	&& \
744 			((fas->f_instance == fasdebug_instance)	|| \
745 			(fasdebug_instance == -1)))
746 
747 #define	EDEBUGGING	((fasdebug > 2)	&& \
748 			((fas->f_instance == fasdebug_instance)	|| \
749 			(fasdebug_instance == -1)))
750 
751 #define	EPRINTF(str)		if (EDEBUGGING)	fas_dprintf(fas, str)
752 #define	EPRINTF1(str, a)	if (EDEBUGGING)	fas_dprintf(fas, str, a)
753 #define	EPRINTF2(str, a, b)	if (EDEBUGGING)	fas_dprintf(fas, str, a, b)
754 #define	EPRINTF3(str, a, b, c)	if (EDEBUGGING)	fas_dprintf(fas, str, a, b, c)
755 #define	EPRINTF4(str, a, b, c, d)	\
756 	if (EDEBUGGING)	fas_dprintf(fas, str, a, b, c, d)
757 #define	EPRINTF5(str, a, b, c, d, e)	\
758 	if (EDEBUGGING)	fas_dprintf(fas, str, a, b, c, d, e)
759 #define	EPRINTF6(str, a, b, c, d, e, f)	\
760 	if (EDEBUGGING)	fas_dprintf(fas, str, a, b, c, d, e, f)
761 
762 #define	DPRINTF(str)		if (DDEBUGGING)	fas_dprintf(fas, str)
763 #define	DPRINTF1(str, a)	if (DDEBUGGING)	fas_dprintf(fas, str, a)
764 #define	DPRINTF2(str, a, b)	if (DDEBUGGING)	fas_dprintf(fas, str, a, b)
765 #define	DPRINTF3(str, a, b, c)	if (DDEBUGGING)	fas_dprintf(fas, str, a, b, c)
766 #define	DPRINTF4(str, a, b, c, d)	\
767 	if (DDEBUGGING)	fas_dprintf(fas, str, a, b, c, d)
768 #define	DPRINTF5(str, a, b, c, d, e)	\
769 	if (DDEBUGGING)	fas_dprintf(fas, str, a, b, c, d, e)
770 #define	DPRINTF6(str, a, b, c, d, e, f)	\
771 	if (DDEBUGGING)	fas_dprintf(fas, str, a, b, c, d, e, f)
772 
773 #define	IPRINTF(str)		if (IDEBUGGING)	fas_dprintf(fas, str)
774 #define	IPRINTF1(str, a)	if (IDEBUGGING)	fas_dprintf(fas, str, a)
775 #define	IPRINTF2(str, a, b)	if (IDEBUGGING)	fas_dprintf(fas, str, a, b)
776 #define	IPRINTF3(str, a, b, c)	if (IDEBUGGING)	fas_dprintf(fas, str, a, b, c)
777 #define	IPRINTF4(str, a, b, c, d)	\
778 	if (IDEBUGGING)	fas_dprintf(fas, str, a, b, c, d)
779 #define	IPRINTF5(str, a, b, c, d, e)	\
780 	if (IDEBUGGING)	fas_dprintf(fas, str, a, b, c, d, e)
781 #define	IPRINTF6(str, a, b, c, d, e, f)	\
782 	if (IDEBUGGING)	fas_dprintf(fas, str, a, b, c, d, e, f)
783 
784 #else	/* FASDEBUG */
785 
786 #define	EPRINTF(str)
787 #define	EPRINTF1(str, a)
788 #define	EPRINTF2(str, a, b)
789 #define	EPRINTF3(str, a, b, c)
790 #define	EPRINTF4(str, a, b, c, d)
791 #define	EPRINTF5(str, a, b, c, d, e)
792 #define	EPRINTF6(str, a, b, c, d, e, f)
793 #define	DPRINTF(str)
794 #define	DPRINTF1(str, a)
795 #define	DPRINTF2(str, a, b)
796 #define	DPRINTF3(str, a, b, c)
797 #define	DPRINTF4(str, a, b, c, d)
798 #define	DPRINTF5(str, a, b, c, d, e)
799 #define	DPRINTF6(str, a, b, c, d, e, f)
800 #define	IPRINTF(str)
801 #define	IPRINTF1(str, a)
802 #define	IPRINTF2(str, a, b)
803 #define	IPRINTF3(str, a, b, c)
804 #define	IPRINTF4(str, a, b, c, d)
805 #define	IPRINTF5(str, a, b, c, d, e)
806 #define	IPRINTF6(str, a, b, c, d, e, f)
807 
808 #endif	/* FASDEBUG */
809 
810 /*
811  * Shorthand macros and	defines
812  */
813 
814 /*
815  * Short hand defines
816  */
817 #define	ALL_TARGETS	0xffff
818 
819 #define	MAX_THROTTLE	254	/* 1 tag used for non-tagged cmds, 1 rsvd */
820 #define	HOLD_THROTTLE	0
821 #define	DRAIN_THROTTLE	-1
822 #define	QFULL_THROTTLE	-2
823 
824 #define	NODISC(tgt)		(fas->f_nodisc & (1<<(tgt)))
825 #define	NOTAG(tgt)		(fas->f_notag &	(1<<(tgt)))
826 #define	TAGGED(tgt)		((fas->f_notag & (1<<(tgt))) ==	0)
827 #define	SYNC_KNOWN(tgt)		(fas->f_sync_known & (1<<(tgt)))
828 
829 #define	NEXTSLOT(slot, d)	((slot)+(d)) & ((N_SLOTS)-1)
830 #define	MY_ID(fas)		((fas)->f_fasconf & FAS_CONF_BUSID)
831 #define	INTPENDING(fas)		(fas_dma_reg_read((fas), \
832 				    &((fas)->f_dma->dma_csr))&DMA_INT_MASK)
833 
834 #define	Tgt(sp)	((sp)->cmd_pkt->pkt_address.a_target)
835 #define	Lun(sp)	((sp)->cmd_pkt->pkt_address.a_lun)
836 
837 #define	New_state(fas, state)\
838 	(fas)->f_laststate = (fas)->f_state, (fas)->f_state = (state)
839 
840 #define	CNUM		(fas->f_instance)
841 #define	TRUE		1
842 #define	FALSE		0
843 #define	UNDEFINED	-1
844 #define	INVALID_MSG	0x7f
845 
846 /*
847  * Default is to have 10 retries on receiving QFULL status and
848  * each retry to be after 100 ms.
849  */
850 #define	QFULL_RETRIES		10
851 #define	QFULL_RETRY_INTERVAL	100
852 
853 /*
854  * FEPS chip revision
855  */
856 #define	FAS_HM_REV(fas)		(fas)->f_hm_rev
857 
858 /*
859  * Some	manifest miscellaneous constants
860  */
861 
862 #define	MEG		(1000 *	1000)
863 #define	FIVE_MEG	(5 * MEG)
864 #define	TEN_MEG		(10 * MEG)
865 #define	TWENTY_MEG	(20 * MEG)
866 #define	TWENTYFIVE_MEG	(25 * MEG)
867 #define	FORTY_MEG	(40 * MEG)
868 #define	FAS_FREQ_SLOP	(25000)
869 
870 /*
871  * wide	support
872  */
873 #define	FAS_XFER_WIDTH	1
874 
875 #define	FAS_EMPTY_CALLBACKQ(fas)  fas_empty_callbackQ(fas)
876 
877 #define	FAS_CHECK_WAITQ_AND_FAS_MUTEX_EXIT(fas)	\
878 	mutex_enter(&fas->f_waitQ_mutex); \
879 	if (fas->f_waitf) { \
880 		fas_empty_waitQ(fas); \
881 	} \
882 	mutex_exit(FAS_MUTEX(fas)); \
883 	mutex_exit(&fas->f_waitQ_mutex);
884 
885 /*
886  * flags for fas_accept_pkt
887  */
888 #define	NO_TRAN_BUSY	0	/* fas_accept_pkt may not bounce these pkts */
889 #define	TRAN_BUSY_OK	1	/* fas_accept_pkt may bounce these pkts */
890 
891 /*
892  * reset delay tick
893  */
894 #define	FAS_WATCH_RESET_DELAY_TICK 50	/* specified in	milli seconds */
895 
896 /*
897  * 2 ms timeout on receiving tag on reconnect
898  */
899 #define	RECONNECT_TAG_RCV_TIMEOUT 2000	/* allow up to 2 ms */
900 
901 
902 /*
903  * auto	request	sense
904  */
905 #define	RQ_MAKECOM_COMMON(pktp,	flag, cmd)   \
906 	(pktp)->pkt_flags = (flag), \
907 	((union	scsi_cdb *)(pktp)->pkt_cdbp)->scc_cmd =	(cmd), \
908 	((union	scsi_cdb *)(pktp)->pkt_cdbp)->scc_lun =	\
909 	    (pktp)->pkt_address.a_lun
910 
911 #define	RQ_MAKECOM_G0(pktp, flag, cmd, addr, cnt)    \
912 	RQ_MAKECOM_COMMON((pktp), (flag), (cmd)), \
913 	FORMG0ADDR(((union scsi_cdb *)(pktp)->pkt_cdbp), (addr)), \
914 	FORMG0COUNT(((union scsi_cdb *)(pktp)->pkt_cdbp), (cnt))
915 
916 #define	NEW_TIMEOUT	1
917 
918 #ifdef	__cplusplus
919 }
920 #endif
921 
922 #endif	/* _SYS_SCSI_ADAPTERS_FASVAR_H */
923