1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  *
26  * Copyright 2018 RackTop Systems.
27  */
28 
29 #include <sys/types.h>
30 #include <sys/modctl.h>
31 #include <sys/debug.h>
32 #include <sys/promif.h>
33 #include <sys/pci.h>
34 #include <sys/errno.h>
35 #include <sys/open.h>
36 #include <sys/uio.h>
37 #include <sys/cred.h>
38 #include <sys/cpu.h>
39 #include "ata_common.h"
40 #include "ata_disk.h"
41 #include "atapi.h"
42 #include "ata_blacklist.h"
43 #include "sil3xxx.h"
44 
45 /*
46  * Solaris Entry Points.
47  */
48 
49 static	int	ata_attach(dev_info_t *dip, ddi_attach_cmd_t cmd);
50 static	int	ata_detach(dev_info_t *dip, ddi_detach_cmd_t cmd);
51 static	int	ata_bus_ctl(dev_info_t *d, dev_info_t *r, ddi_ctl_enum_t o,
52 			void *a, void *v);
53 static	uint_t	ata_intr(caddr_t arg);
54 
55 /*
56  * GHD Entry points
57  */
58 
59 static	int	ata_get_status(void *hba_handle, void *intr_status);
60 static	void	ata_process_intr(void *hba_handle, void *intr_status);
61 static	int	ata_hba_start(void *handle, gcmd_t *gcmdp);
62 static	void	ata_hba_complete(void *handle, gcmd_t *gcmdp, int do_callback);
63 static	int	ata_timeout_func(void *hba_handle, gcmd_t  *gcmdp,
64 			gtgt_t *gtgtp, gact_t  action, int calltype);
65 
66 /*
67  * Local Function Prototypes
68  */
69 static int ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip,
70 		    uint_t flags, char *name, int defvalue);
71 static	int	ata_ctlr_fsm(uchar_t fsm_func, ata_ctl_t *ata_ctlp,
72 			ata_drv_t *ata_drvp, ata_pkt_t *ata_pktp,
73 				int *DoneFlgp);
74 static	void	ata_destroy_controller(dev_info_t *dip);
75 static	int	ata_drive_type(uchar_t drvhd,
76 			ddi_acc_handle_t io_hdl1, caddr_t ioaddr1,
77 			ddi_acc_handle_t io_hdl2, caddr_t ioaddr2,
78 			struct ata_id *ata_id_bufp);
79 static	ata_ctl_t *ata_init_controller(dev_info_t *dip);
80 static	ata_drv_t *ata_init_drive(ata_ctl_t *ata_ctlp,
81 			uchar_t targ, uchar_t lun);
82 static	int	ata_init_drive_pcidma(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp,
83 			dev_info_t *tdip);
84 static	int	ata_flush_cache(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp);
85 static	void	ata_init_pciide(dev_info_t *dip, ata_ctl_t *ata_ctlp);
86 static	int	ata_reset_bus(ata_ctl_t *ata_ctlp);
87 static	int	ata_setup_ioaddr(dev_info_t *dip,
88 			ddi_acc_handle_t *iohandle1, caddr_t *ioaddr1p,
89 			ddi_acc_handle_t *iohandle2, caddr_t *ioaddr2p,
90 			ddi_acc_handle_t *bm_hdlp, caddr_t *bm_addrp);
91 static	int	ata_software_reset(ata_ctl_t *ata_ctlp);
92 static	int	ata_start_arq(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp,
93 			ata_pkt_t *ata_pktp);
94 static	int	ata_strncmp(char *p1, char *p2, int cnt);
95 static	void	ata_uninit_drive(ata_drv_t *ata_drvp);
96 
97 static	int	ata_check_pciide_blacklist(dev_info_t *dip, uint_t flags);
98 static	int	ata_check_revert_to_defaults(ata_drv_t *ata_drvp);
99 static  void	ata_show_transfer_mode(ata_ctl_t *, ata_drv_t *);
100 static	int	ata_spec_init_controller(dev_info_t *dip);
101 
102 static void	ata_init_pm(dev_info_t *);
103 static int	ata_suspend(dev_info_t *);
104 static int	ata_resume(dev_info_t *);
105 static int	ata_power(dev_info_t *, int, int);
106 static int	ata_change_power(dev_info_t *, uint8_t);
107 static int	ata_is_pci(dev_info_t *);
108 static void	ata_disable_DMA(ata_drv_t *ata_drvp);
109 static int	ata_check_dma_mode(ata_drv_t *ata_drvp);
110 
111 /*
112  * Local static data
113  */
114 static	void	*ata_state;
115 
116 static	tmr_t	ata_timer_conf; /* single timeout list for all instances */
117 static	int	ata_watchdog_usec = 100000; /* check timeouts every 100 ms */
118 
119 int	ata_hba_start_watchdog = 1000;
120 int	ata_process_intr_watchdog = 1000;
121 int	ata_reset_bus_watchdog = 1000;
122 
123 
124 /*
125  * Use local or framework power management
126  */
127 
128 #ifdef	ATA_USE_AUTOPM
129 #define	ATA_BUSY_COMPONENT(d, c)	((void)pm_busy_component(d, c))
130 #define	ATA_IDLE_COMPONENT(d, c)	((void)pm_idle_component(d, c))
131 #define	ATA_RAISE_POWER(d, c, l)	pm_raise_power(d, c, l)
132 #define	ATA_LOWER_POWER(d, c, l)	pm_lower_power(d, c, l)
133 #else
134 #define	ATA_BUSY_COMPONENT(d, c)
135 #define	ATA_IDLE_COMPONENT(d, c)
136 #define	ATA_RAISE_POWER(d, c, l)	ata_power(d, c, l)
137 #define	ATA_LOWER_POWER(d, c, l)	ata_power(d, c, l)
138 #endif
139 /*
140  * number of seconds to wait during various operations
141  */
142 int	ata_flush_delay = 5 * 1000000;
143 uint_t	ata_set_feature_wait = 4 * 1000000;
144 uint_t	ata_flush_cache_wait = 60 * 1000000;	/* may take a long time */
145 
146 /*
147  * Change this for SFF-8070i support. Currently SFF-8070i is
148  * using a field in the IDENTIFY PACKET DEVICE response which
149  * already seems to be in use by some vendor's drives. I suspect
150  * SFF will either move their laslun field or provide a reliable
151  * way to validate it.
152  */
153 int	ata_enable_atapi_luns = FALSE;
154 
155 /*
156  * set this to disable all DMA requests
157  */
158 int	ata_dma_disabled = FALSE;
159 
160 /*
161  * set this to TRUE to enable storing the IDENTIFY DEVICE result in the
162  * "ata" or "atapi" property.
163  */
164 int	ata_id_debug = FALSE;
165 
166 /*
167  * set this to TRUE to enable logging device-capability data
168  */
169 int	ata_capability_data = FALSE;
170 
171 /*
172  * DMA selection message pointers
173  */
174 char *ata_cntrl_DMA_sel_msg;
175 char *ata_dev_DMA_sel_msg;
176 
177 /*
178  * bus nexus operations
179  */
180 static	struct bus_ops	 ata_bus_ops;
181 static	struct bus_ops	*scsa_bus_ops_p;
182 
183 /* ARGSUSED */
184 static int
ata_open(dev_t * devp,int flag,int otyp,cred_t * cred_p)185 ata_open(dev_t *devp, int flag, int otyp, cred_t *cred_p)
186 {
187 	if (ddi_get_soft_state(ata_state, getminor(*devp)) == NULL)
188 		return (ENXIO);
189 
190 	return (0);
191 }
192 
193 /*
194  * The purpose of this function is to pass the ioaddress of the controller
195  * to the caller, specifically used for upgrade from pre-pciide
196  * to pciide nodes
197  */
198 /* ARGSUSED */
199 static int
ata_read(dev_t dev,struct uio * uio_p,cred_t * cred_p)200 ata_read(dev_t dev, struct uio *uio_p, cred_t *cred_p)
201 {
202 	ata_ctl_t *ata_ctlp;
203 	char	buf[18];
204 	long len;
205 
206 	ata_ctlp = ddi_get_soft_state(ata_state, getminor(dev));
207 
208 	if (ata_ctlp == NULL)
209 		return (ENXIO);
210 
211 	(void) sprintf(buf, "%p\n", (void *) ata_ctlp->ac_ioaddr1);
212 
213 	len = strlen(buf) - uio_p->uio_offset;
214 	len = min(uio_p->uio_resid,  len);
215 	if (len <= 0)
216 		return (0);
217 
218 	return (uiomove((caddr_t)(buf + uio_p->uio_offset), len,
219 	    UIO_READ, uio_p));
220 }
221 
222 int
ata_devo_reset(dev_info_t * dip,ddi_reset_cmd_t cmd)223 ata_devo_reset(
224 	dev_info_t *dip,
225 	ddi_reset_cmd_t cmd)
226 {
227 	ata_ctl_t *ata_ctlp;
228 	ata_drv_t *ata_drvp;
229 	int	   instance;
230 	int	   i;
231 	int	   rc;
232 	int	   flush_okay;
233 
234 	if (cmd != DDI_RESET_FORCE)
235 		return (0);
236 
237 	instance = ddi_get_instance(dip);
238 	ata_ctlp = ddi_get_soft_state(ata_state, instance);
239 
240 	if (!ata_ctlp)
241 		return (0);
242 
243 	/*
244 	 * reset ATA drives and flush the write cache of any drives
245 	 */
246 	flush_okay = TRUE;
247 	for (i = 0; i < ATA_MAXTARG; i++) {
248 		if ((ata_drvp = CTL2DRV(ata_ctlp, i, 0)) == 0)
249 			continue;
250 		/* Don't revert to defaults for certain IBM drives */
251 		if ((ata_drvp->ad_flags & AD_DISK) != 0 &&
252 		    ((ata_drvp->ad_flags & AD_NORVRT) == 0)) {
253 			/* Enable revert to defaults when reset */
254 			(void) ata_set_feature(ata_ctlp, ata_drvp,
255 			    ATSF_ENA_REVPOD, 0);
256 		}
257 
258 		/*
259 		 * skip flush cache if device type is cdrom
260 		 *
261 		 * notes: the structure definitions for ata_drvp->ad_id are
262 		 * defined for the ATA IDENTIFY_DEVICE, but if AD_ATAPI is set
263 		 * the struct holds data for the ATAPI IDENTIFY_PACKET_DEVICE
264 		 */
265 		if (!IS_CDROM(ata_drvp)) {
266 
267 			/*
268 			 * Try the ATA/ATAPI flush write cache command
269 			 */
270 			rc = ata_flush_cache(ata_ctlp, ata_drvp);
271 			ADBG_WARN(("ata_flush_cache %s\n",
272 			    rc ? "okay" : "failed"));
273 
274 			if (!rc)
275 				flush_okay = FALSE;
276 		}
277 
278 
279 		/*
280 		 * do something else if flush cache not supported
281 		 */
282 	}
283 
284 	/*
285 	 * just busy wait if any drive doesn't support FLUSH CACHE
286 	 */
287 	if (!flush_okay)
288 		drv_usecwait(ata_flush_delay);
289 	return (0);
290 }
291 
292 /*
293  * quiesce(9E) entry point.
294  *
295  * This function is called when the system is single-threaded at high
296  * PIL with preemption disabled. Therefore, this function must not be
297  * blocked.
298  *
299  * This function returns DDI_SUCCESS on success, or DDI_FAILURE on failure.
300  * DDI_FAILURE indicates an error condition and should almost never happen.
301  */
302 int
ata_quiesce(dev_info_t * dip)303 ata_quiesce(dev_info_t *dip)
304 {
305 #ifdef ATA_DEBUG
306 	/*
307 	 * Turn off debugging
308 	 */
309 	ata_debug = 0;
310 #endif
311 
312 	return (ata_devo_reset(dip, DDI_RESET_FORCE));
313 }
314 
315 
316 static struct cb_ops ata_cb_ops = {
317 	ata_open,		/* open */
318 	nulldev,		/* close */
319 	nodev,			/* strategy */
320 	nodev,			/* print */
321 	nodev,			/* dump */
322 	ata_read,		/* read */
323 	nodev,			/* write */
324 	nodev,			/* ioctl */
325 	nodev,			/* devmap */
326 	nodev,			/* mmap */
327 	nodev,			/* segmap */
328 	nochpoll,		/* chpoll */
329 	ddi_prop_op,		/* prop_op */
330 	NULL,			/* stream info */
331 	D_MP,			/* driver compatibility flag */
332 	CB_REV,			/* cb_ops revision */
333 	nodev,			/* aread */
334 	nodev			/* awrite */
335 };
336 
337 static struct dev_ops	ata_ops = {
338 	DEVO_REV,		/* devo_rev, */
339 	0,			/* refcnt  */
340 	ddi_getinfo_1to1,	/* info */
341 	nulldev,		/* identify */
342 	NULL,			/* probe */
343 	ata_attach,		/* attach */
344 	ata_detach,		/* detach */
345 	ata_devo_reset,		/* reset */
346 	&ata_cb_ops,		/* driver operations */
347 	NULL,			/* bus operations */
348 	ata_power,		/* power */
349 	ata_quiesce		/* quiesce */
350 };
351 
352 /* driver loadable module wrapper */
353 static struct modldrv modldrv = {
354 	&mod_driverops,		/* Type of module. This one is a driver */
355 	"ATA AT-bus attachment disk controller Driver",	/* module name */
356 	&ata_ops,					/* driver ops */
357 };
358 
359 static struct modlinkage modlinkage = {
360 	MODREV_1, (void *)&modldrv, NULL
361 };
362 
363 #ifdef ATA_DEBUG
364 int	ata_debug_init = FALSE;
365 int	ata_debug_attach = FALSE;
366 
367 int	ata_debug = ADBG_FLAG_ERROR
368 		/* | ADBG_FLAG_ARQ */
369 		/* | ADBG_FLAG_INIT */
370 		/* | ADBG_FLAG_TRACE */
371 		/* | ADBG_FLAG_TRANSPORT */
372 		/* | ADBG_FLAG_WARN */
373 		;
374 #endif
375 
376 int
_init(void)377 _init(void)
378 {
379 	int err;
380 
381 #ifdef ATA_DEBUG
382 	if (ata_debug_init)
383 		debug_enter("\nATA _INIT\n");
384 #endif
385 
386 	if ((err = ddi_soft_state_init(&ata_state, sizeof (ata_ctl_t), 0)) != 0)
387 		return (err);
388 
389 	if ((err = scsi_hba_init(&modlinkage)) != 0) {
390 		ddi_soft_state_fini(&ata_state);
391 		return (err);
392 	}
393 
394 	/* save pointer to SCSA provided bus_ops struct */
395 	scsa_bus_ops_p = ata_ops.devo_bus_ops;
396 
397 	/* make a copy of SCSA bus_ops */
398 	ata_bus_ops = *(ata_ops.devo_bus_ops);
399 
400 	/*
401 	 * Modify our bus_ops to call our routines.  Our implementation
402 	 * will determine if the device is ATA or ATAPI/SCSA and react
403 	 * accordingly.
404 	 */
405 	ata_bus_ops.bus_ctl = ata_bus_ctl;
406 
407 	/* patch our bus_ops into the dev_ops struct */
408 	ata_ops.devo_bus_ops = &ata_bus_ops;
409 
410 	if ((err = mod_install(&modlinkage)) != 0) {
411 		scsi_hba_fini(&modlinkage);
412 		ddi_soft_state_fini(&ata_state);
413 	}
414 
415 	/*
416 	 * Initialize the per driver timer info.
417 	 */
418 
419 	ghd_timer_init(&ata_timer_conf, drv_usectohz(ata_watchdog_usec));
420 
421 	return (err);
422 }
423 
424 int
_fini(void)425 _fini(void)
426 {
427 	int err;
428 
429 	if ((err = mod_remove(&modlinkage)) == 0) {
430 		ghd_timer_fini(&ata_timer_conf);
431 		scsi_hba_fini(&modlinkage);
432 		ddi_soft_state_fini(&ata_state);
433 	}
434 
435 	return (err);
436 }
437 
438 int
_info(struct modinfo * modinfop)439 _info(struct modinfo *modinfop)
440 {
441 	return (mod_info(&modlinkage, modinfop));
442 }
443 
444 
445 /*
446  *
447  * driver attach entry point
448  *
449  */
450 
451 static int
ata_attach(dev_info_t * dip,ddi_attach_cmd_t cmd)452 ata_attach(
453 	dev_info_t *dip,
454 	ddi_attach_cmd_t cmd)
455 {
456 	ata_ctl_t	*ata_ctlp;
457 	ata_drv_t	*ata_drvp;
458 	ata_drv_t	*first_drvp = NULL;
459 	uchar_t		 targ;
460 	uchar_t		 lun;
461 	uchar_t		 lastlun;
462 	int		 atapi_count = 0;
463 	int		 disk_count = 0;
464 
465 	ADBG_TRACE(("ata_attach entered\n"));
466 #ifdef ATA_DEBUG
467 	if (ata_debug_attach)
468 		debug_enter("\nATA_ATTACH\n\n");
469 #endif
470 
471 	switch (cmd) {
472 	case DDI_ATTACH:
473 		break;
474 	case DDI_RESUME:
475 		return (ata_resume(dip));
476 	default:
477 		return (DDI_FAILURE);
478 	}
479 
480 	/* initialize controller */
481 	ata_ctlp = ata_init_controller(dip);
482 
483 	if (ata_ctlp == NULL)
484 		goto errout;
485 
486 	mutex_enter(&ata_ctlp->ac_ccc.ccc_hba_mutex);
487 
488 	/* initialize drives */
489 
490 	for (targ = 0; targ < ATA_MAXTARG; targ++) {
491 
492 		ata_drvp = ata_init_drive(ata_ctlp, targ, 0);
493 		if (ata_drvp == NULL)
494 			continue;
495 
496 		if (first_drvp == NULL)
497 			first_drvp = ata_drvp;
498 
499 		if (ATAPIDRV(ata_drvp)) {
500 			atapi_count++;
501 			lastlun = ata_drvp->ad_id.ai_lastlun;
502 		} else {
503 			disk_count++;
504 			lastlun = 0;
505 		}
506 
507 		/*
508 		 * LUN support is currently disabled. Check with SFF-8070i
509 		 * before enabling.
510 		 */
511 		if (!ata_enable_atapi_luns)
512 			lastlun = 0;
513 
514 		/* Initialize higher LUNs, if there are any */
515 		for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) {
516 			if ((ata_drvp =
517 			    ata_init_drive(ata_ctlp, targ, lun)) != NULL) {
518 				ata_show_transfer_mode(ata_ctlp, ata_drvp);
519 			}
520 		}
521 	}
522 
523 	if ((atapi_count == 0) && (disk_count == 0)) {
524 		ADBG_WARN(("ata_attach: no drives detected\n"));
525 		goto errout1;
526 	}
527 
528 	/*
529 	 * Always make certain that a valid drive is selected so
530 	 * that routines which poll the status register don't get
531 	 * confused by non-existent drives.
532 	 */
533 	ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd,
534 	    first_drvp->ad_drive_bits);
535 	ata_nsecwait(400);
536 
537 	/*
538 	 * make certain the drive selected
539 	 */
540 	if (!ata_wait(ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2,
541 	    0, ATS_BSY, 5000000)) {
542 		ADBG_ERROR(("ata_attach: select failed\n"));
543 	}
544 
545 	/*
546 	 * initialize atapi/ata_dsk modules if we have at least
547 	 * one drive of that type.
548 	 */
549 
550 	if (atapi_count) {
551 		if (!atapi_attach(ata_ctlp))
552 			goto errout1;
553 		ata_ctlp->ac_flags |= AC_ATAPI_INIT;
554 	}
555 
556 	if (disk_count) {
557 		if (!ata_disk_attach(ata_ctlp))
558 			goto errout1;
559 		ata_ctlp->ac_flags |= AC_DISK_INIT;
560 	}
561 
562 	/*
563 	 * make certain the interrupt and error latches are clear
564 	 */
565 	if (ata_ctlp->ac_pciide) {
566 
567 		int instance = ddi_get_instance(dip);
568 		if (ddi_create_minor_node(dip, "control", S_IFCHR, instance,
569 		    DDI_PSEUDO, 0) != DDI_SUCCESS) {
570 			goto errout1;
571 		}
572 
573 		(void) ata_pciide_status_clear(ata_ctlp);
574 
575 	}
576 
577 	/*
578 	 * enable the interrupt handler and drop the mutex
579 	 */
580 	ata_ctlp->ac_flags |= AC_ATTACHED;
581 	mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex);
582 
583 	ata_init_pm(dip);
584 
585 	ddi_report_dev(dip);
586 	return (DDI_SUCCESS);
587 
588 errout1:
589 	mutex_exit(&ata_ctlp->ac_ccc.ccc_hba_mutex);
590 errout:
591 	(void) ata_detach(dip, DDI_DETACH);
592 	return (DDI_FAILURE);
593 }
594 
595 /* driver detach entry point */
596 
597 static int
ata_detach(dev_info_t * dip,ddi_detach_cmd_t cmd)598 ata_detach(
599 	dev_info_t *dip,
600 	ddi_detach_cmd_t cmd)
601 {
602 	ata_ctl_t *ata_ctlp;
603 	ata_drv_t *ata_drvp;
604 	int	   instance;
605 	int	   i;
606 	int	   j;
607 
608 	ADBG_TRACE(("ata_detach entered\n"));
609 
610 	switch (cmd) {
611 	case DDI_DETACH:
612 		break;
613 	case DDI_SUSPEND:
614 		return (ata_suspend(dip));
615 	default:
616 		return (DDI_FAILURE);
617 	}
618 
619 	instance = ddi_get_instance(dip);
620 	ata_ctlp = ddi_get_soft_state(ata_state, instance);
621 
622 	if (!ata_ctlp)
623 		return (DDI_SUCCESS);
624 
625 	if (ata_ctlp->ac_pm_support) {
626 		ATA_BUSY_COMPONENT(dip, 0);
627 		if (ata_ctlp->ac_pm_level != PM_LEVEL_D0) {
628 			if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) !=
629 			    DDI_SUCCESS) {
630 				ATA_IDLE_COMPONENT(dip, 0);
631 				return (DDI_FAILURE);
632 			}
633 		}
634 		(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components");
635 	}
636 	ata_ctlp->ac_flags &= ~AC_ATTACHED;
637 
638 	/* destroy ata module */
639 	if (ata_ctlp->ac_flags & AC_DISK_INIT)
640 		ata_disk_detach(ata_ctlp);
641 
642 	/* destroy atapi module */
643 	if (ata_ctlp->ac_flags & AC_ATAPI_INIT)
644 		atapi_detach(ata_ctlp);
645 
646 	ddi_remove_minor_node(dip, NULL);
647 
648 	/* destroy drives */
649 	for (i = 0; i < ATA_MAXTARG; i++) {
650 		for (j = 0; j < ATA_MAXLUN; j++) {
651 			ata_drvp = CTL2DRV(ata_ctlp, i, j);
652 			if (ata_drvp != NULL)
653 				ata_uninit_drive(ata_drvp);
654 		}
655 	}
656 
657 	if (ata_ctlp->ac_iohandle1)
658 		ddi_regs_map_free(&ata_ctlp->ac_iohandle1);
659 	if (ata_ctlp->ac_iohandle2)
660 		ddi_regs_map_free(&ata_ctlp->ac_iohandle2);
661 	if (ata_ctlp->ac_bmhandle)
662 		ddi_regs_map_free(&ata_ctlp->ac_bmhandle);
663 
664 	/* destroy controller */
665 	ata_destroy_controller(dip);
666 
667 	ddi_prop_remove_all(dip);
668 
669 	return (DDI_SUCCESS);
670 }
671 
672 /*
673  * Nexus driver bus_ctl entry point
674  */
675 /*ARGSUSED*/
676 static int
ata_bus_ctl(dev_info_t * d,dev_info_t * r,ddi_ctl_enum_t o,void * a,void * v)677 ata_bus_ctl(
678 	dev_info_t *d,
679 	dev_info_t *r,
680 	ddi_ctl_enum_t o,
681 	void *a,
682 	void *v)
683 {
684 	dev_info_t *tdip;
685 	int	target_type;
686 	int	rc;
687 	char	*bufp;
688 
689 	ADBG_TRACE(("ata_bus_ctl entered\n"));
690 
691 	switch (o) {
692 
693 	case DDI_CTLOPS_SIDDEV:
694 		return (DDI_FAILURE);
695 
696 	case DDI_CTLOPS_IOMIN:
697 
698 		/*
699 		 * Since we use PIO, we return a minimum I/O size of
700 		 * one byte.  This will need to be updated when we
701 		 * implement DMA support
702 		 */
703 
704 		*((int *)v) = 1;
705 		return (DDI_SUCCESS);
706 
707 	case DDI_CTLOPS_DMAPMAPC:
708 	case DDI_CTLOPS_REPORTINT:
709 	case DDI_CTLOPS_REGSIZE:
710 	case DDI_CTLOPS_NREGS:
711 	case DDI_CTLOPS_SLAVEONLY:
712 	case DDI_CTLOPS_AFFINITY:
713 	case DDI_CTLOPS_POKE:
714 	case DDI_CTLOPS_PEEK:
715 
716 		/* These ops shouldn't be called by a target driver */
717 		ADBG_ERROR(("ata_bus_ctl: %s%d: invalid op (%d) from %s%d\n",
718 		    ddi_driver_name(d), ddi_get_instance(d), o,
719 		    ddi_driver_name(r), ddi_get_instance(r)));
720 
721 		return (DDI_FAILURE);
722 
723 	case DDI_CTLOPS_REPORTDEV:
724 	case DDI_CTLOPS_INITCHILD:
725 	case DDI_CTLOPS_UNINITCHILD:
726 
727 		/* these require special handling below */
728 		break;
729 
730 	default:
731 		return (ddi_ctlops(d, r, o, a, v));
732 	}
733 
734 	/* get targets dip */
735 
736 	if (o == DDI_CTLOPS_INITCHILD || o == DDI_CTLOPS_UNINITCHILD)
737 		tdip = (dev_info_t *)a;
738 	else
739 		tdip = r;
740 
741 	/*
742 	 * XXX - Get class of target
743 	 *   Before the "class" entry in a conf file becomes
744 	 *   a real property, we use an additional property
745 	 *   tentatively called "class_prop".  We will require that
746 	 *   new classes (ie. direct) export "class_prop".
747 	 *   SCSA target drivers will not have this property, so
748 	 *   no property implies SCSA.
749 	 */
750 	if ((ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS,
751 	    "class", &bufp) == DDI_PROP_SUCCESS) ||
752 	    (ddi_prop_lookup_string(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS,
753 	    "class_prop", &bufp) == DDI_PROP_SUCCESS)) {
754 		if (strcmp(bufp, "dada") == 0)
755 			target_type = ATA_DEV_DISK;
756 		else if (strcmp(bufp, "scsi") == 0)
757 			target_type = ATA_DEV_ATAPI;
758 		else {
759 			ADBG_WARN(("ata_bus_ctl: invalid target class %s\n",
760 			    bufp));
761 			ddi_prop_free(bufp);
762 			return (DDI_FAILURE);
763 		}
764 		ddi_prop_free(bufp);
765 	} else {
766 		target_type = ATA_DEV_ATAPI; /* no class prop, assume SCSI */
767 	}
768 
769 	if (o == DDI_CTLOPS_INITCHILD) {
770 		int	instance = ddi_get_instance(d);
771 		ata_ctl_t *ata_ctlp = ddi_get_soft_state(ata_state, instance);
772 		ata_drv_t *ata_drvp;
773 		int	targ;
774 		int	lun;
775 		int	drive_type;
776 		char	*disk_prop;
777 		char	*class_prop;
778 
779 		if (ata_ctlp == NULL) {
780 			ADBG_WARN(("ata_bus_ctl: failed to find ctl struct\n"));
781 			return (DDI_FAILURE);
782 		}
783 
784 		/* get (target,lun) of child device */
785 
786 		targ = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS,
787 		    "target", -1);
788 		if (targ == -1) {
789 			ADBG_WARN(("ata_bus_ctl: failed to get targ num\n"));
790 			return (DDI_FAILURE);
791 		}
792 
793 		lun = ddi_prop_get_int(DDI_DEV_T_ANY, tdip, DDI_PROP_DONTPASS,
794 		    "lun", 0);
795 
796 		if ((targ < 0) || (targ >= ATA_MAXTARG) ||
797 		    (lun < 0) || (lun >= ATA_MAXLUN)) {
798 			return (DDI_FAILURE);
799 		}
800 
801 		ata_drvp = CTL2DRV(ata_ctlp, targ, lun);
802 
803 		if (ata_drvp == NULL)
804 			return (DDI_FAILURE);	/* no drive */
805 
806 		/* get type of device */
807 
808 		if (ATAPIDRV(ata_drvp))
809 			drive_type = ATA_DEV_ATAPI;
810 		else
811 			drive_type = ATA_DEV_DISK;
812 
813 		/*
814 		 * Check for special handling when child driver is
815 		 * cmdk (which morphs to the correct interface)
816 		 */
817 		if (strcmp(ddi_get_name(tdip), "cmdk") == 0) {
818 
819 			if ((target_type == ATA_DEV_DISK) &&
820 			    (target_type != drive_type))
821 				return (DDI_FAILURE);
822 
823 			target_type = drive_type;
824 
825 			if (drive_type == ATA_DEV_ATAPI) {
826 				class_prop = "scsi";
827 			} else {
828 				disk_prop = "dadk";
829 				class_prop = "dada";
830 
831 				if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip,
832 				    "disk", disk_prop) != DDI_PROP_SUCCESS) {
833 					ADBG_WARN(("ata_bus_ctl: failed to "
834 					    "create disk prop\n"));
835 					return (DDI_FAILURE);
836 				}
837 			}
838 
839 			if (ndi_prop_update_string(DDI_DEV_T_NONE, tdip,
840 			    "class_prop", class_prop) != DDI_PROP_SUCCESS) {
841 				ADBG_WARN(("ata_bus_ctl: failed to "
842 				    "create class prop\n"));
843 				return (DDI_FAILURE);
844 			}
845 		}
846 
847 		/* Check that target class matches the device */
848 
849 		if (target_type != drive_type)
850 			return (DDI_FAILURE);
851 
852 		/* save pointer to drive struct for ata_disk_bus_ctl */
853 		ddi_set_driver_private(tdip, ata_drvp);
854 
855 		/*
856 		 * Determine whether to enable DMA support for this drive.  This
857 		 * check is deferred to this point so that the various dma
858 		 * properties could reside on the devinfo node should finer
859 		 * grained dma control be required.
860 		 */
861 		if (ata_drvp->ad_pciide_dma == ATA_DMA_UNINITIALIZED) {
862 			ata_drvp->ad_pciide_dma =
863 			    ata_init_drive_pcidma(ata_ctlp, ata_drvp, tdip);
864 			ata_show_transfer_mode(ata_ctlp, ata_drvp);
865 		}
866 	}
867 
868 	if (target_type == ATA_DEV_ATAPI) {
869 		rc = scsa_bus_ops_p->bus_ctl(d, r, o, a, v);
870 	} else {
871 		rc = ata_disk_bus_ctl(d, r, o, a, v);
872 	}
873 
874 	return (rc);
875 }
876 
877 /*
878  *
879  * GHD ccc_hba_complete callback
880  *
881  */
882 
883 /* ARGSUSED */
884 static void
ata_hba_complete(void * hba_handle,gcmd_t * gcmdp,int do_callback)885 ata_hba_complete(
886 	void *hba_handle,
887 	gcmd_t *gcmdp,
888 	int do_callback)
889 {
890 	ata_drv_t *ata_drvp;
891 	ata_pkt_t *ata_pktp;
892 
893 	ADBG_TRACE(("ata_hba_complete entered\n"));
894 
895 	ata_drvp = GCMD2DRV(gcmdp);
896 	ata_pktp = GCMD2APKT(gcmdp);
897 	if (ata_pktp->ap_complete)
898 		(*ata_pktp->ap_complete)(ata_drvp, ata_pktp,
899 		    do_callback);
900 }
901 
902 /* GHD ccc_timeout_func callback */
903 
904 /* ARGSUSED */
905 static int
ata_timeout_func(void * hba_handle,gcmd_t * gcmdp,gtgt_t * gtgtp,gact_t action,int calltype)906 ata_timeout_func(
907 	void	*hba_handle,
908 	gcmd_t	*gcmdp,
909 	gtgt_t	*gtgtp,
910 	gact_t	 action,
911 	int	 calltype)
912 {
913 	ata_ctl_t *ata_ctlp;
914 	ata_pkt_t *ata_pktp;
915 	ata_drv_t *ata_drvp;
916 
917 	ADBG_TRACE(("ata_timeout_func entered\n"));
918 
919 	ata_ctlp = (ata_ctl_t *)hba_handle;
920 
921 	if (gcmdp != NULL)
922 		ata_pktp = GCMD2APKT(gcmdp);
923 	else
924 		ata_pktp = NULL;
925 
926 	switch (action) {
927 	case GACTION_EARLY_ABORT:
928 		/* abort before request was started */
929 		if (ata_pktp != NULL) {
930 			ata_pktp->ap_flags |= AP_ABORT;
931 		}
932 		ghd_complete(&ata_ctlp->ac_ccc, gcmdp);
933 		return (TRUE);
934 
935 	case GACTION_EARLY_TIMEOUT:
936 		/* timeout before request was started */
937 		if (ata_pktp != NULL) {
938 			ata_pktp->ap_flags |= AP_TIMEOUT;
939 		}
940 		ghd_complete(&ata_ctlp->ac_ccc, gcmdp);
941 		return (TRUE);
942 
943 	case GACTION_RESET_TARGET:
944 		/*
945 		 * Reset a device is not supported. Resetting a specific
946 		 * device can't be done at all to an ATA device and if
947 		 * you send a RESET to an ATAPI device you have to
948 		 * reset the whole bus to make certain both devices
949 		 * on the bus stay in sync regarding which device is
950 		 * the currently selected one.
951 		 */
952 		return (FALSE);
953 
954 	case GACTION_RESET_BUS:
955 		/*
956 		 * Issue bus reset and reinitialize both drives.
957 		 * But only if this is a timed-out request. Target
958 		 * driver reset requests are ignored because ATA
959 		 * and ATAPI devices shouldn't be gratuitously reset.
960 		 * Also disable DMA if it is a CF device.
961 		 */
962 		if (gcmdp == NULL)
963 			break;
964 		ata_drvp = GCMD2DRV(gcmdp);
965 		if (ata_drvp != NULL)
966 			if (ata_drvp->ad_id.ai_config == ATA_ID_CF_TO_ATA)
967 				ata_disable_DMA(ata_drvp);
968 		return (ata_reset_bus(ata_ctlp));
969 	default:
970 		break;
971 	}
972 	return (FALSE);
973 }
974 
975 /*
976  *
977  * Initialize controller's soft-state structure
978  *
979  */
980 
981 static ata_ctl_t *
ata_init_controller(dev_info_t * dip)982 ata_init_controller(
983 	dev_info_t *dip)
984 {
985 	ata_ctl_t *ata_ctlp;
986 	int	   instance;
987 	caddr_t	   ioaddr1;
988 	caddr_t	   ioaddr2;
989 
990 	ADBG_TRACE(("ata_init_controller entered\n"));
991 
992 	instance = ddi_get_instance(dip);
993 
994 	/* allocate controller structure */
995 	if (ddi_soft_state_zalloc(ata_state, instance) != DDI_SUCCESS) {
996 		ADBG_WARN(("ata_init_controller: soft_state_zalloc failed\n"));
997 		return (NULL);
998 	}
999 
1000 	ata_ctlp = ddi_get_soft_state(ata_state, instance);
1001 
1002 	if (ata_ctlp == NULL) {
1003 		ADBG_WARN(("ata_init_controller: failed to find "
1004 		    "controller struct\n"));
1005 		return (NULL);
1006 	}
1007 
1008 	/*
1009 	 * initialize per-controller data
1010 	 */
1011 	ata_ctlp->ac_dip = dip;
1012 	ata_ctlp->ac_arq_pktp = kmem_zalloc(sizeof (ata_pkt_t), KM_SLEEP);
1013 
1014 	/*
1015 	 * map the device registers
1016 	 */
1017 	if (!ata_setup_ioaddr(dip, &ata_ctlp->ac_iohandle1, &ioaddr1,
1018 	    &ata_ctlp->ac_iohandle2, &ioaddr2,
1019 	    &ata_ctlp->ac_bmhandle, &ata_ctlp->ac_bmaddr)) {
1020 		(void) ata_detach(dip, DDI_DETACH);
1021 		return (NULL);
1022 	}
1023 
1024 	ADBG_INIT(("ata_init_controller: ioaddr1 = 0x%p, ioaddr2 = 0x%p\n",
1025 	    ioaddr1, ioaddr2));
1026 
1027 	/*
1028 	 * Do ARQ setup
1029 	 */
1030 	atapi_init_arq(ata_ctlp);
1031 
1032 	/*
1033 	 * Do PCI-IDE setup
1034 	 */
1035 	ata_init_pciide(dip, ata_ctlp);
1036 
1037 	/*
1038 	 * port addresses associated with ioaddr1
1039 	 */
1040 	ata_ctlp->ac_ioaddr1	= ioaddr1;
1041 	ata_ctlp->ac_data	= (ushort_t *)ioaddr1 + AT_DATA;
1042 	ata_ctlp->ac_error	= (uchar_t *)ioaddr1 + AT_ERROR;
1043 	ata_ctlp->ac_feature	= (uchar_t *)ioaddr1 + AT_FEATURE;
1044 	ata_ctlp->ac_count	= (uchar_t *)ioaddr1 + AT_COUNT;
1045 	ata_ctlp->ac_sect	= (uchar_t *)ioaddr1 + AT_SECT;
1046 	ata_ctlp->ac_lcyl	= (uchar_t *)ioaddr1 + AT_LCYL;
1047 	ata_ctlp->ac_hcyl	= (uchar_t *)ioaddr1 + AT_HCYL;
1048 	ata_ctlp->ac_drvhd	= (uchar_t *)ioaddr1 + AT_DRVHD;
1049 	ata_ctlp->ac_status	= (uchar_t *)ioaddr1 + AT_STATUS;
1050 	ata_ctlp->ac_cmd	= (uchar_t *)ioaddr1 + AT_CMD;
1051 
1052 	/*
1053 	 * port addresses associated with ioaddr2
1054 	 */
1055 	ata_ctlp->ac_ioaddr2	= ioaddr2;
1056 	ata_ctlp->ac_altstatus	= (uchar_t *)ioaddr2 + AT_ALTSTATUS;
1057 	ata_ctlp->ac_devctl	= (uchar_t *)ioaddr2 + AT_DEVCTL;
1058 
1059 	/*
1060 	 * If AC_BSY_WAIT needs to be set  for laptops that do
1061 	 * suspend/resume but do not correctly wait for the busy bit to
1062 	 * drop after a resume.
1063 	 */
1064 	ata_ctlp->ac_timing_flags = ddi_prop_get_int(DDI_DEV_T_ANY,
1065 	    dip, DDI_PROP_DONTPASS, "timing_flags", 0);
1066 	/*
1067 	 * get max transfer size, default to 256 sectors
1068 	 */
1069 	ata_ctlp->ac_max_transfer = ddi_prop_get_int(DDI_DEV_T_ANY,
1070 	    dip, DDI_PROP_DONTPASS, "max_transfer", 0x100);
1071 	if (ata_ctlp->ac_max_transfer < 1)
1072 		ata_ctlp->ac_max_transfer = 1;
1073 	if (ata_ctlp->ac_max_transfer > 0x100)
1074 		ata_ctlp->ac_max_transfer = 0x100;
1075 
1076 	/*
1077 	 * Get the standby timer value
1078 	 */
1079 	ata_ctlp->ac_standby_time = ddi_prop_get_int(DDI_DEV_T_ANY,
1080 	    dip, DDI_PROP_DONTPASS, "standby", -1);
1081 
1082 	/*
1083 	 * If this is a /pci/pci-ide instance check to see if
1084 	 * it's supposed to be attached as an /isa/ata
1085 	 */
1086 	if (ata_ctlp->ac_pciide) {
1087 		static char prop_buf[] = "SUNW-ata-ffff-isa";
1088 		int addr1 = (intptr_t)ioaddr1;
1089 
1090 
1091 		if (addr1 < 0 || addr1 > 0xffff) {
1092 			(void) ata_detach(dip, DDI_DETACH);
1093 			return (NULL);
1094 		}
1095 		(void) sprintf(prop_buf, "SUNW-ata-%04x-isa",
1096 		    addr1);
1097 		if (ddi_prop_exists(DDI_DEV_T_ANY, ddi_root_node(),
1098 		    DDI_PROP_DONTPASS, prop_buf)) {
1099 			(void) ata_detach(dip, DDI_DETACH);
1100 			return (NULL);
1101 		}
1102 	}
1103 
1104 	/* Init controller specific stuff */
1105 	(void) ata_spec_init_controller(dip);
1106 
1107 	/*
1108 	 * initialize GHD
1109 	 */
1110 
1111 	GHD_WAITQ_INIT(&ata_ctlp->ac_ccc.ccc_waitq, NULL, 1);
1112 
1113 	if (!ghd_register("ata", &ata_ctlp->ac_ccc, dip, 0, ata_ctlp,
1114 	    atapi_ccballoc, atapi_ccbfree,
1115 	    ata_pciide_dma_sg_func, ata_hba_start,
1116 	    ata_hba_complete, ata_intr,
1117 	    ata_get_status, ata_process_intr, ata_timeout_func,
1118 	    &ata_timer_conf, NULL)) {
1119 		(void) ata_detach(dip, DDI_DETACH);
1120 		return (NULL);
1121 	}
1122 
1123 	ata_ctlp->ac_flags |= AC_GHD_INIT;
1124 	return (ata_ctlp);
1125 }
1126 
1127 /* destroy a controller */
1128 
1129 static void
ata_destroy_controller(dev_info_t * dip)1130 ata_destroy_controller(
1131 	dev_info_t *dip)
1132 {
1133 	ata_ctl_t *ata_ctlp;
1134 	int	instance;
1135 
1136 	ADBG_TRACE(("ata_destroy_controller entered\n"));
1137 
1138 	instance = ddi_get_instance(dip);
1139 	ata_ctlp = ddi_get_soft_state(ata_state, instance);
1140 
1141 	if (ata_ctlp == NULL)
1142 		return;
1143 
1144 	/* destroy ghd */
1145 	if (ata_ctlp->ac_flags & AC_GHD_INIT)
1146 		ghd_unregister(&ata_ctlp->ac_ccc);
1147 
1148 	/* free the pciide buffer (if any) */
1149 	ata_pciide_free(ata_ctlp);
1150 
1151 	/* destroy controller struct */
1152 	kmem_free(ata_ctlp->ac_arq_pktp, sizeof (ata_pkt_t));
1153 	ddi_soft_state_free(ata_state, instance);
1154 
1155 }
1156 
1157 
1158 /*
1159  *
1160  * initialize a drive
1161  *
1162  */
1163 
1164 static ata_drv_t *
ata_init_drive(ata_ctl_t * ata_ctlp,uchar_t targ,uchar_t lun)1165 ata_init_drive(
1166 	ata_ctl_t	*ata_ctlp,
1167 	uchar_t		targ,
1168 	uchar_t		lun)
1169 {
1170 	static	char	 nec_260[]	= "NEC CD-ROM DRIVE";
1171 	ata_drv_t *ata_drvp;
1172 	struct ata_id	*aidp;
1173 	char	buf[80];
1174 	int	drive_type;
1175 	int	i;
1176 	int	valid_version = 0;
1177 
1178 	ADBG_TRACE(("ata_init_drive entered, targ = %d, lun = %d\n",
1179 	    targ, lun));
1180 
1181 	/* check if device already exists */
1182 
1183 	ata_drvp = CTL2DRV(ata_ctlp, targ, lun);
1184 
1185 	if (ata_drvp != NULL)
1186 		return (ata_drvp);
1187 
1188 	/* allocate new device structure */
1189 
1190 	ata_drvp = kmem_zalloc(sizeof (ata_drv_t), KM_SLEEP);
1191 	aidp = &ata_drvp->ad_id;
1192 
1193 	/*
1194 	 * set up drive struct
1195 	 */
1196 	ata_drvp->ad_ctlp = ata_ctlp;
1197 	ata_drvp->ad_pciide_dma = ATA_DMA_UNINITIALIZED;
1198 	ata_drvp->ad_targ = targ;
1199 	ata_drvp->ad_drive_bits =
1200 	    (ata_drvp->ad_targ == 0 ? ATDH_DRIVE0 : ATDH_DRIVE1);
1201 	/*
1202 	 * Add the LUN for SFF-8070i support
1203 	 */
1204 	ata_drvp->ad_lun = lun;
1205 	ata_drvp->ad_drive_bits |= ata_drvp->ad_lun;
1206 
1207 	/*
1208 	 * get drive type, side effect is to collect
1209 	 * IDENTIFY DRIVE data
1210 	 */
1211 
1212 	drive_type = ata_drive_type(ata_drvp->ad_drive_bits,
1213 	    ata_ctlp->ac_iohandle1,
1214 	    ata_ctlp->ac_ioaddr1,
1215 	    ata_ctlp->ac_iohandle2,
1216 	    ata_ctlp->ac_ioaddr2,
1217 	    aidp);
1218 
1219 	switch (drive_type) {
1220 	case ATA_DEV_NONE:
1221 		/* no drive found */
1222 		goto errout;
1223 	case ATA_DEV_ATAPI:
1224 		ata_drvp->ad_flags |= AD_ATAPI;
1225 		break;
1226 	case ATA_DEV_DISK:
1227 		ata_drvp->ad_flags |= AD_DISK;
1228 		break;
1229 	}
1230 
1231 	/*
1232 	 * swap bytes of all text fields
1233 	 */
1234 	if (!ata_strncmp(nec_260, aidp->ai_model, sizeof (aidp->ai_model))) {
1235 		swab(aidp->ai_drvser, aidp->ai_drvser,
1236 		    sizeof (aidp->ai_drvser));
1237 		swab(aidp->ai_fw, aidp->ai_fw,
1238 		    sizeof (aidp->ai_fw));
1239 		swab(aidp->ai_model, aidp->ai_model,
1240 		    sizeof (aidp->ai_model));
1241 	}
1242 
1243 	/*
1244 	 * Check if this drive has the Single Sector bug
1245 	 */
1246 
1247 	if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_1SECTOR))
1248 		ata_drvp->ad_flags |= AD_1SECTOR;
1249 	else
1250 		ata_drvp->ad_flags &= ~AD_1SECTOR;
1251 
1252 	if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_LBA48))
1253 		ata_drvp->ad_flags |= AD_BLLBA48;
1254 	else
1255 		ata_drvp->ad_flags &= ~AD_BLLBA48;
1256 
1257 	/* Check if this drive has the "revert to defaults" bug */
1258 	if (!ata_check_revert_to_defaults(ata_drvp))
1259 		ata_drvp->ad_flags |= AD_NORVRT;
1260 
1261 	/* Dump the drive info */
1262 	(void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model));
1263 	buf[sizeof (aidp->ai_model)-1] = '\0';
1264 	for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--)
1265 		buf[i] = '\0';
1266 
1267 	ATAPRT(("?\t%s device at targ %d, lun %d lastlun 0x%x\n",
1268 	    (ATAPIDRV(ata_drvp) ? "ATAPI":"IDE"),
1269 	    ata_drvp->ad_targ, ata_drvp->ad_lun, aidp->ai_lastlun));
1270 
1271 	ATAPRT(("?\tmodel %s\n", buf));
1272 
1273 	if (aidp->ai_majorversion != 0 && aidp->ai_majorversion != 0xffff) {
1274 		for (i = 14; i >= 2; i--) {
1275 			if (aidp->ai_majorversion & (1 << i)) {
1276 				valid_version = i;
1277 				break;
1278 			}
1279 		}
1280 		ATAPRT((
1281 		    "?\tATA/ATAPI-%d supported, majver 0x%x minver 0x%x\n",
1282 		    valid_version,
1283 		    aidp->ai_majorversion,
1284 		    aidp->ai_minorversion));
1285 	}
1286 
1287 	if (ata_capability_data) {
1288 
1289 		ATAPRT(("?\t\tstat %x, err %x\n",
1290 		    ddi_get8(ata_ctlp->ac_iohandle2,
1291 		    ata_ctlp->ac_altstatus),
1292 		    ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_error)));
1293 
1294 		ATAPRT(("?\t\tcfg 0x%x, cap 0x%x\n",
1295 		    aidp->ai_config,
1296 		    aidp->ai_cap));
1297 
1298 		/*
1299 		 * Be aware that ATA-6 and later drives may not provide valid
1300 		 * geometry information and other obsoleted info.
1301 		 * Select what is printed based on supported ATA model (skip
1302 		 * anything below ATA/ATAPI-3)
1303 		 */
1304 
1305 		if (valid_version == 0 || aidp->ai_majorversion <
1306 		    ATAC_MAJVER_6) {
1307 			/*
1308 			 * Supported version less then ATA-6
1309 			 */
1310 			ATAPRT(("?\t\tcyl %d, hd %d, sec/trk %d\n",
1311 			    aidp->ai_fixcyls,
1312 			    aidp->ai_heads,
1313 			    aidp->ai_sectors));
1314 		}
1315 		ATAPRT(("?\t\tmult1 0x%x, mult2 0x%x\n",
1316 		    aidp->ai_mult1,
1317 		    aidp->ai_mult2));
1318 		if (valid_version && aidp->ai_majorversion < ATAC_MAJVER_4) {
1319 			ATAPRT((
1320 			"?\t\tpiomode 0x%x, dmamode 0x%x, advpiomode 0x%x\n",
1321 			    aidp->ai_piomode,
1322 			    aidp->ai_dmamode,
1323 			    aidp->ai_advpiomode));
1324 		} else {
1325 			ATAPRT(("?\t\tadvpiomode 0x%x\n",
1326 			    aidp->ai_advpiomode));
1327 		}
1328 		ATAPRT(("?\t\tminpio %d, minpioflow %d\n",
1329 		    aidp->ai_minpio,
1330 		    aidp->ai_minpioflow));
1331 		if (valid_version && aidp->ai_majorversion >= ATAC_MAJVER_4 &&
1332 		    (aidp->ai_validinfo & ATAC_VALIDINFO_83)) {
1333 			ATAPRT(("?\t\tdwdma 0x%x, ultradma 0x%x\n",
1334 			    aidp->ai_dworddma,
1335 			    aidp->ai_ultradma));
1336 		} else {
1337 			ATAPRT(("?\t\tdwdma 0x%x\n",
1338 			    aidp->ai_dworddma));
1339 		}
1340 	}
1341 
1342 	if (ATAPIDRV(ata_drvp)) {
1343 		if (!atapi_init_drive(ata_drvp))
1344 			goto errout;
1345 	} else {
1346 		if (!ata_disk_init_drive(ata_drvp))
1347 			goto errout;
1348 	}
1349 
1350 	/*
1351 	 * store pointer in controller struct
1352 	 */
1353 	CTL2DRV(ata_ctlp, targ, lun) = ata_drvp;
1354 
1355 	/*
1356 	 * lock the drive's current settings in case I have to
1357 	 * reset the drive due to some sort of error
1358 	 */
1359 	(void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_DIS_REVPOD, 0);
1360 
1361 	return (ata_drvp);
1362 
1363 errout:
1364 	ata_uninit_drive(ata_drvp);
1365 	return (NULL);
1366 }
1367 
1368 /* destroy a drive */
1369 
1370 static void
ata_uninit_drive(ata_drv_t * ata_drvp)1371 ata_uninit_drive(
1372 	ata_drv_t *ata_drvp)
1373 {
1374 #if 0
1375 	ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp;
1376 #endif
1377 
1378 	ADBG_TRACE(("ata_uninit_drive entered\n"));
1379 
1380 #if 0
1381 	/*
1382 	 * DON'T DO THIS. disabling interrupts floats the IRQ line
1383 	 * which generates spurious interrupts
1384 	 */
1385 
1386 	/*
1387 	 * Select the correct drive
1388 	 */
1389 	ddi_put8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_drvhd,
1390 	    ata_drvp->ad_drive_bits);
1391 	ata_nsecwait(400);
1392 
1393 	/*
1394 	 * Disable interrupts from the drive
1395 	 */
1396 	ddi_put8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_devctl,
1397 	    (ATDC_D3 | ATDC_NIEN));
1398 #endif
1399 
1400 	/* interface specific clean-ups */
1401 
1402 	if (ata_drvp->ad_flags & AD_ATAPI)
1403 		atapi_uninit_drive(ata_drvp);
1404 	else if (ata_drvp->ad_flags & AD_DISK)
1405 		ata_disk_uninit_drive(ata_drvp);
1406 
1407 	/* free drive struct */
1408 
1409 	kmem_free(ata_drvp, sizeof (ata_drv_t));
1410 }
1411 
1412 
1413 /*
1414  * ata_drive_type()
1415  *
1416  * The timeout values and exact sequence of checking is critical
1417  * especially for atapi device detection, and should not be changed lightly.
1418  *
1419  */
1420 static int
ata_drive_type(uchar_t drvhd,ddi_acc_handle_t io_hdl1,caddr_t ioaddr1,ddi_acc_handle_t io_hdl2,caddr_t ioaddr2,struct ata_id * ata_id_bufp)1421 ata_drive_type(
1422 	uchar_t		 drvhd,
1423 	ddi_acc_handle_t io_hdl1,
1424 	caddr_t		 ioaddr1,
1425 	ddi_acc_handle_t io_hdl2,
1426 	caddr_t		 ioaddr2,
1427 	struct ata_id	*ata_id_bufp)
1428 {
1429 	uchar_t	status;
1430 
1431 	ADBG_TRACE(("ata_drive_type entered\n"));
1432 
1433 	/*
1434 	 * select the appropriate drive and LUN
1435 	 */
1436 	ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_DRVHD, drvhd);
1437 	ata_nsecwait(400);
1438 
1439 	/*
1440 	 * make certain the drive is selected, and wait for not busy
1441 	 */
1442 	(void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY, 0x7f, 0, 0x7f, 0,
1443 	    5 * 1000000);
1444 
1445 	status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS);
1446 
1447 	if (status & ATS_BSY) {
1448 		ADBG_TRACE(("ata_drive_type 0x%p 0x%x\n", ioaddr1, status));
1449 		return (ATA_DEV_NONE);
1450 	}
1451 
1452 	if (ata_disk_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp))
1453 		return (ATA_DEV_DISK);
1454 
1455 	/*
1456 	 * No disk, check for atapi unit.
1457 	 */
1458 	if (!atapi_signature(io_hdl1, ioaddr1)) {
1459 #ifndef ATA_DISABLE_ATAPI_1_7
1460 		/*
1461 		 * Check for old (but prevalent) atapi 1.7B
1462 		 * spec device, the only known example is the
1463 		 * NEC CDR-260 (not 260R which is (mostly) ATAPI 1.2
1464 		 * compliant). This device has no signature
1465 		 * and requires conversion from hex to BCD
1466 		 * for some scsi audio commands.
1467 		 */
1468 		if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) {
1469 			return (ATA_DEV_ATAPI);
1470 		}
1471 #endif
1472 		return (ATA_DEV_NONE);
1473 	}
1474 
1475 	if (atapi_id(io_hdl1, ioaddr1, io_hdl2, ioaddr2, ata_id_bufp)) {
1476 		return (ATA_DEV_ATAPI);
1477 	}
1478 
1479 	return (ATA_DEV_NONE);
1480 
1481 }
1482 
1483 /*
1484  * nsec-granularity time delay function
1485  */
1486 void
ata_nsecwait(clock_t count)1487 ata_nsecwait(clock_t count)
1488 {
1489 	extern int tsc_gethrtime_initted;
1490 
1491 	if (tsc_gethrtime_initted) {
1492 		hrtime_t end = gethrtime() + count;
1493 
1494 		while (gethrtime() < end) {
1495 			SMT_PAUSE();
1496 		}
1497 	} else {
1498 		drv_usecwait(1 + (count / 1000));
1499 	}
1500 }
1501 
1502 
1503 /*
1504  * Wait for a register of a controller to achieve a specific state.
1505  * To return normally, all the bits in the first sub-mask must be ON,
1506  * all the bits in the second sub-mask must be OFF.
1507  * If timeout_usec microseconds pass without the controller achieving
1508  * the desired bit configuration, we return TRUE, else FALSE.
1509  */
1510 
1511 int ata_usec_delay = 10;
1512 
1513 int
ata_wait(ddi_acc_handle_t io_hdl,caddr_t ioaddr,uchar_t onbits,uchar_t offbits,uint_t timeout_usec)1514 ata_wait(
1515 	ddi_acc_handle_t io_hdl,
1516 	caddr_t		ioaddr,
1517 	uchar_t		onbits,
1518 	uchar_t		offbits,
1519 	uint_t		timeout_usec)
1520 {
1521 	ushort_t val;
1522 	hrtime_t deadline = gethrtime() +
1523 	    (hrtime_t)timeout_usec * (NANOSEC / MICROSEC);
1524 
1525 
1526 	do  {
1527 		val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS);
1528 		if ((val & onbits) == onbits && (val & offbits) == 0)
1529 			return (TRUE);
1530 		drv_usecwait(ata_usec_delay);
1531 	} while (gethrtime() < deadline);
1532 
1533 	return (FALSE);
1534 }
1535 
1536 
1537 /*
1538  *
1539  * This is a slightly more complicated version that checks
1540  * for error conditions and bails-out rather than looping
1541  * until the timeout expires
1542  */
1543 int
ata_wait3(ddi_acc_handle_t io_hdl,caddr_t ioaddr,uchar_t onbits1,uchar_t offbits1,uchar_t failure_onbits2,uchar_t failure_offbits2,uchar_t failure_onbits3,uchar_t failure_offbits3,uint_t timeout_usec)1544 ata_wait3(
1545 	ddi_acc_handle_t io_hdl,
1546 	caddr_t		ioaddr,
1547 	uchar_t		onbits1,
1548 	uchar_t		offbits1,
1549 	uchar_t		failure_onbits2,
1550 	uchar_t		failure_offbits2,
1551 	uchar_t		failure_onbits3,
1552 	uchar_t		failure_offbits3,
1553 	uint_t		timeout_usec)
1554 {
1555 	ushort_t val;
1556 	hrtime_t deadline = gethrtime() +
1557 	    (hrtime_t)timeout_usec * (NANOSEC / MICROSEC);
1558 
1559 	do  {
1560 		val = ddi_get8(io_hdl, (uchar_t *)ioaddr + AT_ALTSTATUS);
1561 
1562 		/*
1563 		 * check for expected condition
1564 		 */
1565 		if ((val & onbits1) == onbits1 && (val & offbits1) == 0)
1566 			return (TRUE);
1567 
1568 		/*
1569 		 * check for error conditions
1570 		 */
1571 		if ((val & failure_onbits2) == failure_onbits2 &&
1572 		    (val & failure_offbits2) == 0) {
1573 			return (FALSE);
1574 		}
1575 
1576 		if ((val & failure_onbits3) == failure_onbits3 &&
1577 		    (val & failure_offbits3) == 0) {
1578 			return (FALSE);
1579 		}
1580 
1581 		drv_usecwait(ata_usec_delay);
1582 	} while (gethrtime() < deadline);
1583 
1584 	return (FALSE);
1585 }
1586 
1587 
1588 /*
1589  *
1590  * low level routine for ata_disk_id() and atapi_id()
1591  *
1592  */
1593 
1594 int
ata_id_common(uchar_t id_cmd,int expect_drdy,ddi_acc_handle_t io_hdl1,caddr_t ioaddr1,ddi_acc_handle_t io_hdl2,caddr_t ioaddr2,struct ata_id * aidp)1595 ata_id_common(
1596 	uchar_t		 id_cmd,
1597 	int		 expect_drdy,
1598 	ddi_acc_handle_t io_hdl1,
1599 	caddr_t		 ioaddr1,
1600 	ddi_acc_handle_t io_hdl2,
1601 	caddr_t		 ioaddr2,
1602 	struct ata_id	*aidp)
1603 {
1604 	uchar_t	status;
1605 
1606 	ADBG_TRACE(("ata_id_common entered\n"));
1607 
1608 	bzero(aidp, sizeof (struct ata_id));
1609 
1610 	/*
1611 	 * clear the features register
1612 	 */
1613 	ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_FEATURE, 0);
1614 
1615 	/*
1616 	 * Disable interrupts from the device.  When the ata
1617 	 * hardware is sharing its interrupt with another
1618 	 * device, the shared interrupt might have already been
1619 	 * unmasked in the interrupt controller and
1620 	 * triggering ata device interrupts will result in an
1621 	 * interrupt storm and a hung system.
1622 	 */
1623 	ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3 | ATDC_NIEN);
1624 
1625 	/*
1626 	 * issue IDENTIFY DEVICE or IDENTIFY PACKET DEVICE command
1627 	 */
1628 	ddi_put8(io_hdl1, (uchar_t *)ioaddr1 + AT_CMD, id_cmd);
1629 
1630 	/* wait for the busy bit to settle */
1631 	ata_nsecwait(400);
1632 
1633 	/*
1634 	 * read alternate status and check for conditions which
1635 	 * may indicate the drive is not present, to prevent getting
1636 	 * stuck in ata_wait3() below.
1637 	 */
1638 	status = ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS);
1639 
1640 	/*
1641 	 * 0x0, 0x7f, or ATS_DF can happen when no drive is present
1642 	 */
1643 	if ((status == 0x0) || (status == 0x7f) ||
1644 	    ((status & (ATS_BSY|ATS_DF)) == ATS_DF)) {
1645 		/* invalid status, can't be an ATA or ATAPI device */
1646 		return (FALSE);
1647 	}
1648 
1649 	/*
1650 	 * According to the ATA specification, some drives may have
1651 	 * to read the media to complete this command.  We need to
1652 	 * make sure we give them enough time to respond.
1653 	 */
1654 	(void) ata_wait3(io_hdl2, ioaddr2, 0, ATS_BSY,
1655 	    ATS_ERR, ATS_BSY, 0x7f, 0, 5 * 1000000);
1656 
1657 	/*
1658 	 * read the status byte and clear the pending interrupt
1659 	 */
1660 	status = ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_STATUS);
1661 
1662 	/*
1663 	 * this happens if there's no drive present
1664 	 */
1665 	if (status == 0xff || status == 0x7f) {
1666 		/* invalid status, can't be an ATA or ATAPI device */
1667 		return (FALSE);
1668 	}
1669 
1670 	if (status & ATS_BSY) {
1671 		ADBG_ERROR(("ata_id_common: BUSY status 0x%x error 0x%x\n",
1672 		    ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS),
1673 		    ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR)));
1674 		return (FALSE);
1675 	}
1676 
1677 	if (!(status & ATS_DRQ)) {
1678 		if (status & (ATS_ERR | ATS_DF)) {
1679 			return (FALSE);
1680 		}
1681 		/*
1682 		 * Give the drive another second to assert DRQ. Some older
1683 		 * drives de-assert BSY before asserting DRQ. Bail out
1684 		 * immediately if the status becomes 0x7f, which is invalid
1685 		 * value. It can happen when no drive is present.
1686 		 */
1687 		if (!ata_wait3(io_hdl2, ioaddr2, ATS_DRQ, ATS_BSY, 0x7f,
1688 		    ATS_BSY, 0x7f, ATS_BSY, 1000000)) {
1689 			ADBG_WARN(("ata_id_common: "
1690 			    "!DRQ status 0x%x error 0x%x\n",
1691 			    ddi_get8(io_hdl2, (uchar_t *)ioaddr2 +AT_ALTSTATUS),
1692 			    ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR)));
1693 			return (FALSE);
1694 		}
1695 	}
1696 
1697 	/*
1698 	 * transfer the data
1699 	 */
1700 	ddi_rep_get16(io_hdl1, (ushort_t *)aidp, (ushort_t *)ioaddr1 + AT_DATA,
1701 	    NBPSCTR >> 1, DDI_DEV_NO_AUTOINCR);
1702 
1703 	/* wait for the busy bit to settle */
1704 	ata_nsecwait(400);
1705 
1706 
1707 	/*
1708 	 * Wait for the drive to recognize I've read all the data.
1709 	 * Some drives have been observed to take as much as 3msec to
1710 	 * deassert DRQ after reading the data; allow 1 sec just in case.
1711 	 *
1712 	 * Note: some non-compliant ATAPI drives (e.g., NEC Multispin 6V,
1713 	 * CDR-1350A) don't assert DRDY. If we've made it this far we can
1714 	 * safely ignore the DRDY bit since the ATAPI Packet command
1715 	 * actually doesn't require it to ever be asserted.
1716 	 *
1717 	 * Bail out immediately if the status becomes 0x7f, which is invalid
1718 	 * value. It can happen when no drive is present.
1719 	 *
1720 	 */
1721 	if (!ata_wait3(io_hdl2, ioaddr2, (uchar_t)(expect_drdy ? ATS_DRDY : 0),
1722 	    (ATS_BSY | ATS_DRQ), 0x7f, ATS_BSY, 0x7f, ATS_BSY, 1000000)) {
1723 		ADBG_WARN(("ata_id_common: bad status 0x%x error 0x%x\n",
1724 		    ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS),
1725 		    ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR)));
1726 		return (FALSE);
1727 	}
1728 
1729 	/*
1730 	 * Check to see if the command aborted. This happens if
1731 	 * an IDENTIFY DEVICE command is issued to an ATAPI PACKET device,
1732 	 * or if an IDENTIFY PACKET DEVICE command is issued to an ATA
1733 	 * (non-PACKET) device.
1734 	 */
1735 	if (status & (ATS_DF | ATS_ERR)) {
1736 		ADBG_WARN(("ata_id_common: status 0x%x error 0x%x \n",
1737 		    ddi_get8(io_hdl2, (uchar_t *)ioaddr2 + AT_ALTSTATUS),
1738 		    ddi_get8(io_hdl1, (uchar_t *)ioaddr1 + AT_ERROR)));
1739 		return (FALSE);
1740 	}
1741 	return (TRUE);
1742 }
1743 
1744 
1745 /*
1746  * Low level routine to issue a non-data command and busy wait for
1747  * the completion status.
1748  */
1749 
1750 int
ata_command(ata_ctl_t * ata_ctlp,ata_drv_t * ata_drvp,int expect_drdy,int silent,uint_t busy_wait,uchar_t cmd,uchar_t feature,uchar_t count,uchar_t sector,uchar_t head,uchar_t cyl_low,uchar_t cyl_hi)1751 ata_command(
1752 	ata_ctl_t *ata_ctlp,
1753 	ata_drv_t *ata_drvp,
1754 	int		 expect_drdy,
1755 	int		 silent,
1756 	uint_t		 busy_wait,
1757 	uchar_t		 cmd,
1758 	uchar_t		 feature,
1759 	uchar_t		 count,
1760 	uchar_t		 sector,
1761 	uchar_t		 head,
1762 	uchar_t		 cyl_low,
1763 	uchar_t		 cyl_hi)
1764 {
1765 	ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1;
1766 	ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2;
1767 	uchar_t		 status;
1768 
1769 	/* select the drive */
1770 	ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ata_drvp->ad_drive_bits);
1771 	ata_nsecwait(400);
1772 
1773 	/* make certain the drive selected */
1774 	if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2,
1775 	    (uchar_t)(expect_drdy ? ATS_DRDY : 0),
1776 	    ATS_BSY, busy_wait)) {
1777 		ADBG_ERROR(("ata_command: select failed "
1778 		    "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x  "
1779 		    "S 0x%x H 0x%x CL 0x%x CH 0x%x\n",
1780 		    expect_drdy, cmd, feature, count,
1781 		    sector, head, cyl_low, cyl_hi));
1782 		return (FALSE);
1783 	}
1784 
1785 	/*
1786 	 * set all the regs
1787 	 */
1788 	ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, (head | ata_drvp->ad_drive_bits));
1789 	ddi_put8(io_hdl1, ata_ctlp->ac_sect, sector);
1790 	ddi_put8(io_hdl1, ata_ctlp->ac_count, count);
1791 	ddi_put8(io_hdl1, ata_ctlp->ac_lcyl, cyl_low);
1792 	ddi_put8(io_hdl1, ata_ctlp->ac_hcyl, cyl_hi);
1793 	ddi_put8(io_hdl1, ata_ctlp->ac_feature, feature);
1794 
1795 	/* send the command */
1796 	ddi_put8(io_hdl1, ata_ctlp->ac_cmd, cmd);
1797 
1798 	/* wait for the busy bit to settle */
1799 	ata_nsecwait(400);
1800 
1801 	/* wait for not busy */
1802 	if (!ata_wait(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY, busy_wait)) {
1803 		ADBG_ERROR(("ata_command: BSY too long!"
1804 		    "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x  "
1805 		    "S 0x%x H 0x%x CL 0x%x CH 0x%x\n",
1806 		    expect_drdy, cmd, feature, count,
1807 		    sector, head, cyl_low, cyl_hi));
1808 		return (FALSE);
1809 	}
1810 
1811 	/*
1812 	 * wait for DRDY before continuing
1813 	 */
1814 	(void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2,
1815 	    ATS_DRDY, ATS_BSY, /* okay */
1816 	    ATS_ERR, ATS_BSY, /* cmd failed */
1817 	    ATS_DF, ATS_BSY, /* drive failed */
1818 	    busy_wait);
1819 
1820 	/* read status to clear IRQ, and check for error */
1821 	status =  ddi_get8(io_hdl1, ata_ctlp->ac_status);
1822 
1823 	if ((status & (ATS_BSY | ATS_DF | ATS_ERR)) == 0)
1824 		return (TRUE);
1825 
1826 	if (!silent) {
1827 		ADBG_ERROR(("ata_command status 0x%x error 0x%x "
1828 		    "DRDY 0x%x CMD 0x%x F 0x%x N 0x%x  "
1829 		    "S 0x%x H 0x%x CL 0x%x CH 0x%x\n",
1830 		    ddi_get8(io_hdl1, ata_ctlp->ac_status),
1831 		    ddi_get8(io_hdl1, ata_ctlp->ac_error),
1832 		    expect_drdy, cmd, feature, count,
1833 		    sector, head, cyl_low, cyl_hi));
1834 	}
1835 	return (FALSE);
1836 }
1837 
1838 
1839 
1840 /*
1841  *
1842  * Issue a SET FEATURES command
1843  *
1844  */
1845 
1846 int
ata_set_feature(ata_ctl_t * ata_ctlp,ata_drv_t * ata_drvp,uchar_t feature,uchar_t value)1847 ata_set_feature(
1848 	ata_ctl_t *ata_ctlp,
1849 	ata_drv_t *ata_drvp,
1850 	uchar_t    feature,
1851 	uchar_t    value)
1852 {
1853 	int		 rc;
1854 
1855 	rc = ata_command(ata_ctlp, ata_drvp, TRUE, TRUE, ata_set_feature_wait,
1856 	    ATC_SET_FEAT, feature, value, 0, 0, 0, 0);
1857 	/* feature, count, sector, head, cyl_low, cyl_hi */
1858 
1859 	if (rc) {
1860 		return (TRUE);
1861 	}
1862 
1863 	ADBG_ERROR(("?ata_set_feature: (0x%x,0x%x) failed\n", feature, value));
1864 	return (FALSE);
1865 }
1866 
1867 
1868 
1869 /*
1870  *
1871  * Issue a FLUSH CACHE command
1872  *
1873  */
1874 
1875 static int
ata_flush_cache(ata_ctl_t * ata_ctlp,ata_drv_t * ata_drvp)1876 ata_flush_cache(
1877 	ata_ctl_t *ata_ctlp,
1878 	ata_drv_t *ata_drvp)
1879 {
1880 	/* this command is optional so fail silently */
1881 	return (ata_command(ata_ctlp, ata_drvp, TRUE, TRUE,
1882 	    ata_flush_cache_wait,
1883 	    ATC_FLUSH_CACHE, 0, 0, 0, 0, 0, 0));
1884 }
1885 
1886 /*
1887  * ata_setup_ioaddr()
1888  *
1889  * Map the device registers and return the handles.
1890  *
1891  * If this is a ISA-ATA controller then only two handles are
1892  * initialized and returned.
1893  *
1894  * If this is a PCI-IDE controller than a third handle (for the
1895  * PCI-IDE Bus Mastering registers) is initialized and returned.
1896  *
1897  */
1898 
1899 static int
ata_setup_ioaddr(dev_info_t * dip,ddi_acc_handle_t * handle1p,caddr_t * addr1p,ddi_acc_handle_t * handle2p,caddr_t * addr2p,ddi_acc_handle_t * bm_hdlp,caddr_t * bm_addrp)1900 ata_setup_ioaddr(
1901 	dev_info_t	 *dip,
1902 	ddi_acc_handle_t *handle1p,
1903 	caddr_t		 *addr1p,
1904 	ddi_acc_handle_t *handle2p,
1905 	caddr_t		 *addr2p,
1906 	ddi_acc_handle_t *bm_hdlp,
1907 	caddr_t		 *bm_addrp)
1908 {
1909 	ddi_device_acc_attr_t dev_attr;
1910 	int	 rnumber;
1911 	int	 rc;
1912 	off_t	 regsize;
1913 
1914 	/*
1915 	 * Make certain the controller is enabled and its regs are map-able
1916 	 *
1917 	 */
1918 	rc = ddi_dev_regsize(dip, 0, &regsize);
1919 	if (rc != DDI_SUCCESS || regsize <= AT_CMD) {
1920 		ADBG_INIT(("ata_setup_ioaddr(1): rc %d regsize %lld\n",
1921 		    rc, (long long)regsize));
1922 		return (FALSE);
1923 	}
1924 
1925 	rc = ddi_dev_regsize(dip, 1, &regsize);
1926 	if (rc != DDI_SUCCESS || regsize <= AT_ALTSTATUS) {
1927 		ADBG_INIT(("ata_setup_ioaddr(2): rc %d regsize %lld\n",
1928 		    rc, (long long)regsize));
1929 		return (FALSE);
1930 	}
1931 
1932 	/*
1933 	 * setup the device attribute structure for little-endian,
1934 	 * strict ordering access.
1935 	 */
1936 	dev_attr.devacc_attr_version = DDI_DEVICE_ATTR_V0;
1937 	dev_attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC;
1938 	dev_attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC;
1939 
1940 	*handle1p = NULL;
1941 	*handle2p = NULL;
1942 	*bm_hdlp = NULL;
1943 
1944 	/*
1945 	 * Determine whether this is a ISA, PNP-ISA, or PCI-IDE device
1946 	 */
1947 	if (ddi_prop_exists(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "pnp-csn")) {
1948 		/* it's PNP-ISA, skip over the extra reg tuple */
1949 		rnumber = 1;
1950 		goto not_pciide;
1951 	}
1952 
1953 	/* else, it's ISA or PCI-IDE, check further */
1954 	rnumber = 0;
1955 
1956 	if (!ata_is_pci(dip)) {
1957 		/*
1958 		 * If it's not a PCI-IDE, there are only two reg tuples
1959 		 * and the first one contains the I/O base (170 or 1f0)
1960 		 * rather than the controller instance number.
1961 		 */
1962 		ADBG_TRACE(("ata_setup_ioaddr !pci-ide\n"));
1963 		goto not_pciide;
1964 	}
1965 
1966 
1967 	/*
1968 	 * Map the correct half of the PCI-IDE Bus Master registers.
1969 	 * There's a single BAR that maps these registers for both
1970 	 * controller's in a dual-controller chip and it's upto my
1971 	 * parent nexus, pciide, to adjust which (based on my instance
1972 	 * number) half this call maps.
1973 	 */
1974 	rc = ddi_dev_regsize(dip, 2, &regsize);
1975 	if (rc != DDI_SUCCESS || regsize < 8) {
1976 		ADBG_INIT(("ata_setup_ioaddr(3): rc %d regsize %lld\n",
1977 		    rc, (long long)regsize));
1978 		goto not_pciide;
1979 	}
1980 
1981 	rc = ddi_regs_map_setup(dip, 2, bm_addrp, 0, 0, &dev_attr, bm_hdlp);
1982 
1983 	if (rc != DDI_SUCCESS) {
1984 		/* map failed, try to use in non-pci-ide mode */
1985 		ADBG_WARN(("ata_setup_ioaddr bus master map failed, rc=0x%x\n",
1986 		    rc));
1987 		*bm_hdlp = NULL;
1988 	}
1989 
1990 not_pciide:
1991 	/*
1992 	 * map the lower command block registers
1993 	 */
1994 
1995 	rc = ddi_regs_map_setup(dip, rnumber, addr1p, 0, 0, &dev_attr,
1996 	    handle1p);
1997 
1998 	if (rc != DDI_SUCCESS) {
1999 		cmn_err(CE_WARN, "ata: reg tuple 0 map failed, rc=0x%x\n", rc);
2000 		goto out1;
2001 	}
2002 
2003 	/*
2004 	 * If the controller is being used in compatibility mode
2005 	 * via /devices/isa/ata@1,{1f0,1f0}/..., the reg property
2006 	 * will specify zeros for the I/O ports for the PCI
2007 	 * instance.
2008 	 */
2009 	if (*addr1p == 0) {
2010 		ADBG_TRACE(("ata_setup_ioaddr ioaddr1 0\n"));
2011 		goto out2;
2012 	}
2013 
2014 	/*
2015 	 * map the upper control block registers
2016 	 */
2017 	rc = ddi_regs_map_setup(dip, rnumber + 1, addr2p, 0, 0, &dev_attr,
2018 	    handle2p);
2019 	if (rc == DDI_SUCCESS)
2020 		return (TRUE);
2021 
2022 	cmn_err(CE_WARN, "ata: reg tuple 1 map failed, rc=0x%x", rc);
2023 
2024 out2:
2025 	if (*handle1p != NULL) {
2026 		ddi_regs_map_free(handle1p);
2027 		*handle1p = NULL;
2028 	}
2029 
2030 out1:
2031 	if (*bm_hdlp != NULL) {
2032 		ddi_regs_map_free(bm_hdlp);
2033 		*bm_hdlp = NULL;
2034 	}
2035 	return (FALSE);
2036 
2037 }
2038 
2039 /*
2040  *
2041  * Currently, the only supported controllers are ones which
2042  * support the SFF-8038 Bus Mastering spec.
2043  *
2044  * Check the parent node's IEEE 1275 class-code property to
2045  * determine if it's an PCI-IDE instance which supports SFF-8038
2046  * Bus Mastering. It's perfectly valid to have a PCI-IDE controller
2047  * that doesn't do Bus Mastering. In that case, my interrupt handler
2048  * only uses the interrupt latch bit in PCI-IDE status register.
2049  * The assumption is that the programming interface byte of the
2050  * class-code property reflects the bus master DMA capability of
2051  * the controller.
2052  *
2053  * Whether the drive support supports the DMA option still needs
2054  * to be checked later. Each individual request also has to be
2055  * checked for alignment and size to decide whether to use the
2056  * DMA transfer mode.
2057  */
2058 
2059 static void
ata_init_pciide(dev_info_t * dip,ata_ctl_t * ata_ctlp)2060 ata_init_pciide(
2061 	dev_info_t	 *dip,
2062 	ata_ctl_t *ata_ctlp)
2063 {
2064 	uint_t	 class_code;
2065 	uchar_t	 status;
2066 
2067 	ata_cntrl_DMA_sel_msg = NULL;
2068 
2069 	if (ata_ctlp->ac_bmhandle == NULL) {
2070 		ata_ctlp->ac_pciide = FALSE;
2071 		ata_ctlp->ac_pciide_bm = FALSE;
2072 		ata_cntrl_DMA_sel_msg = "cntrl not Bus Master DMA capable";
2073 		return;
2074 	}
2075 
2076 	/*
2077 	 * check if it's a known bogus PCI-IDE chip
2078 	 */
2079 	if (ata_check_pciide_blacklist(dip, ATA_BL_BOGUS)) {
2080 		ADBG_WARN(("ata_setup_ioaddr pci-ide blacklist\n"));
2081 		ata_ctlp->ac_pciide = FALSE;
2082 		ata_ctlp->ac_pciide_bm = FALSE;
2083 		ata_cntrl_DMA_sel_msg = "cntrl blacklisted";
2084 		return;
2085 	}
2086 	ata_ctlp->ac_pciide = TRUE;
2087 
2088 	if (ata_check_pciide_blacklist(dip, ATA_BL_BMSTATREG_PIO_BROKEN)) {
2089 		ata_ctlp->ac_flags |= AC_BMSTATREG_PIO_BROKEN;
2090 	}
2091 
2092 	/*
2093 	 * check for a PCI-IDE chip with a broken DMA engine
2094 	 */
2095 	if (ata_check_pciide_blacklist(dip, ATA_BL_NODMA)) {
2096 		ata_ctlp->ac_pciide_bm = FALSE;
2097 		ata_cntrl_DMA_sel_msg =
2098 		    "cntrl blacklisted/DMA engine broken";
2099 		return;
2100 	}
2101 
2102 	/*
2103 	 * Check the Programming Interface register to determine
2104 	 * if this device supports PCI-IDE Bus Mastering. Some PCI-IDE
2105 	 * devices don't support Bus Mastering or DMA.
2106 	 * Since we are dealing with pre-qualified pci-ide controller,
2107 	 * check programming interface byte only.
2108 	 */
2109 
2110 	class_code = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip),
2111 	    DDI_PROP_DONTPASS, "class-code", 0);
2112 	if ((class_code & PCIIDE_BM_CAP_MASK) != PCIIDE_BM_CAP_MASK) {
2113 		ata_ctlp->ac_pciide_bm = FALSE;
2114 		ata_cntrl_DMA_sel_msg =
2115 		    "cntrl not Bus Master DMA capable";
2116 		return;
2117 	}
2118 
2119 	/*
2120 	 * Avoid doing DMA on "simplex" chips which share hardware
2121 	 * between channels
2122 	 */
2123 	status = ddi_get8(ata_ctlp->ac_bmhandle,
2124 	    (uchar_t *)ata_ctlp->ac_bmaddr + PCIIDE_BMISX_REG);
2125 	/*
2126 	 * Some motherboards have CSB5's that are wired "to emulate CSB4 mode".
2127 	 * In such a mode, the simplex bit is asserted,  but in fact testing
2128 	 * on such a motherboard has shown that the devices are not simplex
2129 	 * -- DMA can be used on both channels concurrently with no special
2130 	 * considerations.  For chips like this, we have the ATA_BL_NO_SIMPLEX
2131 	 * flag set to indicate that the value of the simplex bit can be
2132 	 * ignored.
2133 	 */
2134 
2135 	if (status & PCIIDE_BMISX_SIMPLEX) {
2136 		if (ata_check_pciide_blacklist(dip, ATA_BL_NO_SIMPLEX)) {
2137 			cmn_err(CE_WARN, "Ignoring false simplex bit \n");
2138 
2139 		} else {
2140 
2141 			int simplex_dma_channel, *rp, proplen, channel;
2142 			int dma_on = FALSE;
2143 
2144 			/*
2145 			 * By default,use DMA on channel 0 and PIO on channel
2146 			 * 1.  This can be switched by setting
2147 			 * ata-simplex-dma-channel to:
2148 			 *	0  DMA on channel 0 (default without this
2149 			 *			    property)
2150 			 *	1  DMA on channel 1
2151 			 *	any other value: DMA off on both channels.
2152 			 */
2153 			simplex_dma_channel = ata_prop_lookup_int(DDI_DEV_T_ANY,
2154 			    ata_ctlp->ac_dip, 0, "ata-simplex-dma-channel", 0);
2155 
2156 			if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY,
2157 			    ata_ctlp->ac_dip, DDI_PROP_DONTPASS, "reg", &rp,
2158 			    (uint_t *)&proplen) == DDI_PROP_SUCCESS) {
2159 
2160 				channel = *rp;
2161 				ddi_prop_free(rp);
2162 
2163 				if (simplex_dma_channel == channel) {
2164 					cmn_err(CE_CONT, "?ata: simplex "
2165 					    "controller.  DMA on channel"
2166 					    "  %d PIO on channel %d",
2167 					    channel, channel ? 0:1);
2168 					dma_on = TRUE;
2169 				} else {
2170 					ata_cntrl_DMA_sel_msg =
2171 					    "simplex controller";
2172 				}
2173 			}
2174 
2175 			if (dma_on == FALSE) {
2176 				ata_ctlp->ac_pciide_bm = FALSE;
2177 
2178 				return;
2179 			}
2180 		}
2181 	}
2182 
2183 	/*
2184 	 * It's a compatible PCI-IDE Bus Mastering controller,
2185 	 * allocate and map the DMA Scatter/Gather list (PRDE table).
2186 	 */
2187 	if (ata_pciide_alloc(dip, ata_ctlp))
2188 		ata_ctlp->ac_pciide_bm = TRUE;
2189 	else {
2190 		ata_ctlp->ac_pciide_bm = FALSE;
2191 		ata_cntrl_DMA_sel_msg = "unable to init DMA S/G list";
2192 	}
2193 }
2194 
2195 /*
2196  *
2197  * Determine whether to enable DMA support for this drive.
2198  * The controller and the drive both have to support DMA.
2199  * The controller's capabilities were already checked in
2200  * ata_init_pciide(), now just check the drive's capabilities.
2201  *
2202  */
2203 
2204 static int
ata_init_drive_pcidma(ata_ctl_t * ata_ctlp,ata_drv_t * ata_drvp,dev_info_t * tdip)2205 ata_init_drive_pcidma(
2206 	ata_ctl_t *ata_ctlp,
2207 	ata_drv_t *ata_drvp,
2208 	dev_info_t *tdip)
2209 {
2210 	boolean_t dma;
2211 	boolean_t cd_dma;
2212 	boolean_t disk_dma;
2213 	boolean_t atapi_dma;
2214 	int ata_options;
2215 
2216 	ata_dev_DMA_sel_msg = NULL;
2217 
2218 	if (ata_ctlp->ac_pciide_bm != TRUE) {
2219 		ata_dev_DMA_sel_msg =
2220 		    "controller is not Bus Master capable";
2221 
2222 		return (ATA_DMA_OFF);
2223 	}
2224 
2225 	ata_options = ddi_prop_get_int(DDI_DEV_T_ANY, ata_ctlp->ac_dip,
2226 	    0, "ata-options", 0);
2227 
2228 	if (!(ata_options & ATA_OPTIONS_DMA)) {
2229 		/*
2230 		 * Either the ata-options property was not found or
2231 		 * DMA is not enabled by this property
2232 		 */
2233 		ata_dev_DMA_sel_msg =
2234 		    "disabled by \"ata-options\" property";
2235 
2236 		return (ATA_DMA_OFF);
2237 	}
2238 
2239 	if (ata_check_drive_blacklist(&ata_drvp->ad_id, ATA_BL_NODMA)) {
2240 		ata_dev_DMA_sel_msg = "device not DMA capable; blacklisted";
2241 
2242 		return (ATA_DMA_OFF);
2243 	}
2244 
2245 	/*
2246 	 * DMA mode is mandatory on ATA-3 (or newer) drives but is
2247 	 * optional on ATA-2 (or older) drives.
2248 	 *
2249 	 * On ATA-2 drives the ai_majorversion word will probably
2250 	 * be 0xffff or 0x0000, check the (now obsolete) DMA bit in
2251 	 * the capabilities word instead. The order of these tests
2252 	 * is important since an ATA-3 drive doesn't have to set
2253 	 * the DMA bit in the capabilities word.
2254 	 *
2255 	 */
2256 
2257 	if (!((ata_drvp->ad_id.ai_majorversion & 0x8000) == 0 &&
2258 	    ata_drvp->ad_id.ai_majorversion >= (1 << 2)) &&
2259 	    !(ata_drvp->ad_id.ai_cap & ATAC_DMA_SUPPORT)) {
2260 		ata_dev_DMA_sel_msg = "device not DMA capable";
2261 
2262 		return (ATA_DMA_OFF);
2263 	}
2264 
2265 	/*
2266 	 * Disable DMA for ATAPI devices on controllers known to
2267 	 * have trouble with ATAPI DMA
2268 	 */
2269 
2270 	if (ATAPIDRV(ata_drvp)) {
2271 		if (ata_check_pciide_blacklist(ata_ctlp->ac_dip,
2272 		    ATA_BL_ATAPI_NODMA)) {
2273 			ata_dev_DMA_sel_msg =
2274 			    "controller incapable of DMA for ATAPI device";
2275 
2276 			return (ATA_DMA_OFF);
2277 		}
2278 	}
2279 	dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip,
2280 	    0, "ata-dma-enabled", TRUE);
2281 	disk_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip,
2282 	    0, "ata-disk-dma-enabled", TRUE);
2283 	cd_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip,
2284 	    0, "atapi-cd-dma-enabled", FALSE);
2285 	atapi_dma = ata_prop_lookup_int(DDI_DEV_T_ANY, tdip,
2286 	    0, "atapi-other-dma-enabled", TRUE);
2287 
2288 	if (dma == FALSE) {
2289 		cmn_err(CE_CONT, "?ata_init_drive_pcidma: "
2290 		    "DMA disabled by \"ata-dma-enabled\" property");
2291 		ata_dev_DMA_sel_msg = "disabled by prop ata-dma-enabled";
2292 
2293 		return (ATA_DMA_OFF);
2294 	}
2295 
2296 	if (IS_CDROM(ata_drvp) == TRUE) {
2297 		if (cd_dma == FALSE) {
2298 			ata_dev_DMA_sel_msg =
2299 			    "disabled.  Control with \"atapi-cd-dma-enabled\""
2300 			    " property";
2301 
2302 			return (ATA_DMA_OFF);
2303 		}
2304 
2305 	} else if (ATAPIDRV(ata_drvp) == FALSE) {
2306 		if (disk_dma == FALSE) {
2307 			ata_dev_DMA_sel_msg =
2308 			    "disabled by \"ata-disk-dma-enabled\" property";
2309 
2310 			return (ATA_DMA_OFF);
2311 		}
2312 
2313 	} else if (atapi_dma == FALSE) {
2314 			ata_dev_DMA_sel_msg =
2315 			    "disabled by \"atapi-other-dma-enabled\" property";
2316 
2317 			return (ATA_DMA_OFF);
2318 	}
2319 
2320 	return (ATA_DMA_ON);
2321 }
2322 
2323 
2324 
2325 /*
2326  * this compare routine squeezes out extra blanks and
2327  * returns TRUE if p1 matches the leftmost substring of p2
2328  */
2329 
2330 static int
ata_strncmp(char * p1,char * p2,int cnt)2331 ata_strncmp(
2332 	char *p1,
2333 	char *p2,
2334 	int cnt)
2335 {
2336 
2337 	for (;;) {
2338 		/*
2339 		 * skip over any extra blanks in both strings
2340 		 */
2341 		while (*p1 != '\0' && *p1 == ' ')
2342 			p1++;
2343 
2344 		while (cnt != 0 && *p2 == ' ') {
2345 			p2++;
2346 			cnt--;
2347 		}
2348 
2349 		/*
2350 		 * compare the two strings
2351 		 */
2352 
2353 		if (cnt == 0 || *p1 != *p2)
2354 			break;
2355 
2356 		while (cnt > 0 && *p1 == *p2) {
2357 			p1++;
2358 			p2++;
2359 			cnt--;
2360 		}
2361 
2362 	}
2363 
2364 	/* return TRUE if both strings ended at same point */
2365 	return ((*p1 == '\0') ? TRUE : FALSE);
2366 }
2367 
2368 /*
2369  * Per PSARC/1997/281 create variant="atapi" property (if necessary)
2370  * on the target's dev_info node. Currently, the sd target driver
2371  * is the only driver which refers to this property.
2372  *
2373  * If the flag ata_id_debug is set also create the
2374  * the "ata" or "atapi" property on the target's dev_info node
2375  *
2376  */
2377 
2378 int
ata_prop_create(dev_info_t * tgt_dip,ata_drv_t * ata_drvp,char * name)2379 ata_prop_create(
2380 	dev_info_t *tgt_dip,
2381 	ata_drv_t  *ata_drvp,
2382 	char	   *name)
2383 {
2384 	int	rc;
2385 
2386 	ADBG_TRACE(("ata_prop_create 0x%p 0x%p %s\n", tgt_dip, ata_drvp, name));
2387 
2388 	if (strcmp("atapi", name) == 0) {
2389 		rc =  ndi_prop_update_string(DDI_DEV_T_NONE, tgt_dip,
2390 		    "variant", name);
2391 		if (rc != DDI_PROP_SUCCESS)
2392 			return (FALSE);
2393 	}
2394 
2395 	if (!ata_id_debug)
2396 		return (TRUE);
2397 
2398 	rc =  ndi_prop_update_byte_array(DDI_DEV_T_NONE, tgt_dip, name,
2399 	    (uchar_t *)&ata_drvp->ad_id, sizeof (ata_drvp->ad_id));
2400 	if (rc != DDI_PROP_SUCCESS) {
2401 		ADBG_ERROR(("ata_prop_create failed, rc=%d\n", rc));
2402 	}
2403 	return (TRUE);
2404 }
2405 
2406 
2407 /* *********************************************************************** */
2408 /* *********************************************************************** */
2409 /* *********************************************************************** */
2410 
2411 /*
2412  * This state machine doesn't implement the ATAPI Optional Overlap
2413  * feature. You need that feature to efficiently support ATAPI
2414  * tape drives. See the 1394-ATA Tailgate spec (D97107), Figure 24,
2415  * for an example of how to add the necessary additional NextActions
2416  * and NextStates to this FSM and the atapi_fsm, in order to support
2417  * the Overlap Feature.
2418  */
2419 
2420 
2421 uchar_t ata_ctlr_fsm_NextAction[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = {
2422 /* --------------------- next action --------------------- | - current - */
2423 /* start0 --- start1 ---- intr ------ fini --- reset --- */
2424 { AC_START,   AC_START,	  AC_NADA,    AC_NADA, AC_RESET_I }, /* idle	 */
2425 { AC_BUSY,    AC_BUSY,	  AC_INTR,    AC_FINI, AC_RESET_A }, /* active0  */
2426 { AC_BUSY,    AC_BUSY,	  AC_INTR,    AC_FINI, AC_RESET_A }, /* active1  */
2427 };
2428 
2429 uchar_t ata_ctlr_fsm_NextState[ATA_CTLR_NSTATES][ATA_CTLR_NFUNCS] = {
2430 
2431 /* --------------------- next state --------------------- | - current - */
2432 /* start0 --- start1 ---- intr ------ fini --- reset --- */
2433 { AS_ACTIVE0, AS_ACTIVE1, AS_IDLE,    AS_IDLE, AS_IDLE	  }, /* idle    */
2434 { AS_ACTIVE0, AS_ACTIVE0, AS_ACTIVE0, AS_IDLE, AS_ACTIVE0 }, /* active0 */
2435 { AS_ACTIVE1, AS_ACTIVE1, AS_ACTIVE1, AS_IDLE, AS_ACTIVE1 }, /* active1 */
2436 };
2437 
2438 
2439 static int
ata_ctlr_fsm(uchar_t fsm_func,ata_ctl_t * ata_ctlp,ata_drv_t * ata_drvp,ata_pkt_t * ata_pktp,int * DoneFlgp)2440 ata_ctlr_fsm(
2441 	uchar_t		 fsm_func,
2442 	ata_ctl_t	*ata_ctlp,
2443 	ata_drv_t	*ata_drvp,
2444 	ata_pkt_t	*ata_pktp,
2445 	int		*DoneFlgp)
2446 {
2447 	uchar_t	   action;
2448 	uchar_t	   current_state;
2449 	uchar_t	   next_state;
2450 	int	   rc;
2451 
2452 	current_state = ata_ctlp->ac_state;
2453 	action = ata_ctlr_fsm_NextAction[current_state][fsm_func];
2454 	next_state = ata_ctlr_fsm_NextState[current_state][fsm_func];
2455 
2456 	/*
2457 	 * Set the controller's new state
2458 	 */
2459 	ata_ctlp->ac_state = next_state;
2460 	switch (action) {
2461 
2462 	case AC_BUSY:
2463 		return (ATA_FSM_RC_BUSY);
2464 
2465 	case AC_NADA:
2466 		return (ATA_FSM_RC_OKAY);
2467 
2468 	case AC_START:
2469 		ASSERT(ata_ctlp->ac_active_pktp == NULL);
2470 		ASSERT(ata_ctlp->ac_active_drvp == NULL);
2471 
2472 		ata_ctlp->ac_active_pktp = ata_pktp;
2473 		ata_ctlp->ac_active_drvp = ata_drvp;
2474 
2475 		rc = (*ata_pktp->ap_start)(ata_ctlp, ata_drvp, ata_pktp);
2476 
2477 		if (rc == ATA_FSM_RC_BUSY) {
2478 			/* the request didn't start, GHD will requeue it */
2479 			ata_ctlp->ac_state = AS_IDLE;
2480 			ata_ctlp->ac_active_pktp = NULL;
2481 			ata_ctlp->ac_active_drvp = NULL;
2482 		}
2483 		return (rc);
2484 
2485 	case AC_INTR:
2486 		ASSERT(ata_ctlp->ac_active_pktp != NULL);
2487 		ASSERT(ata_ctlp->ac_active_drvp != NULL);
2488 
2489 		ata_drvp = ata_ctlp->ac_active_drvp;
2490 		ata_pktp = ata_ctlp->ac_active_pktp;
2491 		return ((*ata_pktp->ap_intr)(ata_ctlp, ata_drvp, ata_pktp));
2492 
2493 	case AC_RESET_A: /* Reset, controller active */
2494 		ASSERT(ata_ctlp->ac_active_pktp != NULL);
2495 		ASSERT(ata_ctlp->ac_active_drvp != NULL);
2496 
2497 		/* clean up the active request */
2498 		ata_pktp = ata_ctlp->ac_active_pktp;
2499 		ata_pktp->ap_flags |= AP_DEV_RESET | AP_BUS_RESET;
2500 
2501 		/* halt the DMA engine */
2502 		if (ata_pktp->ap_pciide_dma) {
2503 			ata_pciide_dma_stop(ata_ctlp);
2504 			(void) ata_pciide_status_clear(ata_ctlp);
2505 		}
2506 
2507 		/* Do a Software Reset to unwedge the bus */
2508 		if (!ata_software_reset(ata_ctlp)) {
2509 			return (ATA_FSM_RC_BUSY);
2510 		}
2511 
2512 		/* Then send a DEVICE RESET cmd to each ATAPI device */
2513 		atapi_fsm_reset(ata_ctlp);
2514 		return (ATA_FSM_RC_FINI);
2515 
2516 	case AC_RESET_I: /* Reset, controller idle */
2517 		/* Do a Software Reset to unwedge the bus */
2518 		if (!ata_software_reset(ata_ctlp)) {
2519 			return (ATA_FSM_RC_BUSY);
2520 		}
2521 
2522 		/* Then send a DEVICE RESET cmd to each ATAPI device */
2523 		atapi_fsm_reset(ata_ctlp);
2524 		return (ATA_FSM_RC_OKAY);
2525 
2526 	case AC_FINI:
2527 		break;
2528 	}
2529 
2530 	/*
2531 	 * AC_FINI, check ARQ needs to be started or finished
2532 	 */
2533 
2534 	ASSERT(action == AC_FINI);
2535 	ASSERT(ata_ctlp->ac_active_pktp != NULL);
2536 	ASSERT(ata_ctlp->ac_active_drvp != NULL);
2537 
2538 	/*
2539 	 * The active request is done now.
2540 	 * Disconnect the request from the controller and
2541 	 * add it to the done queue.
2542 	 */
2543 	ata_drvp = ata_ctlp->ac_active_drvp;
2544 	ata_pktp = ata_ctlp->ac_active_pktp;
2545 
2546 	/*
2547 	 * If ARQ pkt is done, get ptr to original pkt and wrap it up.
2548 	 */
2549 	if (ata_pktp == ata_ctlp->ac_arq_pktp) {
2550 		ata_pkt_t *arq_pktp;
2551 
2552 		ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ done\n", ata_ctlp));
2553 
2554 		arq_pktp = ata_pktp;
2555 		ata_pktp = ata_ctlp->ac_fault_pktp;
2556 		ata_ctlp->ac_fault_pktp = NULL;
2557 		if (arq_pktp->ap_flags & (AP_ERROR | AP_BUS_RESET))
2558 			ata_pktp->ap_flags |= AP_ARQ_ERROR;
2559 		else
2560 			ata_pktp->ap_flags |= AP_ARQ_OKAY;
2561 		goto all_done;
2562 	}
2563 
2564 
2565 #define	AP_ARQ_NEEDED	(AP_ARQ_ON_ERROR | AP_GOT_STATUS | AP_ERROR)
2566 
2567 	/*
2568 	 * Start ARQ pkt if necessary
2569 	 */
2570 	if ((ata_pktp->ap_flags & AP_ARQ_NEEDED) == AP_ARQ_NEEDED &&
2571 	    (ata_pktp->ap_status & ATS_ERR)) {
2572 
2573 		/* set controller state back to active */
2574 		ata_ctlp->ac_state = current_state;
2575 
2576 		/* try to start the ARQ pkt */
2577 		rc = ata_start_arq(ata_ctlp, ata_drvp, ata_pktp);
2578 
2579 		if (rc == ATA_FSM_RC_BUSY) {
2580 			ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ BUSY\n", ata_ctlp));
2581 			/* let the target driver handle the problem */
2582 			ata_ctlp->ac_state = AS_IDLE;
2583 			ata_ctlp->ac_active_pktp = NULL;
2584 			ata_ctlp->ac_active_drvp = NULL;
2585 			ata_ctlp->ac_fault_pktp = NULL;
2586 			goto all_done;
2587 		}
2588 
2589 		ADBG_ARQ(("ata_ctlr_fsm 0x%p ARQ started\n", ata_ctlp));
2590 		return (rc);
2591 	}
2592 
2593 	/*
2594 	 * Normal completion, no error status, and not an ARQ pkt,
2595 	 * just fall through.
2596 	 */
2597 
2598 all_done:
2599 
2600 	/*
2601 	 * wrap everything up and tie a ribbon around it
2602 	 */
2603 	ata_ctlp->ac_active_pktp = NULL;
2604 	ata_ctlp->ac_active_drvp = NULL;
2605 	if (APKT2GCMD(ata_pktp) != (gcmd_t *)0) {
2606 		ghd_complete(&ata_ctlp->ac_ccc, APKT2GCMD(ata_pktp));
2607 		if (DoneFlgp)
2608 			*DoneFlgp = TRUE;
2609 	}
2610 
2611 	return (ATA_FSM_RC_OKAY);
2612 }
2613 
2614 
2615 static int
ata_start_arq(ata_ctl_t * ata_ctlp,ata_drv_t * ata_drvp,ata_pkt_t * ata_pktp)2616 ata_start_arq(
2617 	ata_ctl_t *ata_ctlp,
2618 	ata_drv_t *ata_drvp,
2619 	ata_pkt_t *ata_pktp)
2620 {
2621 	ata_pkt_t		*arq_pktp;
2622 	int			 bytes;
2623 	uint_t			 senselen;
2624 
2625 	ADBG_ARQ(("ata_start_arq 0x%p ARQ needed\n", ata_ctlp));
2626 
2627 	/*
2628 	 * Determine just the size of the Request Sense Data buffer within
2629 	 * the scsi_arq_status structure.
2630 	 */
2631 #define	SIZEOF_ARQ_HEADER	(sizeof (struct scsi_arq_status)	\
2632 				- sizeof (struct scsi_extended_sense))
2633 	senselen = ata_pktp->ap_statuslen - SIZEOF_ARQ_HEADER;
2634 	ASSERT(senselen > 0);
2635 
2636 
2637 	/* save ptr to original pkt */
2638 	ata_ctlp->ac_fault_pktp = ata_pktp;
2639 
2640 	/* switch the controller's active pkt to the ARQ pkt */
2641 	arq_pktp = ata_ctlp->ac_arq_pktp;
2642 	ata_ctlp->ac_active_pktp = arq_pktp;
2643 
2644 	/* finish initializing the ARQ CDB */
2645 	ata_ctlp->ac_arq_cdb[1] = ata_drvp->ad_lun << 4;
2646 	ata_ctlp->ac_arq_cdb[4] = (uchar_t)senselen;
2647 
2648 	/* finish initializing the ARQ pkt */
2649 	arq_pktp->ap_v_addr = (caddr_t)&ata_pktp->ap_scbp->sts_sensedata;
2650 
2651 	arq_pktp->ap_resid = senselen;
2652 	arq_pktp->ap_flags = AP_ATAPI | AP_READ;
2653 	arq_pktp->ap_cdb_pad =
2654 	    ((unsigned)(ata_drvp->ad_cdb_len - arq_pktp->ap_cdb_len)) >> 1;
2655 
2656 	bytes = min(senselen, ATAPI_MAX_BYTES_PER_DRQ);
2657 	arq_pktp->ap_hicyl = (uchar_t)(bytes >> 8);
2658 	arq_pktp->ap_lwcyl = (uchar_t)bytes;
2659 
2660 	/*
2661 	 * This packet is shared by all drives on this controller
2662 	 * therefore we need to init the drive number on every ARQ.
2663 	 */
2664 	arq_pktp->ap_hd = ata_drvp->ad_drive_bits;
2665 
2666 	/* start it up */
2667 	return ((*arq_pktp->ap_start)(ata_ctlp, ata_drvp, arq_pktp));
2668 }
2669 
2670 /*
2671  *
2672  * reset the bus
2673  *
2674  */
2675 
2676 static int
ata_reset_bus(ata_ctl_t * ata_ctlp)2677 ata_reset_bus(
2678 	ata_ctl_t *ata_ctlp)
2679 {
2680 	int	watchdog;
2681 	uchar_t	drive;
2682 	int	rc = FALSE;
2683 	uchar_t	fsm_func;
2684 	int	DoneFlg = FALSE;
2685 
2686 	/*
2687 	 * Do a Software Reset to unwedge the bus, and send
2688 	 * ATAPI DEVICE RESET to each ATAPI drive.
2689 	 */
2690 	fsm_func = ATA_FSM_RESET;
2691 	for (watchdog = ata_reset_bus_watchdog; watchdog > 0; watchdog--) {
2692 		switch (ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL,
2693 		    &DoneFlg)) {
2694 		case ATA_FSM_RC_OKAY:
2695 			rc = TRUE;
2696 			goto fsm_done;
2697 
2698 		case ATA_FSM_RC_BUSY:
2699 			return (FALSE);
2700 
2701 		case ATA_FSM_RC_INTR:
2702 			fsm_func = ATA_FSM_INTR;
2703 			rc = TRUE;
2704 			continue;
2705 
2706 		case ATA_FSM_RC_FINI:
2707 			fsm_func = ATA_FSM_FINI;
2708 			rc = TRUE;
2709 			continue;
2710 		}
2711 	}
2712 	ADBG_WARN(("ata_reset_bus: watchdog\n"));
2713 
2714 fsm_done:
2715 
2716 	/*
2717 	 * Reinitialize the ATA drives
2718 	 */
2719 	for (drive = 0; drive < ATA_MAXTARG; drive++) {
2720 		ata_drv_t *ata_drvp;
2721 
2722 		if ((ata_drvp = CTL2DRV(ata_ctlp, drive, 0)) == NULL)
2723 			continue;
2724 
2725 		if (ATAPIDRV(ata_drvp))
2726 			continue;
2727 
2728 		/*
2729 		 * Reprogram the Read/Write Multiple block factor
2730 		 * and current geometry into the drive.
2731 		 */
2732 		if (!ata_disk_setup_parms(ata_ctlp, ata_drvp))
2733 			rc = FALSE;
2734 	}
2735 
2736 	/* If DoneFlg is TRUE, it means that ghd_complete() function */
2737 	/* has been already called. In this case ignore any errors and */
2738 	/* return TRUE to the caller, otherwise return the value of rc */
2739 	/* to the caller */
2740 	if (DoneFlg)
2741 		return (TRUE);
2742 	else
2743 		return (rc);
2744 }
2745 
2746 
2747 /*
2748  *
2749  * Low level routine to toggle the Software Reset bit
2750  *
2751  */
2752 
2753 static int
ata_software_reset(ata_ctl_t * ata_ctlp)2754 ata_software_reset(
2755 	ata_ctl_t *ata_ctlp)
2756 {
2757 	ddi_acc_handle_t io_hdl1 = ata_ctlp->ac_iohandle1;
2758 	ddi_acc_handle_t io_hdl2 = ata_ctlp->ac_iohandle2;
2759 	hrtime_t deadline;
2760 	uint_t usecs_left;
2761 
2762 	ADBG_TRACE(("ata_reset_bus entered\n"));
2763 
2764 	/* disable interrupts and turn the software reset bit on */
2765 	ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST));
2766 
2767 	/* why 30 milliseconds, the ATA/ATAPI-4 spec says 5 usec. */
2768 	drv_usecwait(30000);
2769 
2770 	/* turn the software reset bit back off */
2771 	ddi_put8(io_hdl2, ata_ctlp->ac_devctl, ATDC_D3);
2772 
2773 	/*
2774 	 * Wait for the controller to assert BUSY status.
2775 	 * I don't think 300 msecs is correct. The ATA/ATAPI-4
2776 	 * spec says 400 nsecs, (and 2 msecs if device
2777 	 * was in sleep mode; but we don't put drives to sleep
2778 	 * so it probably doesn't matter).
2779 	 */
2780 	drv_usecwait(300000);
2781 
2782 	/*
2783 	 * If drive 0 exists the test for completion is simple
2784 	 */
2785 	deadline = gethrtime() + ((hrtime_t)31 * NANOSEC);
2786 
2787 	if (CTL2DRV(ata_ctlp, 0, 0)) {
2788 		goto wait_for_not_busy;
2789 	}
2790 
2791 	ASSERT(CTL2DRV(ata_ctlp, 1, 0) != NULL);
2792 
2793 	/*
2794 	 * This must be a single device configuration, with drive 1
2795 	 * only. This complicates the test for completion because
2796 	 * issuing the software reset just caused drive 1 to
2797 	 * deselect. With drive 1 deselected, if I just read the
2798 	 * status register to test the BSY bit I get garbage, but
2799 	 * I can't re-select drive 1 until I'm certain the BSY bit
2800 	 * is de-asserted. Catch-22.
2801 	 *
2802 	 * In ATA/ATAPI-4, rev 15, section 9.16.2, it says to handle
2803 	 * this situation like this:
2804 	 */
2805 
2806 	/* give up if the drive doesn't settle within 31 seconds */
2807 	while (gethrtime() < deadline) {
2808 		/*
2809 		 * delay 10msec each time around the loop
2810 		 */
2811 		drv_usecwait(10000);
2812 
2813 		/*
2814 		 * try to select drive 1
2815 		 */
2816 		ddi_put8(io_hdl1, ata_ctlp->ac_drvhd, ATDH_DRIVE1);
2817 
2818 		ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0x55);
2819 		ddi_put8(io_hdl1, ata_ctlp->ac_sect, 0xaa);
2820 		if (ddi_get8(io_hdl1, ata_ctlp->ac_sect) != 0xaa)
2821 			continue;
2822 
2823 		ddi_put8(io_hdl1, ata_ctlp->ac_count, 0x55);
2824 		ddi_put8(io_hdl1, ata_ctlp->ac_count, 0xaa);
2825 		if (ddi_get8(io_hdl1, ata_ctlp->ac_count) != 0xaa)
2826 			continue;
2827 
2828 		goto wait_for_not_busy;
2829 	}
2830 	return (FALSE);
2831 
2832 wait_for_not_busy:
2833 
2834 	/*
2835 	 * Now wait up to 31 seconds for BUSY to clear.
2836 	 */
2837 	usecs_left = (deadline - gethrtime()) / 1000;
2838 	(void) ata_wait3(io_hdl2, ata_ctlp->ac_ioaddr2, 0, ATS_BSY,
2839 	    ATS_ERR, ATS_BSY, ATS_DF, ATS_BSY, usecs_left);
2840 
2841 	return (TRUE);
2842 }
2843 
2844 /*
2845  *
2846  * DDI interrupt handler
2847  *
2848  */
2849 
2850 static uint_t
ata_intr(caddr_t arg)2851 ata_intr(
2852 	caddr_t arg)
2853 {
2854 	ata_ctl_t *ata_ctlp;
2855 	int	   one_shot = 1;
2856 
2857 	ata_ctlp = (ata_ctl_t *)arg;
2858 
2859 	return (ghd_intr(&ata_ctlp->ac_ccc, (void *)&one_shot));
2860 }
2861 
2862 
2863 /*
2864  *
2865  * GHD ccc_get_status callback
2866  *
2867  */
2868 
2869 static int
ata_get_status(void * hba_handle,void * intr_status)2870 ata_get_status(
2871 	void *hba_handle,
2872 	void *intr_status)
2873 {
2874 	ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle;
2875 	uchar_t	   status;
2876 
2877 	ADBG_TRACE(("ata_get_status entered\n"));
2878 
2879 	/*
2880 	 * ignore interrupts before ata_attach completes
2881 	 */
2882 	if (!(ata_ctlp->ac_flags & AC_ATTACHED))
2883 		return (FALSE);
2884 
2885 	/*
2886 	 * can't be interrupt pending if nothing active
2887 	 */
2888 	switch (ata_ctlp->ac_state) {
2889 	case AS_IDLE:
2890 		return (FALSE);
2891 	case AS_ACTIVE0:
2892 	case AS_ACTIVE1:
2893 		ASSERT(ata_ctlp->ac_active_drvp != NULL);
2894 		ASSERT(ata_ctlp->ac_active_pktp != NULL);
2895 		break;
2896 	}
2897 
2898 	/*
2899 	 * If this is a PCI-IDE controller, check the PCI-IDE controller's
2900 	 * interrupt status latch. But don't clear it yet.
2901 	 *
2902 	 * AC_BMSTATREG_PIO_BROKEN flag is used currently for
2903 	 * CMD chips with device id 0x646. Since the interrupt bit on
2904 	 * Bus master IDE register is not usable when in PIO mode,
2905 	 * this chip is treated as a legacy device for interrupt
2906 	 * indication.  The following code for CMD
2907 	 * chips may need to be revisited when we enable support for dma.
2908 	 *
2909 	 * CHANGE: DMA is not disabled for these devices. BM intr bit is
2910 	 * checked only if there was DMA used or BM intr is useable on PIO,
2911 	 * else treat it as before - as legacy device.
2912 	 */
2913 
2914 	if ((ata_ctlp->ac_pciide) &&
2915 	    ((ata_ctlp->ac_pciide_bm != FALSE) &&
2916 	    ((ata_ctlp->ac_active_pktp->ap_pciide_dma == TRUE) ||
2917 	    !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)))) {
2918 
2919 		if (!ata_pciide_status_pending(ata_ctlp))
2920 			return (FALSE);
2921 	} else {
2922 		/*
2923 		 * Interrupts from legacy ATA/IDE controllers are
2924 		 * edge-triggered but the dumb legacy ATA/IDE controllers
2925 		 * and drives don't have an interrupt status bit.
2926 		 *
2927 		 * Use a one_shot variable to make sure we only return
2928 		 * one status per interrupt.
2929 		 */
2930 		if (intr_status != NULL) {
2931 			int *one_shot = (int *)intr_status;
2932 
2933 			if (*one_shot == 1)
2934 				*one_shot = 0;
2935 			else
2936 				return (FALSE);
2937 		}
2938 	}
2939 
2940 	/* check if device is still busy */
2941 
2942 	status = ddi_get8(ata_ctlp->ac_iohandle2, ata_ctlp->ac_altstatus);
2943 	if (status & ATS_BSY)
2944 		return (FALSE);
2945 	return (TRUE);
2946 }
2947 
2948 
2949 /*
2950  *
2951  * get the current status and clear the IRQ
2952  *
2953  */
2954 
2955 int
ata_get_status_clear_intr(ata_ctl_t * ata_ctlp,ata_pkt_t * ata_pktp)2956 ata_get_status_clear_intr(
2957 	ata_ctl_t *ata_ctlp,
2958 	ata_pkt_t *ata_pktp)
2959 {
2960 	uchar_t	status;
2961 
2962 	/*
2963 	 * Here's where we clear the PCI-IDE interrupt latch. If this
2964 	 * request used DMA mode then we also have to check and clear
2965 	 * the DMA error latch at the same time.
2966 	 */
2967 
2968 	if (ata_pktp->ap_pciide_dma) {
2969 		if (ata_pciide_status_dmacheck_clear(ata_ctlp))
2970 			ata_pktp->ap_flags |= AP_ERROR | AP_TRAN_ERROR;
2971 	} else if ((ata_ctlp->ac_pciide) &&
2972 	    !(ata_ctlp->ac_flags & AC_BMSTATREG_PIO_BROKEN)) {
2973 		/*
2974 		 * Some requests don't use DMA mode and therefore won't
2975 		 * set the DMA error latch, but we still have to clear
2976 		 * the interrupt latch.
2977 		 * Controllers with broken BM intr in PIO mode do not go
2978 		 * through this path.
2979 		 */
2980 		(void) ata_pciide_status_clear(ata_ctlp);
2981 	}
2982 
2983 	/*
2984 	 * this clears the drive's interrupt
2985 	 */
2986 	status = ddi_get8(ata_ctlp->ac_iohandle1, ata_ctlp->ac_status);
2987 	ADBG_TRACE(("ata_get_status_clear_intr: 0x%x\n", status));
2988 	return (status);
2989 }
2990 
2991 
2992 
2993 /*
2994  *
2995  * GHD interrupt handler
2996  *
2997  */
2998 
2999 /* ARGSUSED */
3000 static void
ata_process_intr(void * hba_handle,void * intr_status)3001 ata_process_intr(
3002 	void *hba_handle,
3003 	void *intr_status)
3004 {
3005 	ata_ctl_t *ata_ctlp = (ata_ctl_t *)hba_handle;
3006 	int	   watchdog;
3007 	uchar_t	   fsm_func;
3008 	int	   rc;
3009 
3010 	ADBG_TRACE(("ata_process_intr entered\n"));
3011 
3012 	/*
3013 	 * process the ATA or ATAPI interrupt
3014 	 */
3015 
3016 	fsm_func = ATA_FSM_INTR;
3017 	for (watchdog = ata_process_intr_watchdog; watchdog > 0; watchdog--) {
3018 		rc =  ata_ctlr_fsm(fsm_func, ata_ctlp, NULL, NULL, NULL);
3019 
3020 		switch (rc) {
3021 		case ATA_FSM_RC_OKAY:
3022 			return;
3023 
3024 		case ATA_FSM_RC_BUSY:	/* wait for the next interrupt */
3025 			return;
3026 
3027 		case ATA_FSM_RC_INTR:	/* re-invoke the FSM */
3028 			fsm_func = ATA_FSM_INTR;
3029 			break;
3030 
3031 		case ATA_FSM_RC_FINI:	/* move a request to done Q */
3032 			fsm_func = ATA_FSM_FINI;
3033 			break;
3034 		}
3035 	}
3036 	ADBG_WARN(("ata_process_intr: watchdog\n"));
3037 }
3038 
3039 
3040 
3041 /*
3042  *
3043  * GHD ccc_hba_start callback
3044  *
3045  */
3046 
3047 static int
ata_hba_start(void * hba_handle,gcmd_t * gcmdp)3048 ata_hba_start(
3049 	void *hba_handle,
3050 	gcmd_t *gcmdp)
3051 {
3052 	ata_ctl_t *ata_ctlp;
3053 	ata_drv_t *ata_drvp;
3054 	ata_pkt_t *ata_pktp;
3055 	uchar_t	   fsm_func;
3056 	int	   request_started;
3057 	int	   watchdog;
3058 
3059 	ADBG_TRACE(("ata_hba_start entered\n"));
3060 
3061 	ata_ctlp = (ata_ctl_t *)hba_handle;
3062 
3063 	if (ata_ctlp->ac_active_drvp != NULL) {
3064 		ADBG_WARN(("ata_hba_start drvp not null\n"));
3065 		return (FALSE);
3066 	}
3067 	if (ata_ctlp->ac_active_pktp != NULL) {
3068 		ADBG_WARN(("ata_hba_start pktp not null\n"));
3069 		return (FALSE);
3070 	}
3071 
3072 	ata_pktp = GCMD2APKT(gcmdp);
3073 	ata_drvp = GCMD2DRV(gcmdp);
3074 
3075 	/*
3076 	 * which drive?
3077 	 */
3078 	if (ata_drvp->ad_targ == 0)
3079 		fsm_func = ATA_FSM_START0;
3080 	else
3081 		fsm_func = ATA_FSM_START1;
3082 
3083 	/*
3084 	 * start the request
3085 	 */
3086 	request_started = FALSE;
3087 	for (watchdog = ata_hba_start_watchdog; watchdog > 0; watchdog--) {
3088 		switch (ata_ctlr_fsm(fsm_func, ata_ctlp, ata_drvp, ata_pktp,
3089 		    NULL)) {
3090 		case ATA_FSM_RC_OKAY:
3091 			request_started = TRUE;
3092 			goto fsm_done;
3093 
3094 		case ATA_FSM_RC_BUSY:
3095 			/* if first time, tell GHD to requeue the request */
3096 			goto fsm_done;
3097 
3098 		case ATA_FSM_RC_INTR:
3099 			/*
3100 			 * The start function polled for the next
3101 			 * bus phase, now fake an interrupt to process
3102 			 * the next action.
3103 			 */
3104 			request_started = TRUE;
3105 			fsm_func = ATA_FSM_INTR;
3106 			ata_drvp = NULL;
3107 			ata_pktp = NULL;
3108 			break;
3109 
3110 		case ATA_FSM_RC_FINI: /* move request to the done queue */
3111 			request_started = TRUE;
3112 			fsm_func = ATA_FSM_FINI;
3113 			ata_drvp = NULL;
3114 			ata_pktp = NULL;
3115 			break;
3116 		}
3117 	}
3118 	ADBG_WARN(("ata_hba_start: watchdog\n"));
3119 
3120 fsm_done:
3121 	return (request_started);
3122 
3123 }
3124 
3125 static int
ata_check_pciide_blacklist(dev_info_t * dip,uint_t flags)3126 ata_check_pciide_blacklist(
3127 	dev_info_t *dip,
3128 	uint_t flags)
3129 {
3130 	ushort_t vendorid;
3131 	ushort_t deviceid;
3132 	pcibl_t	*blp;
3133 	int	*propp;
3134 	uint_t	 count;
3135 	int	 rc;
3136 
3137 
3138 	vendorid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip),
3139 	    DDI_PROP_DONTPASS, "vendor-id", 0);
3140 	deviceid = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip),
3141 	    DDI_PROP_DONTPASS, "device-id", 0);
3142 
3143 	/*
3144 	 * first check for a match in the "pci-ide-blacklist" property
3145 	 */
3146 	rc = ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, 0,
3147 	    "pci-ide-blacklist", &propp, &count);
3148 
3149 	if (rc == DDI_PROP_SUCCESS) {
3150 		count = (count * sizeof (uint_t)) / sizeof (pcibl_t);
3151 		blp = (pcibl_t *)propp;
3152 		while (count--) {
3153 			/* check for matching ID */
3154 			if ((vendorid & blp->b_vmask)
3155 			    != (blp->b_vendorid & blp->b_vmask)) {
3156 				blp++;
3157 				continue;
3158 			}
3159 			if ((deviceid & blp->b_dmask)
3160 			    != (blp->b_deviceid & blp->b_dmask)) {
3161 				blp++;
3162 				continue;
3163 			}
3164 
3165 			/* got a match */
3166 			if (blp->b_flags & flags) {
3167 				ddi_prop_free(propp);
3168 				return (TRUE);
3169 			} else {
3170 				ddi_prop_free(propp);
3171 				return (FALSE);
3172 			}
3173 		}
3174 		ddi_prop_free(propp);
3175 	}
3176 
3177 	/*
3178 	 * then check the built-in blacklist
3179 	 */
3180 	for (blp = ata_pciide_blacklist; blp->b_vendorid; blp++) {
3181 		if ((vendorid & blp->b_vmask) != blp->b_vendorid)
3182 			continue;
3183 		if ((deviceid & blp->b_dmask) != blp->b_deviceid)
3184 			continue;
3185 		if (!(blp->b_flags & flags))
3186 			continue;
3187 		return (TRUE);
3188 	}
3189 	return (FALSE);
3190 }
3191 
3192 int
ata_check_drive_blacklist(struct ata_id * aidp,uint_t flags)3193 ata_check_drive_blacklist(
3194 	struct ata_id *aidp,
3195 	uint_t flags)
3196 {
3197 	atabl_t	*blp;
3198 
3199 	for (blp = ata_drive_blacklist; blp->b_model != NULL; blp++) {
3200 		if (!ata_strncmp(blp->b_model, aidp->ai_model,
3201 		    sizeof (aidp->ai_model)))
3202 			continue;
3203 		if (blp->b_fw != NULL) {
3204 			if (!ata_strncmp(blp->b_fw, aidp->ai_fw,
3205 			    sizeof (aidp->ai_fw)))
3206 				continue;
3207 		}
3208 		if (blp->b_flags & flags)
3209 			return (TRUE);
3210 		return (FALSE);
3211 	}
3212 	return (FALSE);
3213 }
3214 
3215 /*
3216  * Queue a request to perform some sort of internally
3217  * generated command. When this request packet reaches
3218  * the front of the queue (*func)() is invoked.
3219  *
3220  */
3221 
3222 int
ata_queue_cmd(int (* func)(ata_ctl_t *,ata_drv_t *,ata_pkt_t *),void * arg,ata_ctl_t * ata_ctlp,ata_drv_t * ata_drvp,gtgt_t * gtgtp)3223 ata_queue_cmd(
3224 	int	  (*func)(ata_ctl_t *, ata_drv_t *, ata_pkt_t *),
3225 	void	  *arg,
3226 	ata_ctl_t *ata_ctlp,
3227 	ata_drv_t *ata_drvp,
3228 	gtgt_t	  *gtgtp)
3229 {
3230 	ata_pkt_t	*ata_pktp;
3231 	gcmd_t		*gcmdp;
3232 	int		 rc;
3233 
3234 	if (!(gcmdp = ghd_gcmd_alloc(gtgtp, sizeof (*ata_pktp), TRUE))) {
3235 		ADBG_ERROR(("atapi_id_update alloc failed\n"));
3236 		return (FALSE);
3237 	}
3238 
3239 
3240 	/* set the back ptr from the ata_pkt to the gcmd_t */
3241 	ata_pktp = GCMD2APKT(gcmdp);
3242 	ata_pktp->ap_gcmdp = gcmdp;
3243 	ata_pktp->ap_hd = ata_drvp->ad_drive_bits;
3244 	ata_pktp->ap_bytes_per_block = ata_drvp->ad_bytes_per_block;
3245 
3246 	/*
3247 	 * over-ride the default start function
3248 	 */
3249 	ata_pktp = GCMD2APKT(gcmdp);
3250 	ata_pktp->ap_start = func;
3251 	ata_pktp->ap_complete = NULL;
3252 	ata_pktp->ap_v_addr = (caddr_t)arg;
3253 
3254 	/*
3255 	 * add it to the queue, when it gets to the front the
3256 	 * ap_start function is called.
3257 	 */
3258 	rc = ghd_transport(&ata_ctlp->ac_ccc, gcmdp, gcmdp->cmd_gtgtp,
3259 	    0, TRUE, NULL);
3260 
3261 	if (rc != TRAN_ACCEPT) {
3262 		/* this should never, ever happen */
3263 		return (FALSE);
3264 	}
3265 
3266 	if (ata_pktp->ap_flags & AP_ERROR)
3267 		return (FALSE);
3268 	return (TRUE);
3269 }
3270 
3271 /*
3272  * Check if this drive has the "revert to defaults" bug
3273  * PSARC 2001/500 and 2001/xxx - check for the properties
3274  * ata-revert-to-defaults and atarvrt-<diskmodel> before
3275  * examining the blacklist.
3276  * <diskmodel> is made from the model number reported by Identify Drive
3277  * with uppercase letters converted to lowercase and all characters
3278  * except letters, digits, ".", "_", and "-" deleted.
3279  * Return value:
3280  *	TRUE:	enable revert to defaults
3281  *	FALSE:	disable revert to defaults
3282  *
3283  * NOTE: revert to power on defaults that includes reverting to MDMA
3284  * mode is allowed by ATA-6 & ATA-7 specs.
3285  * Therefore drives exhibiting this behaviour are not violating the spec.
3286  * Furthermore, the spec explicitly says that after the soft reset
3287  * host should check the current setting of the device features.
3288  * Correctly working BIOS would therefore reprogram either the drive
3289  * and/or the host controller to match transfer modes.
3290  * Devices with ATA_BL_NORVRT flag will be removed from
3291  * the ata_blacklist.
3292  * The default behaviour will be - no revert to power-on defaults
3293  * for all devices. The property is retained in case the user
3294  * explicitly requests revert-to-defaults before reboot.
3295  */
3296 
3297 #define	ATA_REVERT_PROP_PREFIX "revert-"
3298 #define	ATA_REVERT_PROP_GLOBAL	"ata-revert-to-defaults"
3299 /* room for prefix + model number + terminating NUL character */
3300 #define	PROP_BUF_SIZE	(sizeof (ATA_REVERT_PROP_PREFIX) + \
3301 				sizeof (aidp->ai_model) + 1)
3302 #define	PROP_LEN_MAX	(31)
3303 
3304 static int
ata_check_revert_to_defaults(ata_drv_t * ata_drvp)3305 ata_check_revert_to_defaults(
3306 	ata_drv_t *ata_drvp)
3307 {
3308 	struct ata_id	*aidp = &ata_drvp->ad_id;
3309 	ata_ctl_t	*ata_ctlp = ata_drvp->ad_ctlp;
3310 	char	 prop_buf[PROP_BUF_SIZE];
3311 	int	 i, j;
3312 	int	 propval;
3313 
3314 	/* put prefix into the buffer */
3315 	(void) strcpy(prop_buf, ATA_REVERT_PROP_PREFIX);
3316 	j = strlen(prop_buf);
3317 
3318 	/* append the model number, leaving out invalid characters */
3319 	for (i = 0;  i < sizeof (aidp->ai_model);  ++i) {
3320 		char c = aidp->ai_model[i];
3321 		if (c >= 'A' && c <= 'Z')	/* uppercase -> lower */
3322 			c = c - 'A' + 'a';
3323 		if (c >= 'a' && c <= 'z' || c >= '0' && c <= '9' ||
3324 		    c == '.' || c == '_' || c == '-')
3325 			prop_buf[j++] = c;
3326 		if (c == '\0')
3327 			break;
3328 	}
3329 
3330 	/* make sure there's a terminating NUL character */
3331 	if (j >= PROP_LEN_MAX)
3332 		j =  PROP_LEN_MAX;
3333 	prop_buf[j] = '\0';
3334 
3335 	/* look for a disk-specific "revert" property" */
3336 	propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip,
3337 	    DDI_PROP_DONTPASS, prop_buf, -1);
3338 	if (propval == 0)
3339 		return (FALSE);
3340 	else if (propval != -1)
3341 		return (TRUE);
3342 
3343 	/* look for a global "revert" property" */
3344 	propval = ddi_getprop(DDI_DEV_T_ANY, ata_ctlp->ac_dip,
3345 	    0, ATA_REVERT_PROP_GLOBAL, -1);
3346 	if (propval == 0)
3347 		return (FALSE);
3348 	else if (propval != -1)
3349 		return (TRUE);
3350 
3351 	return (FALSE);
3352 }
3353 
3354 void
ata_show_transfer_mode(ata_ctl_t * ata_ctlp,ata_drv_t * ata_drvp)3355 ata_show_transfer_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp)
3356 {
3357 	int i;
3358 
3359 	if (ata_ctlp->ac_pciide_bm == FALSE ||
3360 	    ata_drvp->ad_pciide_dma != ATA_DMA_ON) {
3361 		if (ata_cntrl_DMA_sel_msg) {
3362 			ATAPRT((
3363 			    "?\tATA DMA off: %s\n", ata_cntrl_DMA_sel_msg));
3364 		} else if (ata_dev_DMA_sel_msg) {
3365 			ATAPRT(("?\tATA DMA off: %s\n", ata_dev_DMA_sel_msg));
3366 		}
3367 		ATAPRT(("?\tPIO mode %d selected\n",
3368 		    (ata_drvp->ad_id.ai_advpiomode & ATAC_ADVPIO_4_SUP) ==
3369 		    ATAC_ADVPIO_4_SUP ? 4 : 3));
3370 	} else {
3371 		/* Using DMA */
3372 		if (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_SEL_MASK) {
3373 			/*
3374 			 * Rely on the fact that either dwdma or udma is
3375 			 * selected, not both.
3376 			 */
3377 			ATAPRT(("?\tMultiwordDMA mode %d selected\n",
3378 			    (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_2_SEL) ==
3379 			    ATAC_MDMA_2_SEL ? 2 :
3380 			    (ata_drvp->ad_id.ai_dworddma & ATAC_MDMA_1_SEL) ==
3381 			    ATAC_MDMA_1_SEL ? 1 : 0));
3382 		} else {
3383 			for (i = 0; i <= 6; i++) {
3384 				if (ata_drvp->ad_id.ai_ultradma &
3385 				    (1 << (i + 8))) {
3386 					ATAPRT((
3387 					    "?\tUltraDMA mode %d selected\n",
3388 					    i));
3389 					break;
3390 				}
3391 			}
3392 		}
3393 	}
3394 }
3395 
3396 /*
3397  * Controller-specific operation pointers.
3398  * Should be extended as needed - init only for now
3399  */
3400 struct ata_ctl_spec_ops {
3401 	uint_t	(*cs_init)(dev_info_t *, ushort_t, ushort_t); /* ctlr init */
3402 };
3403 
3404 
3405 struct ata_ctl_spec {
3406 	ushort_t		cs_vendor_id;
3407 	ushort_t		cs_device_id;
3408 	struct ata_ctl_spec_ops	*cs_ops;
3409 };
3410 
3411 /* Sil3XXX-specific functions (init only for now) */
3412 struct ata_ctl_spec_ops sil3xxx_ops = {
3413 	&sil3xxx_init_controller	/* Sil3XXX cntrl initialization */
3414 };
3415 
3416 
3417 struct ata_ctl_spec ata_cntrls_spec[] = {
3418 	{0x1095, 0x3114, &sil3xxx_ops},
3419 	{0x1095, 0x3512, &sil3xxx_ops},
3420 	{0x1095, 0x3112, &sil3xxx_ops},
3421 	{0, 0, NULL}		/* List must end with cs_ops set to NULL */
3422 };
3423 
3424 /*
3425  * Do controller specific initialization if necessary.
3426  * Pick-up controller specific functions.
3427  */
3428 
3429 int
ata_spec_init_controller(dev_info_t * dip)3430 ata_spec_init_controller(dev_info_t *dip)
3431 {
3432 	ushort_t		vendor_id;
3433 	ushort_t		device_id;
3434 	struct ata_ctl_spec	*ctlsp;
3435 
3436 	vendor_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip),
3437 	    DDI_PROP_DONTPASS, "vendor-id", 0);
3438 	device_id = ddi_prop_get_int(DDI_DEV_T_ANY, ddi_get_parent(dip),
3439 	    DDI_PROP_DONTPASS, "device-id", 0);
3440 
3441 	/* Locate controller specific ops, if they exist */
3442 	ctlsp = ata_cntrls_spec;
3443 	while (ctlsp->cs_ops != NULL) {
3444 		if (ctlsp->cs_vendor_id == vendor_id &&
3445 		    ctlsp->cs_device_id == device_id)
3446 			break;
3447 		ctlsp++;
3448 	}
3449 
3450 	if (ctlsp->cs_ops != NULL) {
3451 		if (ctlsp->cs_ops->cs_init != NULL) {
3452 			/* Initialize controller */
3453 			if ((*(ctlsp->cs_ops->cs_init))
3454 			    (dip, vendor_id, device_id) != TRUE) {
3455 				cmn_err(CE_WARN,
3456 				    "pci%4x,%4x cntrl specific "
3457 				    "initialization failed",
3458 				    vendor_id, device_id);
3459 				return (FALSE);
3460 			}
3461 		}
3462 	}
3463 	return (TRUE);
3464 }
3465 
3466 /*
3467  * this routine works like ddi_prop_get_int, except that it works on
3468  * a string property that contains ascii representations
3469  * of an integer.
3470  * If the property is not found, the default value is returned.
3471  */
3472 static int
ata_prop_lookup_int(dev_t match_dev,dev_info_t * dip,uint_t flags,char * name,int defvalue)3473 ata_prop_lookup_int(dev_t match_dev, dev_info_t *dip,
3474     uint_t flags, char *name, int defvalue)
3475 {
3476 
3477 	char *bufp, *cp;
3478 	int rc = defvalue;
3479 	int proprc;
3480 
3481 	proprc = ddi_prop_lookup_string(match_dev, dip,
3482 	    flags, name, &bufp);
3483 
3484 	if (proprc == DDI_PROP_SUCCESS) {
3485 		cp = bufp;
3486 		rc = stoi(&cp);
3487 		ddi_prop_free(bufp);
3488 	} else {
3489 		/*
3490 		 * see if property is encoded as an int instead of string.
3491 		 */
3492 		rc = ddi_prop_get_int(match_dev, dip, flags, name, defvalue);
3493 	}
3494 
3495 	return (rc);
3496 }
3497 
3498 /*
3499  * Initialize the power management components
3500  */
3501 static void
ata_init_pm(dev_info_t * dip)3502 ata_init_pm(dev_info_t *dip)
3503 {
3504 	int		instance;
3505 	ata_ctl_t 	*ata_ctlp;
3506 #ifdef	ATA_USE_AUTOPM
3507 	char		pmc_name[16];
3508 	char		*pmc[] = {
3509 				NULL,
3510 				"0=Sleep (PCI D3 State)",
3511 				"3=PowerOn (PCI D0 State)",
3512 				NULL
3513 			};
3514 #endif
3515 
3516 
3517 	instance = ddi_get_instance(dip);
3518 	ata_ctlp = ddi_get_soft_state(ata_state, instance);
3519 	ata_ctlp->ac_pm_support = 0;
3520 
3521 	/* check PCI capabilities */
3522 	if (!ata_is_pci(dip))
3523 		return;
3524 
3525 #ifdef	ATA_USE_AUTOPM
3526 	(void) sprintf(pmc_name, "NAME=ata%d", instance);
3527 	pmc[0] = pmc_name;
3528 
3529 	if (ddi_prop_update_string_array(DDI_DEV_T_NONE, dip,
3530 	    "pm-components", pmc, 3) != DDI_PROP_SUCCESS) {
3531 		return;
3532 	}
3533 #endif
3534 
3535 	ata_ctlp->ac_pm_support = 1;
3536 	ata_ctlp->ac_pm_level = PM_LEVEL_D0;
3537 
3538 	ATA_BUSY_COMPONENT(dip, 0);
3539 	if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) != DDI_SUCCESS) {
3540 		(void) ddi_prop_remove(DDI_DEV_T_NONE, dip, "pm-components");
3541 	}
3542 	ATA_IDLE_COMPONENT(dip, 0);
3543 }
3544 
3545 /*
3546  * resume the hard drive
3547  */
3548 static void
ata_resume_drive(ata_drv_t * ata_drvp)3549 ata_resume_drive(ata_drv_t *ata_drvp)
3550 {
3551 	ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp;
3552 	int drive_type;
3553 	struct ata_id id;
3554 
3555 	ADBG_TRACE(("ata_resume_drive entered\n"));
3556 
3557 	drive_type = ata_drive_type(ata_drvp->ad_drive_bits,
3558 	    ata_ctlp->ac_iohandle1, ata_ctlp->ac_ioaddr1,
3559 	    ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2,
3560 	    &id);
3561 	if (drive_type == ATA_DEV_NONE)
3562 		return;
3563 
3564 	if (!ATAPIDRV(ata_drvp)) {
3565 		/* Reset Ultra DMA mode */
3566 		ata_reset_dma_mode(ata_drvp);
3567 		if (!ata_disk_setup_parms(ata_ctlp, ata_drvp))
3568 			return;
3569 	} else {
3570 		(void) atapi_init_drive(ata_drvp);
3571 		if (ata_drvp->ad_dma_mode != 0) {
3572 			(void) atapi_reset_dma_mode(ata_drvp, FALSE);
3573 			if (!ata_check_dma_mode(ata_drvp))
3574 				atapi_reset_dma_mode(ata_drvp, TRUE);
3575 			if (ata_drvp->ad_id.ai_ultradma !=
3576 			    ata_drvp->ad_dma_mode) {
3577 				ata_drvp->ad_pciide_dma = ATA_DMA_OFF;
3578 			} else {
3579 				ata_drvp->ad_pciide_dma = ATA_DMA_ON;
3580 			}
3581 		}
3582 	}
3583 	(void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_DIS_REVPOD, 0);
3584 
3585 }
3586 
3587 /*
3588  * resume routine, it will be run when get the command
3589  * DDI_RESUME at attach(9E) from system power management
3590  */
3591 static int
ata_resume(dev_info_t * dip)3592 ata_resume(dev_info_t *dip)
3593 {
3594 	int		instance;
3595 	ata_ctl_t 	*ata_ctlp;
3596 	ddi_acc_handle_t io_hdl2;
3597 	caddr_t		ioaddr2;
3598 
3599 	instance = ddi_get_instance(dip);
3600 	ata_ctlp = ddi_get_soft_state(ata_state, instance);
3601 
3602 	if (!ata_ctlp->ac_pm_support)
3603 		return (DDI_FAILURE);
3604 	if (ata_ctlp->ac_pm_level == PM_LEVEL_D0)
3605 		return (DDI_SUCCESS);
3606 
3607 	ATA_BUSY_COMPONENT(dip, 0);
3608 	if (ATA_RAISE_POWER(dip, 0, PM_LEVEL_D0) == DDI_FAILURE)
3609 		return (DDI_FAILURE);
3610 	ATA_IDLE_COMPONENT(dip, 0);
3611 
3612 	/* enable interrupts from the device */
3613 	io_hdl2 = ata_ctlp->ac_iohandle2;
3614 	ioaddr2 = ata_ctlp->ac_ioaddr2;
3615 	ddi_put8(io_hdl2, (uchar_t *)ioaddr2 + AT_DEVCTL, ATDC_D3);
3616 	ata_ctlp->ac_pm_level = PM_LEVEL_D0;
3617 
3618 	return (DDI_SUCCESS);
3619 }
3620 
3621 /*
3622  * suspend routine, it will be run when get the command
3623  * DDI_SUSPEND at detach(9E) from system power management
3624  */
3625 static int
ata_suspend(dev_info_t * dip)3626 ata_suspend(dev_info_t *dip)
3627 {
3628 	int		instance;
3629 	ata_ctl_t 	*ata_ctlp;
3630 	ddi_acc_handle_t io_hdl2;
3631 
3632 	instance = ddi_get_instance(dip);
3633 	ata_ctlp = ddi_get_soft_state(ata_state, instance);
3634 
3635 	if (!ata_ctlp->ac_pm_support)
3636 		return (DDI_FAILURE);
3637 	if (ata_ctlp->ac_pm_level == PM_LEVEL_D3)
3638 		return (DDI_SUCCESS);
3639 
3640 	/* disable interrupts and turn the software reset bit on */
3641 	io_hdl2 = ata_ctlp->ac_iohandle2;
3642 	ddi_put8(io_hdl2, ata_ctlp->ac_devctl, (ATDC_D3 | ATDC_SRST));
3643 
3644 	(void) ata_reset_bus(ata_ctlp);
3645 	(void) ata_change_power(dip, ATC_SLEEP);
3646 	ata_ctlp->ac_pm_level = PM_LEVEL_D3;
3647 	return (DDI_SUCCESS);
3648 }
3649 
3650 int ata_save_pci_config = 0;
3651 /*
3652  * ata specific power management entry point, it was
3653  * used to change the power management component
3654  */
3655 static int
ata_power(dev_info_t * dip,int component,int level)3656 ata_power(dev_info_t *dip, int component, int level)
3657 {
3658 	int		instance;
3659 	ata_ctl_t 	*ata_ctlp;
3660 	uint8_t		cmd;
3661 
3662 	ADBG_TRACE(("ata_power entered, component = %d, level = %d\n",
3663 	    component, level));
3664 
3665 	instance = ddi_get_instance(dip);
3666 	ata_ctlp = ddi_get_soft_state(ata_state, instance);
3667 	if (ata_ctlp == NULL || component != 0)
3668 		return (DDI_FAILURE);
3669 
3670 	if (!ata_ctlp->ac_pm_support)
3671 		return (DDI_FAILURE);
3672 
3673 	if (ata_ctlp->ac_pm_level == level)
3674 		return (DDI_SUCCESS);
3675 
3676 	switch (level) {
3677 	case PM_LEVEL_D0:
3678 		if (ata_save_pci_config)
3679 			(void) pci_restore_config_regs(dip);
3680 		ata_ctlp->ac_pm_level = PM_LEVEL_D0;
3681 		cmd = ATC_IDLE_IMMED;
3682 		break;
3683 	case PM_LEVEL_D3:
3684 		if (ata_save_pci_config)
3685 			(void) pci_save_config_regs(dip);
3686 		ata_ctlp->ac_pm_level = PM_LEVEL_D3;
3687 		cmd = ATC_SLEEP;
3688 		break;
3689 	default:
3690 		return (DDI_FAILURE);
3691 	}
3692 	return (ata_change_power(dip, cmd));
3693 }
3694 
3695 /*
3696  * sent commands to ata controller to change the power level
3697  */
3698 static int
ata_change_power(dev_info_t * dip,uint8_t cmd)3699 ata_change_power(dev_info_t *dip, uint8_t cmd)
3700 {
3701 	int		instance;
3702 	ata_ctl_t	*ata_ctlp;
3703 	ata_drv_t	*ata_drvp;
3704 	uchar_t		targ;
3705 	struct ata_id	id;
3706 	uchar_t		lun;
3707 	uchar_t		lastlun;
3708 	struct ata_id	*aidp;
3709 
3710 	ADBG_TRACE(("ata_change_power entered, cmd = %d\n", cmd));
3711 
3712 	instance = ddi_get_instance(dip);
3713 	ata_ctlp = ddi_get_soft_state(ata_state, instance);
3714 
3715 	/*
3716 	 * Issue command on each disk device on the bus.
3717 	 */
3718 	if (cmd == ATC_SLEEP) {
3719 		for (targ = 0; targ < ATA_MAXTARG; targ++) {
3720 			ata_drvp = CTL2DRV(ata_ctlp, targ, 0);
3721 			if (ata_drvp == NULL)
3722 				continue;
3723 			if (ata_drvp->ad_dma_cap == 0 &&
3724 			    ata_drvp->ad_pciide_dma == ATA_DMA_ON) {
3725 				aidp = &ata_drvp->ad_id;
3726 				if ((aidp->ai_validinfo & ATAC_VALIDINFO_83) &&
3727 				    (aidp->ai_ultradma & ATAC_UDMA_SEL_MASK)) {
3728 					ata_drvp->ad_dma_cap =
3729 					    ATA_DMA_ULTRAMODE;
3730 					ata_drvp->ad_dma_mode =
3731 					    aidp->ai_ultradma;
3732 				} else if (aidp->ai_dworddma &
3733 				    ATAC_MDMA_SEL_MASK) {
3734 					ata_drvp->ad_dma_cap =
3735 					    ATA_DMA_MWORDMODE;
3736 					ata_drvp->ad_dma_mode =
3737 					    aidp->ai_dworddma;
3738 				}
3739 			}
3740 			if (ata_drive_type(ata_drvp->ad_drive_bits,
3741 			    ata_ctlp->ac_iohandle1, ata_ctlp->ac_ioaddr1,
3742 			    ata_ctlp->ac_iohandle2, ata_ctlp->ac_ioaddr2,
3743 			    &id) != ATA_DEV_DISK)
3744 				continue;
3745 			(void) ata_flush_cache(ata_ctlp, ata_drvp);
3746 			if (!ata_command(ata_ctlp, ata_drvp, TRUE, TRUE,
3747 			    5 * 1000000, cmd, 0, 0, 0, 0, 0, 0)) {
3748 				cmn_err(CE_WARN, "!ata_controller - Can not "
3749 				    "put drive %d in to power mode %u",
3750 				    targ, cmd);
3751 				(void) ata_devo_reset(dip, DDI_RESET_FORCE);
3752 				return (DDI_FAILURE);
3753 			}
3754 		}
3755 		return (DDI_SUCCESS);
3756 	}
3757 
3758 	(void) ata_software_reset(ata_ctlp);
3759 	for (targ = 0; targ < ATA_MAXTARG; targ++) {
3760 		ata_drvp = CTL2DRV(ata_ctlp, targ, 0);
3761 		if (ata_drvp == NULL)
3762 			continue;
3763 		ata_resume_drive(ata_drvp);
3764 
3765 		if (ATAPIDRV(ata_drvp))
3766 			lastlun = ata_drvp->ad_id.ai_lastlun;
3767 		else
3768 			lastlun = 0;
3769 		if (!ata_enable_atapi_luns)
3770 			lastlun = 0;
3771 		for (lun = 1; lun <= lastlun && lun < ATA_MAXLUN; lun++) {
3772 			ata_drvp = CTL2DRV(ata_ctlp, targ, lun);
3773 			if (ata_drvp != NULL)
3774 				ata_resume_drive(ata_drvp);
3775 		}
3776 	}
3777 
3778 	return (DDI_SUCCESS);
3779 }
3780 
3781 /*
3782  * return 1 when ata controller is a pci device,
3783  * otherwise return 0
3784  */
3785 static int
ata_is_pci(dev_info_t * dip)3786 ata_is_pci(dev_info_t *dip)
3787 {
3788 	int rc;
3789 	char *bufp;
3790 	int ispci;
3791 
3792 	rc = ddi_prop_lookup_string(DDI_DEV_T_ANY, ddi_get_parent(dip),
3793 	    DDI_PROP_DONTPASS, "device_type", &bufp);
3794 
3795 	if (rc != DDI_PROP_SUCCESS) {
3796 		ADBG_ERROR(("ata_is_pci !device_type\n"));
3797 		return (0);
3798 	}
3799 
3800 	ispci = (strcmp(bufp, "pci-ide") == 0);
3801 
3802 	ddi_prop_free(bufp);
3803 
3804 	return (ispci);
3805 }
3806 
3807 /*
3808  * Disable DMA for this drive
3809  */
3810 static void
ata_disable_DMA(ata_drv_t * ata_drvp)3811 ata_disable_DMA(ata_drv_t *ata_drvp)
3812 {
3813 	struct ata_id *aidp;
3814 	char buf[sizeof (aidp->ai_model) +2];
3815 	int i;
3816 
3817 	if (ata_drvp == NULL)
3818 		return;
3819 
3820 	if (ata_drvp->ad_pciide_dma == ATA_DMA_OFF)
3821 		return;
3822 
3823 	ata_drvp->ad_pciide_dma = ATA_DMA_OFF;
3824 
3825 	/* Print the message */
3826 	buf[0] = '\0';
3827 	aidp = &ata_drvp->ad_id;
3828 	if (aidp != NULL) {
3829 		(void) strncpy(buf, aidp->ai_model, sizeof (aidp->ai_model));
3830 		buf[sizeof (aidp->ai_model) -1] = '\0';
3831 		for (i = sizeof (aidp->ai_model) - 2; buf[i] == ' '; i--)
3832 			buf[i] = '\0';
3833 	}
3834 	cmn_err(CE_CONT,
3835 	    "?DMA disabled on %s target=%d, lun=%d due to DMA errors,",
3836 	    buf, ata_drvp->ad_targ, ata_drvp->ad_lun);
3837 	cmn_err(CE_CONT, "?most likely due to the CF-to-IDE adapter.");
3838 }
3839 
3840 /*
3841  * Check and select DMA mode
3842  *
3843  * TRUE is returned when set feature is called successfully,
3844  * otherwise return FALSE
3845  */
3846 int
ata_set_dma_mode(ata_ctl_t * ata_ctlp,ata_drv_t * ata_drvp)3847 ata_set_dma_mode(ata_ctl_t *ata_ctlp, ata_drv_t *ata_drvp)
3848 {
3849 	struct ata_id *aidp;
3850 	int mode, rval = FALSE;
3851 	uint8_t subcmd;
3852 
3853 	aidp = &ata_drvp->ad_id;
3854 
3855 	/* Return directly if DMA is not supported */
3856 	if (!(aidp->ai_cap & ATAC_DMA_SUPPORT))
3857 		return (rval);
3858 
3859 	/* Return if DMA mode is already selected */
3860 	if (((aidp->ai_validinfo & ATAC_VALIDINFO_83) &&
3861 	    (aidp->ai_ultradma & ATAC_UDMA_SEL_MASK)) ||
3862 	    (aidp->ai_dworddma & ATAC_MDMA_SEL_MASK))
3863 		return (rval);
3864 
3865 	/* First check Ultra DMA mode if no DMA is selected */
3866 	if ((aidp->ai_validinfo & ATAC_VALIDINFO_83) &&
3867 	    (aidp->ai_ultradma & ATAC_UDMA_SUP_MASK)) {
3868 		for (mode = 6; mode >= 0; --mode) {
3869 			if (aidp->ai_ultradma & (1 << mode))
3870 				break;
3871 		}
3872 		subcmd = ATF_XFRMOD_UDMA;
3873 
3874 	} else if (aidp->ai_dworddma & ATAC_MDMA_SUP_MASK) {
3875 		/* Then check multi-word DMA mode */
3876 		for (mode = 2; mode >= 0; --mode) {
3877 			if (aidp->ai_dworddma & (1 << mode))
3878 				break;
3879 		}
3880 		subcmd = ATF_XFRMOD_MDMA;
3881 
3882 	} else {
3883 		return (rval);
3884 	}
3885 
3886 	rval = ata_set_feature(ata_ctlp, ata_drvp, ATSF_SET_XFRMOD,
3887 	    subcmd|mode);
3888 
3889 	return (rval);
3890 }
3891 
3892 /*
3893  * Reset Ultra DMA mode / MWDMA mode
3894  */
3895 void
ata_reset_dma_mode(ata_drv_t * ata_drvp)3896 ata_reset_dma_mode(ata_drv_t *ata_drvp)
3897 {
3898 	uint8_t	subcmd;
3899 	int	mode;
3900 	ata_ctl_t *ata_ctlp = ata_drvp->ad_ctlp;
3901 
3902 	switch (ata_drvp->ad_dma_cap) {
3903 	case ATA_DMA_ULTRAMODE:
3904 		subcmd = ATF_XFRMOD_UDMA;
3905 		for (mode = 0; mode <= 6; mode++) {
3906 			if (ata_drvp->ad_dma_mode & (1 << (mode + 8)))
3907 				break;
3908 		}
3909 		break;
3910 	case ATA_DMA_MWORDMODE:
3911 		subcmd = ATF_XFRMOD_MDMA;
3912 		mode = ((ata_drvp->ad_dma_mode & ATAC_MDMA_2_SEL) ==
3913 		    ATAC_MDMA_2_SEL ? 2 :
3914 		    (ata_drvp->ad_dma_mode & ATAC_MDMA_1_SEL) ==
3915 		    ATAC_MDMA_1_SEL ? 1 : 0);
3916 		break;
3917 	default:
3918 		return;
3919 	}
3920 
3921 	(void) ata_set_feature(ata_ctlp, ata_drvp, ATSF_SET_XFRMOD,
3922 	    (subcmd | mode));
3923 }
3924 
3925 /*
3926  * Check DMA mode is the same with saved info
3927  * return value: 0 - not same
3928  *		 1 - same
3929  */
3930 static int
ata_check_dma_mode(ata_drv_t * ata_drvp)3931 ata_check_dma_mode(ata_drv_t *ata_drvp)
3932 {
3933 	struct ata_id	*aidp;
3934 
3935 	aidp = &ata_drvp->ad_id;
3936 	switch (ata_drvp->ad_dma_cap) {
3937 	case ATA_DMA_ULTRAMODE:
3938 		if ((aidp->ai_validinfo & ATAC_VALIDINFO_83) &&
3939 		    (aidp->ai_ultradma & ATAC_UDMA_SEL_MASK) &&
3940 		    (aidp->ai_ultradma == ata_drvp->ad_dma_mode))
3941 			break;
3942 		else
3943 			return (0);
3944 	case ATA_DMA_MWORDMODE:
3945 		if ((aidp->ai_dworddma & ATAC_MDMA_SEL_MASK) &&
3946 		    (aidp->ai_dworddma == ata_drvp->ad_dma_mode))
3947 			break;
3948 		else
3949 			return (0);
3950 	default:
3951 		return (0);
3952 	}
3953 	return (1);
3954 }
3955