1 /******************************************************************************
2   SPDX-License-Identifier: BSD-3-Clause
3 
4   Copyright (c) 2001-2017, Intel Corporation
5   All rights reserved.
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33 ******************************************************************************/
34 /*$FreeBSD$*/
35 
36 #include "ixgbe_api.h"
37 #include "ixgbe_common.h"
38 #include "ixgbe_phy.h"
39 
40 static void ixgbe_i2c_start(struct ixgbe_hw *hw);
41 static void ixgbe_i2c_stop(struct ixgbe_hw *hw);
42 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data);
43 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data);
44 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw);
45 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data);
46 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data);
47 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
48 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl);
49 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data);
50 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl);
51 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
52 					  u8 *sff8472_data);
53 
54 /**
55  * ixgbe_out_i2c_byte_ack - Send I2C byte with ack
56  * @hw: pointer to the hardware structure
57  * @byte: byte to send
58  *
59  * Returns an error code on error.
60  */
ixgbe_out_i2c_byte_ack(struct ixgbe_hw * hw,u8 byte)61 static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte)
62 {
63 	s32 status;
64 
65 	status = ixgbe_clock_out_i2c_byte(hw, byte);
66 	if (status)
67 		return status;
68 	return ixgbe_get_i2c_ack(hw);
69 }
70 
71 /**
72  * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack
73  * @hw: pointer to the hardware structure
74  * @byte: pointer to a u8 to receive the byte
75  *
76  * Returns an error code on error.
77  */
ixgbe_in_i2c_byte_ack(struct ixgbe_hw * hw,u8 * byte)78 static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte)
79 {
80 	s32 status;
81 
82 	status = ixgbe_clock_in_i2c_byte(hw, byte);
83 	if (status)
84 		return status;
85 	/* ACK */
86 	return ixgbe_clock_out_i2c_bit(hw, FALSE);
87 }
88 
89 /**
90  * ixgbe_ones_comp_byte_add - Perform one's complement addition
91  * @add1: addend 1
92  * @add2: addend 2
93  *
94  * Returns one's complement 8-bit sum.
95  */
ixgbe_ones_comp_byte_add(u8 add1,u8 add2)96 static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2)
97 {
98 	u16 sum = add1 + add2;
99 
100 	sum = (sum & 0xFF) + (sum >> 8);
101 	return sum & 0xFF;
102 }
103 
104 /**
105  * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation
106  * @hw: pointer to the hardware structure
107  * @addr: I2C bus address to read from
108  * @reg: I2C device register to read from
109  * @val: pointer to location to receive read value
110  * @lock: TRUE if to take and release semaphore
111  *
112  * Returns an error code on error.
113  */
ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 * val,bool lock)114 s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
115 					u16 *val, bool lock)
116 {
117 	u32 swfw_mask = hw->phy.phy_semaphore_mask;
118 	int max_retry = 3;
119 	int retry = 0;
120 	u8 csum_byte;
121 	u8 high_bits;
122 	u8 low_bits;
123 	u8 reg_high;
124 	u8 csum;
125 
126 	reg_high = ((reg >> 7) & 0xFE) | 1;	/* Indicate read combined */
127 	csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
128 	csum = ~csum;
129 	do {
130 		if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
131 			return IXGBE_ERR_SWFW_SYNC;
132 		ixgbe_i2c_start(hw);
133 		/* Device Address and write indication */
134 		if (ixgbe_out_i2c_byte_ack(hw, addr))
135 			goto fail;
136 		/* Write bits 14:8 */
137 		if (ixgbe_out_i2c_byte_ack(hw, reg_high))
138 			goto fail;
139 		/* Write bits 7:0 */
140 		if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
141 			goto fail;
142 		/* Write csum */
143 		if (ixgbe_out_i2c_byte_ack(hw, csum))
144 			goto fail;
145 		/* Re-start condition */
146 		ixgbe_i2c_start(hw);
147 		/* Device Address and read indication */
148 		if (ixgbe_out_i2c_byte_ack(hw, addr | 1))
149 			goto fail;
150 		/* Get upper bits */
151 		if (ixgbe_in_i2c_byte_ack(hw, &high_bits))
152 			goto fail;
153 		/* Get low bits */
154 		if (ixgbe_in_i2c_byte_ack(hw, &low_bits))
155 			goto fail;
156 		/* Get csum */
157 		if (ixgbe_clock_in_i2c_byte(hw, &csum_byte))
158 			goto fail;
159 		/* NACK */
160 		if (ixgbe_clock_out_i2c_bit(hw, FALSE))
161 			goto fail;
162 		ixgbe_i2c_stop(hw);
163 		if (lock)
164 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
165 		*val = (high_bits << 8) | low_bits;
166 		return 0;
167 
168 fail:
169 		ixgbe_i2c_bus_clear(hw);
170 		if (lock)
171 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
172 		retry++;
173 		if (retry < max_retry)
174 			DEBUGOUT("I2C byte read combined error - Retrying.\n");
175 		else
176 			DEBUGOUT("I2C byte read combined error.\n");
177 	} while (retry < max_retry);
178 
179 	return IXGBE_ERR_I2C;
180 }
181 
182 /**
183  * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation
184  * @hw: pointer to the hardware structure
185  * @addr: I2C bus address to write to
186  * @reg: I2C device register to write to
187  * @val: value to write
188  * @lock: TRUE if to take and release semaphore
189  *
190  * Returns an error code on error.
191  */
ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw * hw,u8 addr,u16 reg,u16 val,bool lock)192 s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, u16 reg,
193 					 u16 val, bool lock)
194 {
195 	u32 swfw_mask = hw->phy.phy_semaphore_mask;
196 	int max_retry = 1;
197 	int retry = 0;
198 	u8 reg_high;
199 	u8 csum;
200 
201 	reg_high = (reg >> 7) & 0xFE;	/* Indicate write combined */
202 	csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF);
203 	csum = ixgbe_ones_comp_byte_add(csum, val >> 8);
204 	csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF);
205 	csum = ~csum;
206 	do {
207 		if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
208 			return IXGBE_ERR_SWFW_SYNC;
209 		ixgbe_i2c_start(hw);
210 		/* Device Address and write indication */
211 		if (ixgbe_out_i2c_byte_ack(hw, addr))
212 			goto fail;
213 		/* Write bits 14:8 */
214 		if (ixgbe_out_i2c_byte_ack(hw, reg_high))
215 			goto fail;
216 		/* Write bits 7:0 */
217 		if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF))
218 			goto fail;
219 		/* Write data 15:8 */
220 		if (ixgbe_out_i2c_byte_ack(hw, val >> 8))
221 			goto fail;
222 		/* Write data 7:0 */
223 		if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF))
224 			goto fail;
225 		/* Write csum */
226 		if (ixgbe_out_i2c_byte_ack(hw, csum))
227 			goto fail;
228 		ixgbe_i2c_stop(hw);
229 		if (lock)
230 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
231 		return 0;
232 
233 fail:
234 		ixgbe_i2c_bus_clear(hw);
235 		if (lock)
236 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
237 		retry++;
238 		if (retry < max_retry)
239 			DEBUGOUT("I2C byte write combined error - Retrying.\n");
240 		else
241 			DEBUGOUT("I2C byte write combined error.\n");
242 	} while (retry < max_retry);
243 
244 	return IXGBE_ERR_I2C;
245 }
246 
247 /**
248  *  ixgbe_init_phy_ops_generic - Inits PHY function ptrs
249  *  @hw: pointer to the hardware structure
250  *
251  *  Initialize the function pointers.
252  **/
ixgbe_init_phy_ops_generic(struct ixgbe_hw * hw)253 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw)
254 {
255 	struct ixgbe_phy_info *phy = &hw->phy;
256 
257 	DEBUGFUNC("ixgbe_init_phy_ops_generic");
258 
259 	/* PHY */
260 	phy->ops.identify = ixgbe_identify_phy_generic;
261 	phy->ops.reset = ixgbe_reset_phy_generic;
262 	phy->ops.read_reg = ixgbe_read_phy_reg_generic;
263 	phy->ops.write_reg = ixgbe_write_phy_reg_generic;
264 	phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi;
265 	phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi;
266 	phy->ops.setup_link = ixgbe_setup_phy_link_generic;
267 	phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic;
268 	phy->ops.check_link = NULL;
269 	phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic;
270 	phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic;
271 	phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic;
272 	phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic;
273 	phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic;
274 	phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic;
275 	phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear;
276 	phy->ops.identify_sfp = ixgbe_identify_module_generic;
277 	phy->sfp_type = ixgbe_sfp_type_unknown;
278 	phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked;
279 	phy->ops.write_i2c_byte_unlocked =
280 				ixgbe_write_i2c_byte_generic_unlocked;
281 	phy->ops.check_overtemp = ixgbe_tn_check_overtemp;
282 	return IXGBE_SUCCESS;
283 }
284 
285 /**
286  * ixgbe_probe_phy - Probe a single address for a PHY
287  * @hw: pointer to hardware structure
288  * @phy_addr: PHY address to probe
289  *
290  * Returns TRUE if PHY found
291  */
ixgbe_probe_phy(struct ixgbe_hw * hw,u16 phy_addr)292 static bool ixgbe_probe_phy(struct ixgbe_hw *hw, u16 phy_addr)
293 {
294 	u16 ext_ability = 0;
295 
296 	if (!ixgbe_validate_phy_addr(hw, phy_addr)) {
297 		DEBUGOUT1("Unable to validate PHY address 0x%04X\n",
298 			phy_addr);
299 		return FALSE;
300 	}
301 
302 	if (ixgbe_get_phy_id(hw))
303 		return FALSE;
304 
305 	hw->phy.type = ixgbe_get_phy_type_from_id(hw->phy.id);
306 
307 	if (hw->phy.type == ixgbe_phy_unknown) {
308 		hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY,
309 				     IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability);
310 		if (ext_ability &
311 		    (IXGBE_MDIO_PHY_10GBASET_ABILITY |
312 		     IXGBE_MDIO_PHY_1000BASET_ABILITY))
313 			hw->phy.type = ixgbe_phy_cu_unknown;
314 		else
315 			hw->phy.type = ixgbe_phy_generic;
316 	}
317 
318 	return TRUE;
319 }
320 
321 /**
322  *  ixgbe_identify_phy_generic - Get physical layer module
323  *  @hw: pointer to hardware structure
324  *
325  *  Determines the physical layer module found on the current adapter.
326  **/
ixgbe_identify_phy_generic(struct ixgbe_hw * hw)327 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw)
328 {
329 	s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
330 	u16 phy_addr;
331 
332 	DEBUGFUNC("ixgbe_identify_phy_generic");
333 
334 	if (!hw->phy.phy_semaphore_mask) {
335 		if (hw->bus.lan_id)
336 			hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM;
337 		else
338 			hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM;
339 	}
340 
341 	if (hw->phy.type != ixgbe_phy_unknown)
342 		return IXGBE_SUCCESS;
343 
344 	if (hw->phy.nw_mng_if_sel) {
345 		phy_addr = (hw->phy.nw_mng_if_sel &
346 			    IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD) >>
347 			   IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT;
348 		if (ixgbe_probe_phy(hw, phy_addr))
349 			return IXGBE_SUCCESS;
350 		else
351 			return IXGBE_ERR_PHY_ADDR_INVALID;
352 	}
353 
354 	for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) {
355 		if (ixgbe_probe_phy(hw, phy_addr)) {
356 			status = IXGBE_SUCCESS;
357 			break;
358 		}
359 	}
360 
361 	/* Certain media types do not have a phy so an address will not
362 	 * be found and the code will take this path.  Caller has to
363 	 * decide if it is an error or not.
364 	 */
365 	if (status != IXGBE_SUCCESS)
366 		hw->phy.addr = 0;
367 
368 	return status;
369 }
370 
371 /**
372  * ixgbe_check_reset_blocked - check status of MNG FW veto bit
373  * @hw: pointer to the hardware structure
374  *
375  * This function checks the MMNGC.MNG_VETO bit to see if there are
376  * any constraints on link from manageability.  For MAC's that don't
377  * have this bit just return faluse since the link can not be blocked
378  * via this method.
379  **/
ixgbe_check_reset_blocked(struct ixgbe_hw * hw)380 s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw)
381 {
382 	u32 mmngc;
383 
384 	DEBUGFUNC("ixgbe_check_reset_blocked");
385 
386 	/* If we don't have this bit, it can't be blocking */
387 	if (hw->mac.type == ixgbe_mac_82598EB)
388 		return FALSE;
389 
390 	mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC);
391 	if (mmngc & IXGBE_MMNGC_MNG_VETO) {
392 		ERROR_REPORT1(IXGBE_ERROR_SOFTWARE,
393 			      "MNG_VETO bit detected.\n");
394 		return TRUE;
395 	}
396 
397 	return FALSE;
398 }
399 
400 /**
401  *  ixgbe_validate_phy_addr - Determines phy address is valid
402  *  @hw: pointer to hardware structure
403  *  @phy_addr: PHY address
404  *
405  **/
ixgbe_validate_phy_addr(struct ixgbe_hw * hw,u32 phy_addr)406 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr)
407 {
408 	u16 phy_id = 0;
409 	bool valid = FALSE;
410 
411 	DEBUGFUNC("ixgbe_validate_phy_addr");
412 
413 	hw->phy.addr = phy_addr;
414 	hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
415 			     IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id);
416 
417 	if (phy_id != 0xFFFF && phy_id != 0x0)
418 		valid = TRUE;
419 
420 	DEBUGOUT1("PHY ID HIGH is 0x%04X\n", phy_id);
421 
422 	return valid;
423 }
424 
425 /**
426  *  ixgbe_get_phy_id - Get the phy type
427  *  @hw: pointer to hardware structure
428  *
429  **/
ixgbe_get_phy_id(struct ixgbe_hw * hw)430 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw)
431 {
432 	u32 status;
433 	u16 phy_id_high = 0;
434 	u16 phy_id_low = 0;
435 
436 	DEBUGFUNC("ixgbe_get_phy_id");
437 
438 	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH,
439 				      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
440 				      &phy_id_high);
441 
442 	if (status == IXGBE_SUCCESS) {
443 		hw->phy.id = (u32)(phy_id_high << 16);
444 		status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW,
445 					      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
446 					      &phy_id_low);
447 		hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK);
448 		hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK);
449 	}
450 	DEBUGOUT2("PHY_ID_HIGH 0x%04X, PHY_ID_LOW 0x%04X\n",
451 		  phy_id_high, phy_id_low);
452 
453 	return status;
454 }
455 
456 /**
457  *  ixgbe_get_phy_type_from_id - Get the phy type
458  *  @phy_id: PHY ID information
459  *
460  **/
ixgbe_get_phy_type_from_id(u32 phy_id)461 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id)
462 {
463 	enum ixgbe_phy_type phy_type;
464 
465 	DEBUGFUNC("ixgbe_get_phy_type_from_id");
466 
467 	switch (phy_id) {
468 	case TN1010_PHY_ID:
469 		phy_type = ixgbe_phy_tn;
470 		break;
471 	case X550_PHY_ID2:
472 	case X550_PHY_ID3:
473 	case X540_PHY_ID:
474 		phy_type = ixgbe_phy_aq;
475 		break;
476 	case QT2022_PHY_ID:
477 		phy_type = ixgbe_phy_qt;
478 		break;
479 	case ATH_PHY_ID:
480 		phy_type = ixgbe_phy_nl;
481 		break;
482 	case X557_PHY_ID:
483 	case X557_PHY_ID2:
484 		phy_type = ixgbe_phy_x550em_ext_t;
485 		break;
486 	case IXGBE_M88E1500_E_PHY_ID:
487 	case IXGBE_M88E1543_E_PHY_ID:
488 		phy_type = ixgbe_phy_ext_1g_t;
489 		break;
490 	default:
491 		phy_type = ixgbe_phy_unknown;
492 		break;
493 	}
494 	return phy_type;
495 }
496 
497 /**
498  *  ixgbe_reset_phy_generic - Performs a PHY reset
499  *  @hw: pointer to hardware structure
500  **/
ixgbe_reset_phy_generic(struct ixgbe_hw * hw)501 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw)
502 {
503 	u32 i;
504 	u16 ctrl = 0;
505 	s32 status = IXGBE_SUCCESS;
506 
507 	DEBUGFUNC("ixgbe_reset_phy_generic");
508 
509 	if (hw->phy.type == ixgbe_phy_unknown)
510 		status = ixgbe_identify_phy_generic(hw);
511 
512 	if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none)
513 		goto out;
514 
515 	/* Don't reset PHY if it's shut down due to overtemp. */
516 	if (!hw->phy.reset_if_overtemp &&
517 	    (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw)))
518 		goto out;
519 
520 	/* Blocked by MNG FW so bail */
521 	if (ixgbe_check_reset_blocked(hw))
522 		goto out;
523 
524 	/*
525 	 * Perform soft PHY reset to the PHY_XS.
526 	 * This will cause a soft reset to the PHY
527 	 */
528 	hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
529 			      IXGBE_MDIO_PHY_XS_DEV_TYPE,
530 			      IXGBE_MDIO_PHY_XS_RESET);
531 
532 	/*
533 	 * Poll for reset bit to self-clear indicating reset is complete.
534 	 * Some PHYs could take up to 3 seconds to complete and need about
535 	 * 1.7 usec delay after the reset is complete.
536 	 */
537 	for (i = 0; i < 30; i++) {
538 		msec_delay(100);
539 		if (hw->phy.type == ixgbe_phy_x550em_ext_t) {
540 			status = hw->phy.ops.read_reg(hw,
541 						  IXGBE_MDIO_TX_VENDOR_ALARMS_3,
542 						  IXGBE_MDIO_PMA_PMD_DEV_TYPE,
543 						  &ctrl);
544 			if (status != IXGBE_SUCCESS)
545 				return status;
546 
547 			if (ctrl & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) {
548 				usec_delay(2);
549 				break;
550 			}
551 		} else {
552 			status = hw->phy.ops.read_reg(hw,
553 						     IXGBE_MDIO_PHY_XS_CONTROL,
554 						     IXGBE_MDIO_PHY_XS_DEV_TYPE,
555 						     &ctrl);
556 			if (status != IXGBE_SUCCESS)
557 				return status;
558 
559 			if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) {
560 				usec_delay(2);
561 				break;
562 			}
563 		}
564 	}
565 
566 	if (ctrl & IXGBE_MDIO_PHY_XS_RESET) {
567 		status = IXGBE_ERR_RESET_FAILED;
568 		ERROR_REPORT1(IXGBE_ERROR_POLLING,
569 			     "PHY reset polling failed to complete.\n");
570 	}
571 
572 out:
573 	return status;
574 }
575 
576 /**
577  *  ixgbe_read_phy_mdi - Reads a value from a specified PHY register without
578  *  the SWFW lock
579  *  @hw: pointer to hardware structure
580  *  @reg_addr: 32 bit address of PHY register to read
581  *  @device_type: 5 bit device type
582  *  @phy_data: Pointer to read data from PHY register
583  **/
ixgbe_read_phy_reg_mdi(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)584 s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type,
585 			   u16 *phy_data)
586 {
587 	u32 i, data, command;
588 
589 	/* Setup and write the address cycle command */
590 	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
591 		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
592 		   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
593 		   (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
594 
595 	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
596 
597 	/*
598 	 * Check every 10 usec to see if the address cycle completed.
599 	 * The MDI Command bit will clear when the operation is
600 	 * complete
601 	 */
602 	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
603 		usec_delay(10);
604 
605 		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
606 		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
607 			break;
608 	}
609 
610 
611 	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
612 		ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n");
613 		DEBUGOUT("PHY address command did not complete, returning IXGBE_ERR_PHY\n");
614 		return IXGBE_ERR_PHY;
615 	}
616 
617 	/*
618 	 * Address cycle complete, setup and write the read
619 	 * command
620 	 */
621 	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
622 		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
623 		   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
624 		   (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND));
625 
626 	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
627 
628 	/*
629 	 * Check every 10 usec to see if the address cycle
630 	 * completed. The MDI Command bit will clear when the
631 	 * operation is complete
632 	 */
633 	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
634 		usec_delay(10);
635 
636 		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
637 		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
638 			break;
639 	}
640 
641 	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
642 		ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n");
643 		DEBUGOUT("PHY read command didn't complete, returning IXGBE_ERR_PHY\n");
644 		return IXGBE_ERR_PHY;
645 	}
646 
647 	/*
648 	 * Read operation is complete.  Get the data
649 	 * from MSRWD
650 	 */
651 	data = IXGBE_READ_REG(hw, IXGBE_MSRWD);
652 	data >>= IXGBE_MSRWD_READ_DATA_SHIFT;
653 	*phy_data = (u16)(data);
654 
655 	return IXGBE_SUCCESS;
656 }
657 
658 /**
659  *  ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register
660  *  using the SWFW lock - this function is needed in most cases
661  *  @hw: pointer to hardware structure
662  *  @reg_addr: 32 bit address of PHY register to read
663  *  @device_type: 5 bit device type
664  *  @phy_data: Pointer to read data from PHY register
665  **/
ixgbe_read_phy_reg_generic(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 * phy_data)666 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
667 			       u32 device_type, u16 *phy_data)
668 {
669 	s32 status;
670 	u32 gssr = hw->phy.phy_semaphore_mask;
671 
672 	DEBUGFUNC("ixgbe_read_phy_reg_generic");
673 
674 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr))
675 		return IXGBE_ERR_SWFW_SYNC;
676 
677 	status = hw->phy.ops.read_reg_mdi(hw, reg_addr, device_type, phy_data);
678 
679 	hw->mac.ops.release_swfw_sync(hw, gssr);
680 
681 	return status;
682 }
683 
684 /**
685  *  ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register
686  *  without SWFW lock
687  *  @hw: pointer to hardware structure
688  *  @reg_addr: 32 bit PHY register to write
689  *  @device_type: 5 bit device type
690  *  @phy_data: Data to write to the PHY register
691  **/
ixgbe_write_phy_reg_mdi(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)692 s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr,
693 				u32 device_type, u16 phy_data)
694 {
695 	u32 i, command;
696 
697 	/* Put the data in the MDI single read and write data register*/
698 	IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data);
699 
700 	/* Setup and write the address cycle command */
701 	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
702 		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
703 		   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
704 		   (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND));
705 
706 	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
707 
708 	/*
709 	 * Check every 10 usec to see if the address cycle completed.
710 	 * The MDI Command bit will clear when the operation is
711 	 * complete
712 	 */
713 	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
714 		usec_delay(10);
715 
716 		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
717 		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
718 			break;
719 	}
720 
721 	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
722 		ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n");
723 		return IXGBE_ERR_PHY;
724 	}
725 
726 	/*
727 	 * Address cycle complete, setup and write the write
728 	 * command
729 	 */
730 	command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT)  |
731 		   (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) |
732 		   (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) |
733 		   (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND));
734 
735 	IXGBE_WRITE_REG(hw, IXGBE_MSCA, command);
736 
737 	/*
738 	 * Check every 10 usec to see if the address cycle
739 	 * completed. The MDI Command bit will clear when the
740 	 * operation is complete
741 	 */
742 	for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) {
743 		usec_delay(10);
744 
745 		command = IXGBE_READ_REG(hw, IXGBE_MSCA);
746 		if ((command & IXGBE_MSCA_MDI_COMMAND) == 0)
747 			break;
748 	}
749 
750 	if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) {
751 		ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n");
752 		return IXGBE_ERR_PHY;
753 	}
754 
755 	return IXGBE_SUCCESS;
756 }
757 
758 /**
759  *  ixgbe_write_phy_reg_generic - Writes a value to specified PHY register
760  *  using SWFW lock- this function is needed in most cases
761  *  @hw: pointer to hardware structure
762  *  @reg_addr: 32 bit PHY register to write
763  *  @device_type: 5 bit device type
764  *  @phy_data: Data to write to the PHY register
765  **/
ixgbe_write_phy_reg_generic(struct ixgbe_hw * hw,u32 reg_addr,u32 device_type,u16 phy_data)766 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
767 				u32 device_type, u16 phy_data)
768 {
769 	s32 status;
770 	u32 gssr = hw->phy.phy_semaphore_mask;
771 
772 	DEBUGFUNC("ixgbe_write_phy_reg_generic");
773 
774 	if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) {
775 		status = hw->phy.ops.write_reg_mdi(hw, reg_addr, device_type,
776 						 phy_data);
777 		hw->mac.ops.release_swfw_sync(hw, gssr);
778 	} else {
779 		status = IXGBE_ERR_SWFW_SYNC;
780 	}
781 
782 	return status;
783 }
784 
785 /**
786  *  ixgbe_setup_phy_link_generic - Set and restart auto-neg
787  *  @hw: pointer to hardware structure
788  *
789  *  Restart auto-negotiation and PHY and waits for completion.
790  **/
ixgbe_setup_phy_link_generic(struct ixgbe_hw * hw)791 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw)
792 {
793 	s32 status = IXGBE_SUCCESS;
794 	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
795 	bool autoneg = FALSE;
796 	ixgbe_link_speed speed;
797 
798 	DEBUGFUNC("ixgbe_setup_phy_link_generic");
799 
800 	ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
801 
802 	/* Set or unset auto-negotiation 10G advertisement */
803 	hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
804 			     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
805 			     &autoneg_reg);
806 
807 	autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
808 	if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) &&
809 	    (speed & IXGBE_LINK_SPEED_10GB_FULL))
810 		autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
811 
812 	hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
813 			      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
814 			      autoneg_reg);
815 
816 	hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
817 			     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
818 			     &autoneg_reg);
819 
820 	if (hw->mac.type == ixgbe_mac_X550) {
821 		/* Set or unset auto-negotiation 5G advertisement */
822 		autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE;
823 		if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_5GB_FULL) &&
824 		    (speed & IXGBE_LINK_SPEED_5GB_FULL))
825 			autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE;
826 
827 		/* Set or unset auto-negotiation 2.5G advertisement */
828 		autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE;
829 		if ((hw->phy.autoneg_advertised &
830 		     IXGBE_LINK_SPEED_2_5GB_FULL) &&
831 		    (speed & IXGBE_LINK_SPEED_2_5GB_FULL))
832 			autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE;
833 	}
834 
835 	/* Set or unset auto-negotiation 1G advertisement */
836 	autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE;
837 	if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) &&
838 	    (speed & IXGBE_LINK_SPEED_1GB_FULL))
839 		autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE;
840 
841 	hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG,
842 			      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
843 			      autoneg_reg);
844 
845 	/* Set or unset auto-negotiation 100M advertisement */
846 	hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
847 			     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
848 			     &autoneg_reg);
849 
850 	autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE |
851 			 IXGBE_MII_100BASE_T_ADVERTISE_HALF);
852 	if ((hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) &&
853 	    (speed & IXGBE_LINK_SPEED_100_FULL))
854 		autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
855 
856 	hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
857 			      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
858 			      autoneg_reg);
859 
860 	/* Blocked by MNG FW so don't reset PHY */
861 	if (ixgbe_check_reset_blocked(hw))
862 		return status;
863 
864 	/* Restart PHY auto-negotiation. */
865 	hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
866 			     IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
867 
868 	autoneg_reg |= IXGBE_MII_RESTART;
869 
870 	hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
871 			      IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
872 
873 	return status;
874 }
875 
876 /**
877  *  ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities
878  *  @hw: pointer to hardware structure
879  *  @speed: new link speed
880  *  @autoneg_wait_to_complete: unused
881  **/
ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw * hw,ixgbe_link_speed speed,bool autoneg_wait_to_complete)882 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
883 				       ixgbe_link_speed speed,
884 				       bool autoneg_wait_to_complete)
885 {
886 	UNREFERENCED_1PARAMETER(autoneg_wait_to_complete);
887 
888 	DEBUGFUNC("ixgbe_setup_phy_link_speed_generic");
889 
890 	/*
891 	 * Clear autoneg_advertised and set new values based on input link
892 	 * speed.
893 	 */
894 	hw->phy.autoneg_advertised = 0;
895 
896 	if (speed & IXGBE_LINK_SPEED_10GB_FULL)
897 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL;
898 
899 	if (speed & IXGBE_LINK_SPEED_5GB_FULL)
900 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL;
901 
902 	if (speed & IXGBE_LINK_SPEED_2_5GB_FULL)
903 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL;
904 
905 	if (speed & IXGBE_LINK_SPEED_1GB_FULL)
906 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL;
907 
908 	if (speed & IXGBE_LINK_SPEED_100_FULL)
909 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL;
910 
911 	if (speed & IXGBE_LINK_SPEED_10_FULL)
912 		hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10_FULL;
913 
914 	/* Setup link based on the new speed settings */
915 	ixgbe_setup_phy_link(hw);
916 
917 	return IXGBE_SUCCESS;
918 }
919 
920 /**
921  * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy
922  * @hw: pointer to hardware structure
923  *
924  * Determines the supported link capabilities by reading the PHY auto
925  * negotiation register.
926  **/
ixgbe_get_copper_speeds_supported(struct ixgbe_hw * hw)927 static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw)
928 {
929 	s32 status;
930 	u16 speed_ability;
931 
932 	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY,
933 				      IXGBE_MDIO_PMA_PMD_DEV_TYPE,
934 				      &speed_ability);
935 	if (status)
936 		return status;
937 
938 	if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G)
939 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL;
940 	if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G)
941 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL;
942 	if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M)
943 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL;
944 
945 	switch (hw->mac.type) {
946 	case ixgbe_mac_X550:
947 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL;
948 		hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL;
949 		break;
950 	case ixgbe_mac_X550EM_x:
951 	case ixgbe_mac_X550EM_a:
952 		hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL;
953 		break;
954 	default:
955 		break;
956 	}
957 
958 	return status;
959 }
960 
961 /**
962  *  ixgbe_get_copper_link_capabilities_generic - Determines link capabilities
963  *  @hw: pointer to hardware structure
964  *  @speed: pointer to link speed
965  *  @autoneg: boolean auto-negotiation value
966  **/
ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * autoneg)967 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
968 					       ixgbe_link_speed *speed,
969 					       bool *autoneg)
970 {
971 	s32 status = IXGBE_SUCCESS;
972 
973 	DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic");
974 
975 	*autoneg = TRUE;
976 	if (!hw->phy.speeds_supported)
977 		status = ixgbe_get_copper_speeds_supported(hw);
978 
979 	*speed = hw->phy.speeds_supported;
980 	return status;
981 }
982 
983 /**
984  *  ixgbe_check_phy_link_tnx - Determine link and speed status
985  *  @hw: pointer to hardware structure
986  *  @speed: current link speed
987  *  @link_up: TRUE is link is up, FALSE otherwise
988  *
989  *  Reads the VS1 register to determine if link is up and the current speed for
990  *  the PHY.
991  **/
ixgbe_check_phy_link_tnx(struct ixgbe_hw * hw,ixgbe_link_speed * speed,bool * link_up)992 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed,
993 			     bool *link_up)
994 {
995 	s32 status = IXGBE_SUCCESS;
996 	u32 time_out;
997 	u32 max_time_out = 10;
998 	u16 phy_link = 0;
999 	u16 phy_speed = 0;
1000 	u16 phy_data = 0;
1001 
1002 	DEBUGFUNC("ixgbe_check_phy_link_tnx");
1003 
1004 	/* Initialize speed and link to default case */
1005 	*link_up = FALSE;
1006 	*speed = IXGBE_LINK_SPEED_10GB_FULL;
1007 
1008 	/*
1009 	 * Check current speed and link status of the PHY register.
1010 	 * This is a vendor specific register and may have to
1011 	 * be changed for other copper PHYs.
1012 	 */
1013 	for (time_out = 0; time_out < max_time_out; time_out++) {
1014 		usec_delay(10);
1015 		status = hw->phy.ops.read_reg(hw,
1016 					IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS,
1017 					IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1018 					&phy_data);
1019 		phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS;
1020 		phy_speed = phy_data &
1021 				 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS;
1022 		if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) {
1023 			*link_up = TRUE;
1024 			if (phy_speed ==
1025 			    IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS)
1026 				*speed = IXGBE_LINK_SPEED_1GB_FULL;
1027 			break;
1028 		}
1029 	}
1030 
1031 	return status;
1032 }
1033 
1034 /**
1035  *	ixgbe_setup_phy_link_tnx - Set and restart auto-neg
1036  *	@hw: pointer to hardware structure
1037  *
1038  *	Restart auto-negotiation and PHY and waits for completion.
1039  **/
ixgbe_setup_phy_link_tnx(struct ixgbe_hw * hw)1040 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw)
1041 {
1042 	s32 status = IXGBE_SUCCESS;
1043 	u16 autoneg_reg = IXGBE_MII_AUTONEG_REG;
1044 	bool autoneg = FALSE;
1045 	ixgbe_link_speed speed;
1046 
1047 	DEBUGFUNC("ixgbe_setup_phy_link_tnx");
1048 
1049 	ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg);
1050 
1051 	if (speed & IXGBE_LINK_SPEED_10GB_FULL) {
1052 		/* Set or unset auto-negotiation 10G advertisement */
1053 		hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1054 				     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1055 				     &autoneg_reg);
1056 
1057 		autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE;
1058 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL)
1059 			autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE;
1060 
1061 		hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG,
1062 				      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1063 				      autoneg_reg);
1064 	}
1065 
1066 	if (speed & IXGBE_LINK_SPEED_1GB_FULL) {
1067 		/* Set or unset auto-negotiation 1G advertisement */
1068 		hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1069 				     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1070 				     &autoneg_reg);
1071 
1072 		autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1073 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL)
1074 			autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX;
1075 
1076 		hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG,
1077 				      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1078 				      autoneg_reg);
1079 	}
1080 
1081 	if (speed & IXGBE_LINK_SPEED_100_FULL) {
1082 		/* Set or unset auto-negotiation 100M advertisement */
1083 		hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1084 				     IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1085 				     &autoneg_reg);
1086 
1087 		autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE;
1088 		if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL)
1089 			autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE;
1090 
1091 		hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG,
1092 				      IXGBE_MDIO_AUTO_NEG_DEV_TYPE,
1093 				      autoneg_reg);
1094 	}
1095 
1096 	/* Blocked by MNG FW so don't reset PHY */
1097 	if (ixgbe_check_reset_blocked(hw))
1098 		return status;
1099 
1100 	/* Restart PHY auto-negotiation. */
1101 	hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1102 			     IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg);
1103 
1104 	autoneg_reg |= IXGBE_MII_RESTART;
1105 
1106 	hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL,
1107 			      IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg);
1108 
1109 	return status;
1110 }
1111 
1112 /**
1113  *  ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version
1114  *  @hw: pointer to hardware structure
1115  *  @firmware_version: pointer to the PHY Firmware Version
1116  **/
ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw * hw,u16 * firmware_version)1117 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
1118 				       u16 *firmware_version)
1119 {
1120 	s32 status;
1121 
1122 	DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx");
1123 
1124 	status = hw->phy.ops.read_reg(hw, TNX_FW_REV,
1125 				      IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1126 				      firmware_version);
1127 
1128 	return status;
1129 }
1130 
1131 /**
1132  *  ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version
1133  *  @hw: pointer to hardware structure
1134  *  @firmware_version: pointer to the PHY Firmware Version
1135  **/
ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw * hw,u16 * firmware_version)1136 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
1137 					   u16 *firmware_version)
1138 {
1139 	s32 status;
1140 
1141 	DEBUGFUNC("ixgbe_get_phy_firmware_version_generic");
1142 
1143 	status = hw->phy.ops.read_reg(hw, AQ_FW_REV,
1144 				      IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
1145 				      firmware_version);
1146 
1147 	return status;
1148 }
1149 
1150 /**
1151  *  ixgbe_reset_phy_nl - Performs a PHY reset
1152  *  @hw: pointer to hardware structure
1153  **/
ixgbe_reset_phy_nl(struct ixgbe_hw * hw)1154 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw)
1155 {
1156 	u16 phy_offset, control, eword, edata, block_crc;
1157 	bool end_data = FALSE;
1158 	u16 list_offset, data_offset;
1159 	u16 phy_data = 0;
1160 	s32 ret_val = IXGBE_SUCCESS;
1161 	u32 i;
1162 
1163 	DEBUGFUNC("ixgbe_reset_phy_nl");
1164 
1165 	/* Blocked by MNG FW so bail */
1166 	if (ixgbe_check_reset_blocked(hw))
1167 		goto out;
1168 
1169 	hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1170 			     IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1171 
1172 	/* reset the PHY and poll for completion */
1173 	hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1174 			      IXGBE_MDIO_PHY_XS_DEV_TYPE,
1175 			      (phy_data | IXGBE_MDIO_PHY_XS_RESET));
1176 
1177 	for (i = 0; i < 100; i++) {
1178 		hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL,
1179 				     IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data);
1180 		if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0)
1181 			break;
1182 		msec_delay(10);
1183 	}
1184 
1185 	if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) {
1186 		DEBUGOUT("PHY reset did not complete.\n");
1187 		ret_val = IXGBE_ERR_PHY;
1188 		goto out;
1189 	}
1190 
1191 	/* Get init offsets */
1192 	ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset,
1193 						      &data_offset);
1194 	if (ret_val != IXGBE_SUCCESS)
1195 		goto out;
1196 
1197 	ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc);
1198 	data_offset++;
1199 	while (!end_data) {
1200 		/*
1201 		 * Read control word from PHY init contents offset
1202 		 */
1203 		ret_val = hw->eeprom.ops.read(hw, data_offset, &eword);
1204 		if (ret_val)
1205 			goto err_eeprom;
1206 		control = (eword & IXGBE_CONTROL_MASK_NL) >>
1207 			   IXGBE_CONTROL_SHIFT_NL;
1208 		edata = eword & IXGBE_DATA_MASK_NL;
1209 		switch (control) {
1210 		case IXGBE_DELAY_NL:
1211 			data_offset++;
1212 			DEBUGOUT1("DELAY: %d MS\n", edata);
1213 			msec_delay(edata);
1214 			break;
1215 		case IXGBE_DATA_NL:
1216 			DEBUGOUT("DATA:\n");
1217 			data_offset++;
1218 			ret_val = hw->eeprom.ops.read(hw, data_offset,
1219 						      &phy_offset);
1220 			if (ret_val)
1221 				goto err_eeprom;
1222 			data_offset++;
1223 			for (i = 0; i < edata; i++) {
1224 				ret_val = hw->eeprom.ops.read(hw, data_offset,
1225 							      &eword);
1226 				if (ret_val)
1227 					goto err_eeprom;
1228 				hw->phy.ops.write_reg(hw, phy_offset,
1229 						      IXGBE_TWINAX_DEV, eword);
1230 				DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword,
1231 					  phy_offset);
1232 				data_offset++;
1233 				phy_offset++;
1234 			}
1235 			break;
1236 		case IXGBE_CONTROL_NL:
1237 			data_offset++;
1238 			DEBUGOUT("CONTROL:\n");
1239 			if (edata == IXGBE_CONTROL_EOL_NL) {
1240 				DEBUGOUT("EOL\n");
1241 				end_data = TRUE;
1242 			} else if (edata == IXGBE_CONTROL_SOL_NL) {
1243 				DEBUGOUT("SOL\n");
1244 			} else {
1245 				DEBUGOUT("Bad control value\n");
1246 				ret_val = IXGBE_ERR_PHY;
1247 				goto out;
1248 			}
1249 			break;
1250 		default:
1251 			DEBUGOUT("Bad control type\n");
1252 			ret_val = IXGBE_ERR_PHY;
1253 			goto out;
1254 		}
1255 	}
1256 
1257 out:
1258 	return ret_val;
1259 
1260 err_eeprom:
1261 	ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1262 		      "eeprom read at offset %d failed", data_offset);
1263 	return IXGBE_ERR_PHY;
1264 }
1265 
1266 /**
1267  *  ixgbe_identify_module_generic - Identifies module type
1268  *  @hw: pointer to hardware structure
1269  *
1270  *  Determines HW type and calls appropriate function.
1271  **/
ixgbe_identify_module_generic(struct ixgbe_hw * hw)1272 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw)
1273 {
1274 	s32 status = IXGBE_ERR_SFP_NOT_PRESENT;
1275 
1276 	DEBUGFUNC("ixgbe_identify_module_generic");
1277 
1278 	switch (hw->mac.ops.get_media_type(hw)) {
1279 	case ixgbe_media_type_fiber:
1280 		status = ixgbe_identify_sfp_module_generic(hw);
1281 		break;
1282 
1283 	case ixgbe_media_type_fiber_qsfp:
1284 		status = ixgbe_identify_qsfp_module_generic(hw);
1285 		break;
1286 
1287 	default:
1288 		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1289 		status = IXGBE_ERR_SFP_NOT_PRESENT;
1290 		break;
1291 	}
1292 
1293 	return status;
1294 }
1295 
1296 /**
1297  *  ixgbe_identify_sfp_module_generic - Identifies SFP modules
1298  *  @hw: pointer to hardware structure
1299  *
1300  *  Searches for and identifies the SFP module and assigns appropriate PHY type.
1301  **/
ixgbe_identify_sfp_module_generic(struct ixgbe_hw * hw)1302 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw)
1303 {
1304 	s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1305 	u32 vendor_oui = 0;
1306 	enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1307 	u8 identifier = 0;
1308 	u8 comp_codes_1g = 0;
1309 	u8 comp_codes_10g = 0;
1310 	u8 oui_bytes[3] = {0, 0, 0};
1311 	u8 cable_tech = 0;
1312 	u8 cable_spec = 0;
1313 	u16 enforce_sfp = 0;
1314 
1315 	DEBUGFUNC("ixgbe_identify_sfp_module_generic");
1316 
1317 	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) {
1318 		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1319 		status = IXGBE_ERR_SFP_NOT_PRESENT;
1320 		goto out;
1321 	}
1322 
1323 	/* LAN ID is needed for I2C access */
1324 	hw->mac.ops.set_lan_id(hw);
1325 
1326 	status = hw->phy.ops.read_i2c_eeprom(hw,
1327 					     IXGBE_SFF_IDENTIFIER,
1328 					     &identifier);
1329 
1330 	if (status != IXGBE_SUCCESS)
1331 		goto err_read_i2c_eeprom;
1332 
1333 	if (identifier != IXGBE_SFF_IDENTIFIER_SFP) {
1334 		hw->phy.type = ixgbe_phy_sfp_unsupported;
1335 		status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1336 	} else {
1337 		status = hw->phy.ops.read_i2c_eeprom(hw,
1338 						     IXGBE_SFF_1GBE_COMP_CODES,
1339 						     &comp_codes_1g);
1340 
1341 		if (status != IXGBE_SUCCESS)
1342 			goto err_read_i2c_eeprom;
1343 
1344 		status = hw->phy.ops.read_i2c_eeprom(hw,
1345 						     IXGBE_SFF_10GBE_COMP_CODES,
1346 						     &comp_codes_10g);
1347 
1348 		if (status != IXGBE_SUCCESS)
1349 			goto err_read_i2c_eeprom;
1350 		status = hw->phy.ops.read_i2c_eeprom(hw,
1351 						     IXGBE_SFF_CABLE_TECHNOLOGY,
1352 						     &cable_tech);
1353 
1354 		if (status != IXGBE_SUCCESS)
1355 			goto err_read_i2c_eeprom;
1356 
1357 		 /* ID Module
1358 		  * =========
1359 		  * 0   SFP_DA_CU
1360 		  * 1   SFP_SR
1361 		  * 2   SFP_LR
1362 		  * 3   SFP_DA_CORE0 - 82599-specific
1363 		  * 4   SFP_DA_CORE1 - 82599-specific
1364 		  * 5   SFP_SR/LR_CORE0 - 82599-specific
1365 		  * 6   SFP_SR/LR_CORE1 - 82599-specific
1366 		  * 7   SFP_act_lmt_DA_CORE0 - 82599-specific
1367 		  * 8   SFP_act_lmt_DA_CORE1 - 82599-specific
1368 		  * 9   SFP_1g_cu_CORE0 - 82599-specific
1369 		  * 10  SFP_1g_cu_CORE1 - 82599-specific
1370 		  * 11  SFP_1g_sx_CORE0 - 82599-specific
1371 		  * 12  SFP_1g_sx_CORE1 - 82599-specific
1372 		  */
1373 		if (hw->mac.type == ixgbe_mac_82598EB) {
1374 			if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1375 				hw->phy.sfp_type = ixgbe_sfp_type_da_cu;
1376 			else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1377 				hw->phy.sfp_type = ixgbe_sfp_type_sr;
1378 			else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1379 				hw->phy.sfp_type = ixgbe_sfp_type_lr;
1380 			else
1381 				hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1382 		} else {
1383 			if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) {
1384 				if (hw->bus.lan_id == 0)
1385 					hw->phy.sfp_type =
1386 						     ixgbe_sfp_type_da_cu_core0;
1387 				else
1388 					hw->phy.sfp_type =
1389 						     ixgbe_sfp_type_da_cu_core1;
1390 			} else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) {
1391 				hw->phy.ops.read_i2c_eeprom(
1392 						hw, IXGBE_SFF_CABLE_SPEC_COMP,
1393 						&cable_spec);
1394 				if (cable_spec &
1395 				    IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) {
1396 					if (hw->bus.lan_id == 0)
1397 						hw->phy.sfp_type =
1398 						ixgbe_sfp_type_da_act_lmt_core0;
1399 					else
1400 						hw->phy.sfp_type =
1401 						ixgbe_sfp_type_da_act_lmt_core1;
1402 				} else {
1403 					hw->phy.sfp_type =
1404 							ixgbe_sfp_type_unknown;
1405 				}
1406 			} else if (comp_codes_10g &
1407 				   (IXGBE_SFF_10GBASESR_CAPABLE |
1408 				    IXGBE_SFF_10GBASELR_CAPABLE)) {
1409 				if (hw->bus.lan_id == 0)
1410 					hw->phy.sfp_type =
1411 						      ixgbe_sfp_type_srlr_core0;
1412 				else
1413 					hw->phy.sfp_type =
1414 						      ixgbe_sfp_type_srlr_core1;
1415 			} else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) {
1416 				if (hw->bus.lan_id == 0)
1417 					hw->phy.sfp_type =
1418 						ixgbe_sfp_type_1g_cu_core0;
1419 				else
1420 					hw->phy.sfp_type =
1421 						ixgbe_sfp_type_1g_cu_core1;
1422 			} else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) {
1423 				if (hw->bus.lan_id == 0)
1424 					hw->phy.sfp_type =
1425 						ixgbe_sfp_type_1g_sx_core0;
1426 				else
1427 					hw->phy.sfp_type =
1428 						ixgbe_sfp_type_1g_sx_core1;
1429 			} else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) {
1430 				if (hw->bus.lan_id == 0)
1431 					hw->phy.sfp_type =
1432 						ixgbe_sfp_type_1g_lx_core0;
1433 				else
1434 					hw->phy.sfp_type =
1435 						ixgbe_sfp_type_1g_lx_core1;
1436 			} else {
1437 				hw->phy.sfp_type = ixgbe_sfp_type_unknown;
1438 			}
1439 		}
1440 
1441 		if (hw->phy.sfp_type != stored_sfp_type)
1442 			hw->phy.sfp_setup_needed = TRUE;
1443 
1444 		/* Determine if the SFP+ PHY is dual speed or not. */
1445 		hw->phy.multispeed_fiber = FALSE;
1446 		if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1447 		   (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1448 		   ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1449 		   (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1450 			hw->phy.multispeed_fiber = TRUE;
1451 
1452 		/* Determine PHY vendor */
1453 		if (hw->phy.type != ixgbe_phy_nl) {
1454 			hw->phy.id = identifier;
1455 			status = hw->phy.ops.read_i2c_eeprom(hw,
1456 						    IXGBE_SFF_VENDOR_OUI_BYTE0,
1457 						    &oui_bytes[0]);
1458 
1459 			if (status != IXGBE_SUCCESS)
1460 				goto err_read_i2c_eeprom;
1461 
1462 			status = hw->phy.ops.read_i2c_eeprom(hw,
1463 						    IXGBE_SFF_VENDOR_OUI_BYTE1,
1464 						    &oui_bytes[1]);
1465 
1466 			if (status != IXGBE_SUCCESS)
1467 				goto err_read_i2c_eeprom;
1468 
1469 			status = hw->phy.ops.read_i2c_eeprom(hw,
1470 						    IXGBE_SFF_VENDOR_OUI_BYTE2,
1471 						    &oui_bytes[2]);
1472 
1473 			if (status != IXGBE_SUCCESS)
1474 				goto err_read_i2c_eeprom;
1475 
1476 			vendor_oui =
1477 			  ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1478 			   (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1479 			   (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1480 
1481 			switch (vendor_oui) {
1482 			case IXGBE_SFF_VENDOR_OUI_TYCO:
1483 				if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1484 					hw->phy.type =
1485 						    ixgbe_phy_sfp_passive_tyco;
1486 				break;
1487 			case IXGBE_SFF_VENDOR_OUI_FTL:
1488 				if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1489 					hw->phy.type = ixgbe_phy_sfp_ftl_active;
1490 				else
1491 					hw->phy.type = ixgbe_phy_sfp_ftl;
1492 				break;
1493 			case IXGBE_SFF_VENDOR_OUI_AVAGO:
1494 				hw->phy.type = ixgbe_phy_sfp_avago;
1495 				break;
1496 			case IXGBE_SFF_VENDOR_OUI_INTEL:
1497 				hw->phy.type = ixgbe_phy_sfp_intel;
1498 				break;
1499 			default:
1500 				hw->phy.type = ixgbe_phy_sfp_unknown;
1501 				break;
1502 			}
1503 		}
1504 
1505 		/* Allow any DA cable vendor */
1506 		if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE |
1507 			IXGBE_SFF_DA_ACTIVE_CABLE)) {
1508 			if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE)
1509 				hw->phy.type = ixgbe_phy_sfp_passive_unknown;
1510 			else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE)
1511 				hw->phy.type = ixgbe_phy_sfp_active_unknown;
1512 			status = IXGBE_SUCCESS;
1513 			goto out;
1514 		}
1515 
1516 		/* Verify supported 1G SFP modules */
1517 		if (comp_codes_10g == 0 &&
1518 		    !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1519 		      hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1520 		      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1521 		      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1522 		      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1523 		      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1524 			hw->phy.type = ixgbe_phy_sfp_unsupported;
1525 			status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1526 			goto out;
1527 		}
1528 
1529 		/* Anything else 82598-based is supported */
1530 		if (hw->mac.type == ixgbe_mac_82598EB) {
1531 			status = IXGBE_SUCCESS;
1532 			goto out;
1533 		}
1534 
1535 		ixgbe_get_device_caps(hw, &enforce_sfp);
1536 		if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) &&
1537 		    !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1538 		      hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1539 		      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1540 		      hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1541 		      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 ||
1542 		      hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) {
1543 			/* Make sure we're a supported PHY type */
1544 			if (hw->phy.type == ixgbe_phy_sfp_intel) {
1545 				status = IXGBE_SUCCESS;
1546 			} else {
1547 				if (hw->allow_unsupported_sfp == TRUE) {
1548 					EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1549 					status = IXGBE_SUCCESS;
1550 				} else {
1551 					DEBUGOUT("SFP+ module not supported\n");
1552 					hw->phy.type =
1553 						ixgbe_phy_sfp_unsupported;
1554 					status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1555 				}
1556 			}
1557 		} else {
1558 			status = IXGBE_SUCCESS;
1559 		}
1560 	}
1561 
1562 out:
1563 	return status;
1564 
1565 err_read_i2c_eeprom:
1566 	hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1567 	if (hw->phy.type != ixgbe_phy_nl) {
1568 		hw->phy.id = 0;
1569 		hw->phy.type = ixgbe_phy_unknown;
1570 	}
1571 	return IXGBE_ERR_SFP_NOT_PRESENT;
1572 }
1573 
1574 /**
1575  *  ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type
1576  *  @hw: pointer to hardware structure
1577  *
1578  *  Determines physical layer capabilities of the current SFP.
1579  */
ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw * hw)1580 u64 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw)
1581 {
1582 	u64 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN;
1583 	u8 comp_codes_10g = 0;
1584 	u8 comp_codes_1g = 0;
1585 
1586 	DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic");
1587 
1588 	hw->phy.ops.identify_sfp(hw);
1589 	if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1590 		return physical_layer;
1591 
1592 	switch (hw->phy.type) {
1593 	case ixgbe_phy_sfp_passive_tyco:
1594 	case ixgbe_phy_sfp_passive_unknown:
1595 	case ixgbe_phy_qsfp_passive_unknown:
1596 		physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU;
1597 		break;
1598 	case ixgbe_phy_sfp_ftl_active:
1599 	case ixgbe_phy_sfp_active_unknown:
1600 	case ixgbe_phy_qsfp_active_unknown:
1601 		physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA;
1602 		break;
1603 	case ixgbe_phy_sfp_avago:
1604 	case ixgbe_phy_sfp_ftl:
1605 	case ixgbe_phy_sfp_intel:
1606 	case ixgbe_phy_sfp_unknown:
1607 		hw->phy.ops.read_i2c_eeprom(hw,
1608 		      IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g);
1609 		hw->phy.ops.read_i2c_eeprom(hw,
1610 		      IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g);
1611 		if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1612 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1613 		else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1614 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1615 		else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE)
1616 			physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T;
1617 		else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE)
1618 			physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX;
1619 		break;
1620 	case ixgbe_phy_qsfp_intel:
1621 	case ixgbe_phy_qsfp_unknown:
1622 		hw->phy.ops.read_i2c_eeprom(hw,
1623 		      IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g);
1624 		if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)
1625 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR;
1626 		else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)
1627 			physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR;
1628 		break;
1629 	default:
1630 		break;
1631 	}
1632 
1633 	return physical_layer;
1634 }
1635 
1636 /**
1637  *  ixgbe_identify_qsfp_module_generic - Identifies QSFP modules
1638  *  @hw: pointer to hardware structure
1639  *
1640  *  Searches for and identifies the QSFP module and assigns appropriate PHY type
1641  **/
ixgbe_identify_qsfp_module_generic(struct ixgbe_hw * hw)1642 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw)
1643 {
1644 	s32 status = IXGBE_ERR_PHY_ADDR_INVALID;
1645 	u32 vendor_oui = 0;
1646 	enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type;
1647 	u8 identifier = 0;
1648 	u8 comp_codes_1g = 0;
1649 	u8 comp_codes_10g = 0;
1650 	u8 oui_bytes[3] = {0, 0, 0};
1651 	u16 enforce_sfp = 0;
1652 	u8 connector = 0;
1653 	u8 cable_length = 0;
1654 	u8 device_tech = 0;
1655 	bool active_cable = FALSE;
1656 
1657 	DEBUGFUNC("ixgbe_identify_qsfp_module_generic");
1658 
1659 	if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) {
1660 		hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1661 		status = IXGBE_ERR_SFP_NOT_PRESENT;
1662 		goto out;
1663 	}
1664 
1665 	/* LAN ID is needed for I2C access */
1666 	hw->mac.ops.set_lan_id(hw);
1667 
1668 	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER,
1669 					     &identifier);
1670 
1671 	if (status != IXGBE_SUCCESS)
1672 		goto err_read_i2c_eeprom;
1673 
1674 	if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) {
1675 		hw->phy.type = ixgbe_phy_sfp_unsupported;
1676 		status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1677 		goto out;
1678 	}
1679 
1680 	hw->phy.id = identifier;
1681 
1682 	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP,
1683 					     &comp_codes_10g);
1684 
1685 	if (status != IXGBE_SUCCESS)
1686 		goto err_read_i2c_eeprom;
1687 
1688 	status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP,
1689 					     &comp_codes_1g);
1690 
1691 	if (status != IXGBE_SUCCESS)
1692 		goto err_read_i2c_eeprom;
1693 
1694 	if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) {
1695 		hw->phy.type = ixgbe_phy_qsfp_passive_unknown;
1696 		if (hw->bus.lan_id == 0)
1697 			hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0;
1698 		else
1699 			hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1;
1700 	} else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1701 				     IXGBE_SFF_10GBASELR_CAPABLE)) {
1702 		if (hw->bus.lan_id == 0)
1703 			hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0;
1704 		else
1705 			hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1;
1706 	} else {
1707 		if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE)
1708 			active_cable = TRUE;
1709 
1710 		if (!active_cable) {
1711 			/* check for active DA cables that pre-date
1712 			 * SFF-8436 v3.6 */
1713 			hw->phy.ops.read_i2c_eeprom(hw,
1714 					IXGBE_SFF_QSFP_CONNECTOR,
1715 					&connector);
1716 
1717 			hw->phy.ops.read_i2c_eeprom(hw,
1718 					IXGBE_SFF_QSFP_CABLE_LENGTH,
1719 					&cable_length);
1720 
1721 			hw->phy.ops.read_i2c_eeprom(hw,
1722 					IXGBE_SFF_QSFP_DEVICE_TECH,
1723 					&device_tech);
1724 
1725 			if ((connector ==
1726 				     IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) &&
1727 			    (cable_length > 0) &&
1728 			    ((device_tech >> 4) ==
1729 				     IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL))
1730 				active_cable = TRUE;
1731 		}
1732 
1733 		if (active_cable) {
1734 			hw->phy.type = ixgbe_phy_qsfp_active_unknown;
1735 			if (hw->bus.lan_id == 0)
1736 				hw->phy.sfp_type =
1737 						ixgbe_sfp_type_da_act_lmt_core0;
1738 			else
1739 				hw->phy.sfp_type =
1740 						ixgbe_sfp_type_da_act_lmt_core1;
1741 		} else {
1742 			/* unsupported module type */
1743 			hw->phy.type = ixgbe_phy_sfp_unsupported;
1744 			status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1745 			goto out;
1746 		}
1747 	}
1748 
1749 	if (hw->phy.sfp_type != stored_sfp_type)
1750 		hw->phy.sfp_setup_needed = TRUE;
1751 
1752 	/* Determine if the QSFP+ PHY is dual speed or not. */
1753 	hw->phy.multispeed_fiber = FALSE;
1754 	if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) &&
1755 	   (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) ||
1756 	   ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) &&
1757 	   (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE)))
1758 		hw->phy.multispeed_fiber = TRUE;
1759 
1760 	/* Determine PHY vendor for optical modules */
1761 	if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE |
1762 			      IXGBE_SFF_10GBASELR_CAPABLE))  {
1763 		status = hw->phy.ops.read_i2c_eeprom(hw,
1764 					    IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0,
1765 					    &oui_bytes[0]);
1766 
1767 		if (status != IXGBE_SUCCESS)
1768 			goto err_read_i2c_eeprom;
1769 
1770 		status = hw->phy.ops.read_i2c_eeprom(hw,
1771 					    IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1,
1772 					    &oui_bytes[1]);
1773 
1774 		if (status != IXGBE_SUCCESS)
1775 			goto err_read_i2c_eeprom;
1776 
1777 		status = hw->phy.ops.read_i2c_eeprom(hw,
1778 					    IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2,
1779 					    &oui_bytes[2]);
1780 
1781 		if (status != IXGBE_SUCCESS)
1782 			goto err_read_i2c_eeprom;
1783 
1784 		vendor_oui =
1785 		  ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) |
1786 		   (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) |
1787 		   (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT));
1788 
1789 		if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL)
1790 			hw->phy.type = ixgbe_phy_qsfp_intel;
1791 		else
1792 			hw->phy.type = ixgbe_phy_qsfp_unknown;
1793 
1794 		ixgbe_get_device_caps(hw, &enforce_sfp);
1795 		if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) {
1796 			/* Make sure we're a supported PHY type */
1797 			if (hw->phy.type == ixgbe_phy_qsfp_intel) {
1798 				status = IXGBE_SUCCESS;
1799 			} else {
1800 				if (hw->allow_unsupported_sfp == TRUE) {
1801 					EWARN(hw, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules.\n");
1802 					status = IXGBE_SUCCESS;
1803 				} else {
1804 					DEBUGOUT("QSFP module not supported\n");
1805 					hw->phy.type =
1806 						ixgbe_phy_sfp_unsupported;
1807 					status = IXGBE_ERR_SFP_NOT_SUPPORTED;
1808 				}
1809 			}
1810 		} else {
1811 			status = IXGBE_SUCCESS;
1812 		}
1813 	}
1814 
1815 out:
1816 	return status;
1817 
1818 err_read_i2c_eeprom:
1819 	hw->phy.sfp_type = ixgbe_sfp_type_not_present;
1820 	hw->phy.id = 0;
1821 	hw->phy.type = ixgbe_phy_unknown;
1822 
1823 	return IXGBE_ERR_SFP_NOT_PRESENT;
1824 }
1825 
1826 /**
1827  *  ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence
1828  *  @hw: pointer to hardware structure
1829  *  @list_offset: offset to the SFP ID list
1830  *  @data_offset: offset to the SFP data block
1831  *
1832  *  Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if
1833  *  so it returns the offsets to the phy init sequence block.
1834  **/
ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw * hw,u16 * list_offset,u16 * data_offset)1835 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
1836 					u16 *list_offset,
1837 					u16 *data_offset)
1838 {
1839 	u16 sfp_id;
1840 	u16 sfp_type = hw->phy.sfp_type;
1841 
1842 	DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets");
1843 
1844 	if (hw->phy.sfp_type == ixgbe_sfp_type_unknown)
1845 		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1846 
1847 	if (hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1848 		return IXGBE_ERR_SFP_NOT_PRESENT;
1849 
1850 	if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) &&
1851 	    (hw->phy.sfp_type == ixgbe_sfp_type_da_cu))
1852 		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1853 
1854 	/*
1855 	 * Limiting active cables and 1G Phys must be initialized as
1856 	 * SR modules
1857 	 */
1858 	if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 ||
1859 	    sfp_type == ixgbe_sfp_type_1g_lx_core0 ||
1860 	    sfp_type == ixgbe_sfp_type_1g_cu_core0 ||
1861 	    sfp_type == ixgbe_sfp_type_1g_sx_core0)
1862 		sfp_type = ixgbe_sfp_type_srlr_core0;
1863 	else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 ||
1864 		 sfp_type == ixgbe_sfp_type_1g_lx_core1 ||
1865 		 sfp_type == ixgbe_sfp_type_1g_cu_core1 ||
1866 		 sfp_type == ixgbe_sfp_type_1g_sx_core1)
1867 		sfp_type = ixgbe_sfp_type_srlr_core1;
1868 
1869 	/* Read offset to PHY init contents */
1870 	if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) {
1871 		ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1872 			      "eeprom read at offset %d failed",
1873 			      IXGBE_PHY_INIT_OFFSET_NL);
1874 		return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1875 	}
1876 
1877 	if ((!*list_offset) || (*list_offset == 0xFFFF))
1878 		return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT;
1879 
1880 	/* Shift offset to first ID word */
1881 	(*list_offset)++;
1882 
1883 	/*
1884 	 * Find the matching SFP ID in the EEPROM
1885 	 * and program the init sequence
1886 	 */
1887 	if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1888 		goto err_phy;
1889 
1890 	while (sfp_id != IXGBE_PHY_INIT_END_NL) {
1891 		if (sfp_id == sfp_type) {
1892 			(*list_offset)++;
1893 			if (hw->eeprom.ops.read(hw, *list_offset, data_offset))
1894 				goto err_phy;
1895 			if ((!*data_offset) || (*data_offset == 0xFFFF)) {
1896 				DEBUGOUT("SFP+ module not supported\n");
1897 				return IXGBE_ERR_SFP_NOT_SUPPORTED;
1898 			} else {
1899 				break;
1900 			}
1901 		} else {
1902 			(*list_offset) += 2;
1903 			if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id))
1904 				goto err_phy;
1905 		}
1906 	}
1907 
1908 	if (sfp_id == IXGBE_PHY_INIT_END_NL) {
1909 		DEBUGOUT("No matching SFP+ module found\n");
1910 		return IXGBE_ERR_SFP_NOT_SUPPORTED;
1911 	}
1912 
1913 	return IXGBE_SUCCESS;
1914 
1915 err_phy:
1916 	ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
1917 		      "eeprom read at offset %d failed", *list_offset);
1918 	return IXGBE_ERR_PHY;
1919 }
1920 
1921 /**
1922  *  ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface
1923  *  @hw: pointer to hardware structure
1924  *  @byte_offset: EEPROM byte offset to read
1925  *  @eeprom_data: value read
1926  *
1927  *  Performs byte read operation to SFP module's EEPROM over I2C interface.
1928  **/
ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 * eeprom_data)1929 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1930 				  u8 *eeprom_data)
1931 {
1932 	DEBUGFUNC("ixgbe_read_i2c_eeprom_generic");
1933 
1934 	return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1935 					 IXGBE_I2C_EEPROM_DEV_ADDR,
1936 					 eeprom_data);
1937 }
1938 
1939 /**
1940  *  ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface
1941  *  @hw: pointer to hardware structure
1942  *  @byte_offset: byte offset at address 0xA2
1943  *  @sff8472_data: value read
1944  *
1945  *  Performs byte read operation to SFP module's SFF-8472 data over I2C
1946  **/
ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 * sff8472_data)1947 static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset,
1948 					  u8 *sff8472_data)
1949 {
1950 	return hw->phy.ops.read_i2c_byte(hw, byte_offset,
1951 					 IXGBE_I2C_EEPROM_DEV_ADDR2,
1952 					 sff8472_data);
1953 }
1954 
1955 /**
1956  *  ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface
1957  *  @hw: pointer to hardware structure
1958  *  @byte_offset: EEPROM byte offset to write
1959  *  @eeprom_data: value to write
1960  *
1961  *  Performs byte write operation to SFP module's EEPROM over I2C interface.
1962  **/
ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 eeprom_data)1963 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
1964 				   u8 eeprom_data)
1965 {
1966 	DEBUGFUNC("ixgbe_write_i2c_eeprom_generic");
1967 
1968 	return hw->phy.ops.write_i2c_byte(hw, byte_offset,
1969 					  IXGBE_I2C_EEPROM_DEV_ADDR,
1970 					  eeprom_data);
1971 }
1972 
1973 /**
1974  * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected
1975  * @hw: pointer to hardware structure
1976  * @offset: eeprom offset to be read
1977  * @addr: I2C address to be read
1978  */
ixgbe_is_sfp_probe(struct ixgbe_hw * hw,u8 offset,u8 addr)1979 static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr)
1980 {
1981 	if (addr == IXGBE_I2C_EEPROM_DEV_ADDR &&
1982 	    offset == IXGBE_SFF_IDENTIFIER &&
1983 	    hw->phy.sfp_type == ixgbe_sfp_type_not_present)
1984 		return TRUE;
1985 	return FALSE;
1986 }
1987 
1988 /**
1989  *  ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C
1990  *  @hw: pointer to hardware structure
1991  *  @byte_offset: byte offset to read
1992  *  @dev_addr: address to read from
1993  *  @data: value read
1994  *  @lock: TRUE if to take and release semaphore
1995  *
1996  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
1997  *  a specified device address.
1998  **/
ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data,bool lock)1999 static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2000 					   u8 dev_addr, u8 *data, bool lock)
2001 {
2002 	s32 status;
2003 	u32 max_retry = 10;
2004 	u32 retry = 0;
2005 	u32 swfw_mask = hw->phy.phy_semaphore_mask;
2006 	bool nack = 1;
2007 	*data = 0;
2008 
2009 	DEBUGFUNC("ixgbe_read_i2c_byte_generic");
2010 
2011 	if (hw->mac.type >= ixgbe_mac_X550)
2012 		max_retry = 3;
2013 	if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr))
2014 		max_retry = IXGBE_SFP_DETECT_RETRIES;
2015 
2016 	do {
2017 		if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask))
2018 			return IXGBE_ERR_SWFW_SYNC;
2019 
2020 		ixgbe_i2c_start(hw);
2021 
2022 		/* Device Address and write indication */
2023 		status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2024 		if (status != IXGBE_SUCCESS)
2025 			goto fail;
2026 
2027 		status = ixgbe_get_i2c_ack(hw);
2028 		if (status != IXGBE_SUCCESS)
2029 			goto fail;
2030 
2031 		status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2032 		if (status != IXGBE_SUCCESS)
2033 			goto fail;
2034 
2035 		status = ixgbe_get_i2c_ack(hw);
2036 		if (status != IXGBE_SUCCESS)
2037 			goto fail;
2038 
2039 		ixgbe_i2c_start(hw);
2040 
2041 		/* Device Address and read indication */
2042 		status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1));
2043 		if (status != IXGBE_SUCCESS)
2044 			goto fail;
2045 
2046 		status = ixgbe_get_i2c_ack(hw);
2047 		if (status != IXGBE_SUCCESS)
2048 			goto fail;
2049 
2050 		status = ixgbe_clock_in_i2c_byte(hw, data);
2051 		if (status != IXGBE_SUCCESS)
2052 			goto fail;
2053 
2054 		status = ixgbe_clock_out_i2c_bit(hw, nack);
2055 		if (status != IXGBE_SUCCESS)
2056 			goto fail;
2057 
2058 		ixgbe_i2c_stop(hw);
2059 		if (lock)
2060 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2061 		return IXGBE_SUCCESS;
2062 
2063 fail:
2064 		ixgbe_i2c_bus_clear(hw);
2065 		if (lock) {
2066 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2067 			msec_delay(100);
2068 		}
2069 		retry++;
2070 		if (retry < max_retry)
2071 			DEBUGOUT("I2C byte read error - Retrying.\n");
2072 		else
2073 			DEBUGOUT("I2C byte read error.\n");
2074 
2075 	} while (retry < max_retry);
2076 
2077 	return status;
2078 }
2079 
2080 /**
2081  *  ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C
2082  *  @hw: pointer to hardware structure
2083  *  @byte_offset: byte offset to read
2084  *  @dev_addr: address to read from
2085  *  @data: value read
2086  *
2087  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2088  *  a specified device address.
2089  **/
ixgbe_read_i2c_byte_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)2090 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2091 				u8 dev_addr, u8 *data)
2092 {
2093 	return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2094 					       data, TRUE);
2095 }
2096 
2097 /**
2098  *  ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C
2099  *  @hw: pointer to hardware structure
2100  *  @byte_offset: byte offset to read
2101  *  @dev_addr: address to read from
2102  *  @data: value read
2103  *
2104  *  Performs byte read operation to SFP module's EEPROM over I2C interface at
2105  *  a specified device address.
2106  **/
ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 * data)2107 s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2108 					 u8 dev_addr, u8 *data)
2109 {
2110 	return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2111 					       data, FALSE);
2112 }
2113 
2114 /**
2115  *  ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C
2116  *  @hw: pointer to hardware structure
2117  *  @byte_offset: byte offset to write
2118  *  @dev_addr: address to write to
2119  *  @data: value to write
2120  *  @lock: TRUE if to take and release semaphore
2121  *
2122  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2123  *  a specified device address.
2124  **/
ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data,bool lock)2125 static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset,
2126 					    u8 dev_addr, u8 data, bool lock)
2127 {
2128 	s32 status;
2129 	u32 max_retry = 1;
2130 	u32 retry = 0;
2131 	u32 swfw_mask = hw->phy.phy_semaphore_mask;
2132 
2133 	DEBUGFUNC("ixgbe_write_i2c_byte_generic");
2134 
2135 	if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) !=
2136 	    IXGBE_SUCCESS)
2137 		return IXGBE_ERR_SWFW_SYNC;
2138 
2139 	do {
2140 		ixgbe_i2c_start(hw);
2141 
2142 		status = ixgbe_clock_out_i2c_byte(hw, dev_addr);
2143 		if (status != IXGBE_SUCCESS)
2144 			goto fail;
2145 
2146 		status = ixgbe_get_i2c_ack(hw);
2147 		if (status != IXGBE_SUCCESS)
2148 			goto fail;
2149 
2150 		status = ixgbe_clock_out_i2c_byte(hw, byte_offset);
2151 		if (status != IXGBE_SUCCESS)
2152 			goto fail;
2153 
2154 		status = ixgbe_get_i2c_ack(hw);
2155 		if (status != IXGBE_SUCCESS)
2156 			goto fail;
2157 
2158 		status = ixgbe_clock_out_i2c_byte(hw, data);
2159 		if (status != IXGBE_SUCCESS)
2160 			goto fail;
2161 
2162 		status = ixgbe_get_i2c_ack(hw);
2163 		if (status != IXGBE_SUCCESS)
2164 			goto fail;
2165 
2166 		ixgbe_i2c_stop(hw);
2167 		if (lock)
2168 			hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2169 		return IXGBE_SUCCESS;
2170 
2171 fail:
2172 		ixgbe_i2c_bus_clear(hw);
2173 		retry++;
2174 		if (retry < max_retry)
2175 			DEBUGOUT("I2C byte write error - Retrying.\n");
2176 		else
2177 			DEBUGOUT("I2C byte write error.\n");
2178 	} while (retry < max_retry);
2179 
2180 	if (lock)
2181 		hw->mac.ops.release_swfw_sync(hw, swfw_mask);
2182 
2183 	return status;
2184 }
2185 
2186 /**
2187  *  ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C
2188  *  @hw: pointer to hardware structure
2189  *  @byte_offset: byte offset to write
2190  *  @dev_addr: address to write to
2191  *  @data: value to write
2192  *
2193  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2194  *  a specified device address.
2195  **/
ixgbe_write_i2c_byte_generic(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)2196 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
2197 				 u8 dev_addr, u8 data)
2198 {
2199 	return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2200 						data, TRUE);
2201 }
2202 
2203 /**
2204  *  ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C
2205  *  @hw: pointer to hardware structure
2206  *  @byte_offset: byte offset to write
2207  *  @dev_addr: address to write to
2208  *  @data: value to write
2209  *
2210  *  Performs byte write operation to SFP module's EEPROM over I2C interface at
2211  *  a specified device address.
2212  **/
ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw * hw,u8 byte_offset,u8 dev_addr,u8 data)2213 s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset,
2214 					  u8 dev_addr, u8 data)
2215 {
2216 	return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr,
2217 						data, FALSE);
2218 }
2219 
2220 /**
2221  *  ixgbe_i2c_start - Sets I2C start condition
2222  *  @hw: pointer to hardware structure
2223  *
2224  *  Sets I2C start condition (High -> Low on SDA while SCL is High)
2225  *  Set bit-bang mode on X550 hardware.
2226  **/
ixgbe_i2c_start(struct ixgbe_hw * hw)2227 static void ixgbe_i2c_start(struct ixgbe_hw *hw)
2228 {
2229 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2230 
2231 	DEBUGFUNC("ixgbe_i2c_start");
2232 
2233 	i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw);
2234 
2235 	/* Start condition must begin with data and clock high */
2236 	ixgbe_set_i2c_data(hw, &i2cctl, 1);
2237 	ixgbe_raise_i2c_clk(hw, &i2cctl);
2238 
2239 	/* Setup time for start condition (4.7us) */
2240 	usec_delay(IXGBE_I2C_T_SU_STA);
2241 
2242 	ixgbe_set_i2c_data(hw, &i2cctl, 0);
2243 
2244 	/* Hold time for start condition (4us) */
2245 	usec_delay(IXGBE_I2C_T_HD_STA);
2246 
2247 	ixgbe_lower_i2c_clk(hw, &i2cctl);
2248 
2249 	/* Minimum low period of clock is 4.7 us */
2250 	usec_delay(IXGBE_I2C_T_LOW);
2251 
2252 }
2253 
2254 /**
2255  *  ixgbe_i2c_stop - Sets I2C stop condition
2256  *  @hw: pointer to hardware structure
2257  *
2258  *  Sets I2C stop condition (Low -> High on SDA while SCL is High)
2259  *  Disables bit-bang mode and negates data output enable on X550
2260  *  hardware.
2261  **/
ixgbe_i2c_stop(struct ixgbe_hw * hw)2262 static void ixgbe_i2c_stop(struct ixgbe_hw *hw)
2263 {
2264 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2265 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2266 	u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2267 	u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw);
2268 
2269 	DEBUGFUNC("ixgbe_i2c_stop");
2270 
2271 	/* Stop condition must begin with data low and clock high */
2272 	ixgbe_set_i2c_data(hw, &i2cctl, 0);
2273 	ixgbe_raise_i2c_clk(hw, &i2cctl);
2274 
2275 	/* Setup time for stop condition (4us) */
2276 	usec_delay(IXGBE_I2C_T_SU_STO);
2277 
2278 	ixgbe_set_i2c_data(hw, &i2cctl, 1);
2279 
2280 	/* bus free time between stop and start (4.7us)*/
2281 	usec_delay(IXGBE_I2C_T_BUF);
2282 
2283 	if (bb_en_bit || data_oe_bit || clk_oe_bit) {
2284 		i2cctl &= ~bb_en_bit;
2285 		i2cctl |= data_oe_bit | clk_oe_bit;
2286 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2287 		IXGBE_WRITE_FLUSH(hw);
2288 	}
2289 }
2290 
2291 /**
2292  *  ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C
2293  *  @hw: pointer to hardware structure
2294  *  @data: data byte to clock in
2295  *
2296  *  Clocks in one byte data via I2C data/clock
2297  **/
ixgbe_clock_in_i2c_byte(struct ixgbe_hw * hw,u8 * data)2298 static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data)
2299 {
2300 	s32 i;
2301 	bool bit = 0;
2302 
2303 	DEBUGFUNC("ixgbe_clock_in_i2c_byte");
2304 
2305 	*data = 0;
2306 	for (i = 7; i >= 0; i--) {
2307 		ixgbe_clock_in_i2c_bit(hw, &bit);
2308 		*data |= bit << i;
2309 	}
2310 
2311 	return IXGBE_SUCCESS;
2312 }
2313 
2314 /**
2315  *  ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C
2316  *  @hw: pointer to hardware structure
2317  *  @data: data byte clocked out
2318  *
2319  *  Clocks out one byte data via I2C data/clock
2320  **/
ixgbe_clock_out_i2c_byte(struct ixgbe_hw * hw,u8 data)2321 static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data)
2322 {
2323 	s32 status = IXGBE_SUCCESS;
2324 	s32 i;
2325 	u32 i2cctl;
2326 	bool bit;
2327 
2328 	DEBUGFUNC("ixgbe_clock_out_i2c_byte");
2329 
2330 	for (i = 7; i >= 0; i--) {
2331 		bit = (data >> i) & 0x1;
2332 		status = ixgbe_clock_out_i2c_bit(hw, bit);
2333 
2334 		if (status != IXGBE_SUCCESS)
2335 			break;
2336 	}
2337 
2338 	/* Release SDA line (set high) */
2339 	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2340 	i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2341 	i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2342 	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2343 	IXGBE_WRITE_FLUSH(hw);
2344 
2345 	return status;
2346 }
2347 
2348 /**
2349  *  ixgbe_get_i2c_ack - Polls for I2C ACK
2350  *  @hw: pointer to hardware structure
2351  *
2352  *  Clocks in/out one bit via I2C data/clock
2353  **/
ixgbe_get_i2c_ack(struct ixgbe_hw * hw)2354 static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw)
2355 {
2356 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2357 	s32 status = IXGBE_SUCCESS;
2358 	u32 i = 0;
2359 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2360 	u32 timeout = 10;
2361 	bool ack = 1;
2362 
2363 	DEBUGFUNC("ixgbe_get_i2c_ack");
2364 
2365 	if (data_oe_bit) {
2366 		i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2367 		i2cctl |= data_oe_bit;
2368 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2369 		IXGBE_WRITE_FLUSH(hw);
2370 	}
2371 	ixgbe_raise_i2c_clk(hw, &i2cctl);
2372 
2373 	/* Minimum high period of clock is 4us */
2374 	usec_delay(IXGBE_I2C_T_HIGH);
2375 
2376 	/* Poll for ACK.  Note that ACK in I2C spec is
2377 	 * transition from 1 to 0 */
2378 	for (i = 0; i < timeout; i++) {
2379 		i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2380 		ack = ixgbe_get_i2c_data(hw, &i2cctl);
2381 
2382 		usec_delay(1);
2383 		if (!ack)
2384 			break;
2385 	}
2386 
2387 	if (ack) {
2388 		DEBUGOUT("I2C ack was not received.\n");
2389 		status = IXGBE_ERR_I2C;
2390 	}
2391 
2392 	ixgbe_lower_i2c_clk(hw, &i2cctl);
2393 
2394 	/* Minimum low period of clock is 4.7 us */
2395 	usec_delay(IXGBE_I2C_T_LOW);
2396 
2397 	return status;
2398 }
2399 
2400 /**
2401  *  ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
2402  *  @hw: pointer to hardware structure
2403  *  @data: read data value
2404  *
2405  *  Clocks in one bit via I2C data/clock
2406  **/
ixgbe_clock_in_i2c_bit(struct ixgbe_hw * hw,bool * data)2407 static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data)
2408 {
2409 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2410 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2411 
2412 	DEBUGFUNC("ixgbe_clock_in_i2c_bit");
2413 
2414 	if (data_oe_bit) {
2415 		i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2416 		i2cctl |= data_oe_bit;
2417 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl);
2418 		IXGBE_WRITE_FLUSH(hw);
2419 	}
2420 	ixgbe_raise_i2c_clk(hw, &i2cctl);
2421 
2422 	/* Minimum high period of clock is 4us */
2423 	usec_delay(IXGBE_I2C_T_HIGH);
2424 
2425 	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2426 	*data = ixgbe_get_i2c_data(hw, &i2cctl);
2427 
2428 	ixgbe_lower_i2c_clk(hw, &i2cctl);
2429 
2430 	/* Minimum low period of clock is 4.7 us */
2431 	usec_delay(IXGBE_I2C_T_LOW);
2432 
2433 	return IXGBE_SUCCESS;
2434 }
2435 
2436 /**
2437  *  ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
2438  *  @hw: pointer to hardware structure
2439  *  @data: data value to write
2440  *
2441  *  Clocks out one bit via I2C data/clock
2442  **/
ixgbe_clock_out_i2c_bit(struct ixgbe_hw * hw,bool data)2443 static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data)
2444 {
2445 	s32 status;
2446 	u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2447 
2448 	DEBUGFUNC("ixgbe_clock_out_i2c_bit");
2449 
2450 	status = ixgbe_set_i2c_data(hw, &i2cctl, data);
2451 	if (status == IXGBE_SUCCESS) {
2452 		ixgbe_raise_i2c_clk(hw, &i2cctl);
2453 
2454 		/* Minimum high period of clock is 4us */
2455 		usec_delay(IXGBE_I2C_T_HIGH);
2456 
2457 		ixgbe_lower_i2c_clk(hw, &i2cctl);
2458 
2459 		/* Minimum low period of clock is 4.7 us.
2460 		 * This also takes care of the data hold time.
2461 		 */
2462 		usec_delay(IXGBE_I2C_T_LOW);
2463 	} else {
2464 		status = IXGBE_ERR_I2C;
2465 		ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2466 			     "I2C data was not set to %X\n", data);
2467 	}
2468 
2469 	return status;
2470 }
2471 
2472 /**
2473  *  ixgbe_raise_i2c_clk - Raises the I2C SCL clock
2474  *  @hw: pointer to hardware structure
2475  *  @i2cctl: Current value of I2CCTL register
2476  *
2477  *  Raises the I2C clock line '0'->'1'
2478  *  Negates the I2C clock output enable on X550 hardware.
2479  **/
ixgbe_raise_i2c_clk(struct ixgbe_hw * hw,u32 * i2cctl)2480 static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2481 {
2482 	u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2483 	u32 i = 0;
2484 	u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT;
2485 	u32 i2cctl_r = 0;
2486 
2487 	DEBUGFUNC("ixgbe_raise_i2c_clk");
2488 
2489 	if (clk_oe_bit) {
2490 		*i2cctl |= clk_oe_bit;
2491 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2492 	}
2493 
2494 	for (i = 0; i < timeout; i++) {
2495 		*i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw);
2496 
2497 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2498 		IXGBE_WRITE_FLUSH(hw);
2499 		/* SCL rise time (1000ns) */
2500 		usec_delay(IXGBE_I2C_T_RISE);
2501 
2502 		i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2503 		if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw))
2504 			break;
2505 	}
2506 }
2507 
2508 /**
2509  *  ixgbe_lower_i2c_clk - Lowers the I2C SCL clock
2510  *  @hw: pointer to hardware structure
2511  *  @i2cctl: Current value of I2CCTL register
2512  *
2513  *  Lowers the I2C clock line '1'->'0'
2514  *  Asserts the I2C clock output enable on X550 hardware.
2515  **/
ixgbe_lower_i2c_clk(struct ixgbe_hw * hw,u32 * i2cctl)2516 static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl)
2517 {
2518 	DEBUGFUNC("ixgbe_lower_i2c_clk");
2519 
2520 	*i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw));
2521 	*i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw);
2522 
2523 	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2524 	IXGBE_WRITE_FLUSH(hw);
2525 
2526 	/* SCL fall time (300ns) */
2527 	usec_delay(IXGBE_I2C_T_FALL);
2528 }
2529 
2530 /**
2531  *  ixgbe_set_i2c_data - Sets the I2C data bit
2532  *  @hw: pointer to hardware structure
2533  *  @i2cctl: Current value of I2CCTL register
2534  *  @data: I2C data value (0 or 1) to set
2535  *
2536  *  Sets the I2C data bit
2537  *  Asserts the I2C data output enable on X550 hardware.
2538  **/
ixgbe_set_i2c_data(struct ixgbe_hw * hw,u32 * i2cctl,bool data)2539 static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data)
2540 {
2541 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2542 	s32 status = IXGBE_SUCCESS;
2543 
2544 	DEBUGFUNC("ixgbe_set_i2c_data");
2545 
2546 	if (data)
2547 		*i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw);
2548 	else
2549 		*i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw));
2550 	*i2cctl &= ~data_oe_bit;
2551 
2552 	IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2553 	IXGBE_WRITE_FLUSH(hw);
2554 
2555 	/* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
2556 	usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA);
2557 
2558 	if (!data)	/* Can't verify data in this case */
2559 		return IXGBE_SUCCESS;
2560 	if (data_oe_bit) {
2561 		*i2cctl |= data_oe_bit;
2562 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2563 		IXGBE_WRITE_FLUSH(hw);
2564 	}
2565 
2566 	/* Verify data was set correctly */
2567 	*i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2568 	if (data != ixgbe_get_i2c_data(hw, i2cctl)) {
2569 		status = IXGBE_ERR_I2C;
2570 		ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE,
2571 			     "Error - I2C data was not set to %X.\n",
2572 			     data);
2573 	}
2574 
2575 	return status;
2576 }
2577 
2578 /**
2579  *  ixgbe_get_i2c_data - Reads the I2C SDA data bit
2580  *  @hw: pointer to hardware structure
2581  *  @i2cctl: Current value of I2CCTL register
2582  *
2583  *  Returns the I2C data bit value
2584  *  Negates the I2C data output enable on X550 hardware.
2585  **/
ixgbe_get_i2c_data(struct ixgbe_hw * hw,u32 * i2cctl)2586 static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl)
2587 {
2588 	u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw);
2589 	bool data;
2590 	UNREFERENCED_1PARAMETER(hw);
2591 
2592 	DEBUGFUNC("ixgbe_get_i2c_data");
2593 
2594 	if (data_oe_bit) {
2595 		*i2cctl |= data_oe_bit;
2596 		IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl);
2597 		IXGBE_WRITE_FLUSH(hw);
2598 		usec_delay(IXGBE_I2C_T_FALL);
2599 	}
2600 
2601 	if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw))
2602 		data = 1;
2603 	else
2604 		data = 0;
2605 
2606 	return data;
2607 }
2608 
2609 /**
2610  *  ixgbe_i2c_bus_clear - Clears the I2C bus
2611  *  @hw: pointer to hardware structure
2612  *
2613  *  Clears the I2C bus by sending nine clock pulses.
2614  *  Used when data line is stuck low.
2615  **/
ixgbe_i2c_bus_clear(struct ixgbe_hw * hw)2616 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw)
2617 {
2618 	u32 i2cctl;
2619 	u32 i;
2620 
2621 	DEBUGFUNC("ixgbe_i2c_bus_clear");
2622 
2623 	ixgbe_i2c_start(hw);
2624 	i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw));
2625 
2626 	ixgbe_set_i2c_data(hw, &i2cctl, 1);
2627 
2628 	for (i = 0; i < 9; i++) {
2629 		ixgbe_raise_i2c_clk(hw, &i2cctl);
2630 
2631 		/* Min high period of clock is 4us */
2632 		usec_delay(IXGBE_I2C_T_HIGH);
2633 
2634 		ixgbe_lower_i2c_clk(hw, &i2cctl);
2635 
2636 		/* Min low period of clock is 4.7us*/
2637 		usec_delay(IXGBE_I2C_T_LOW);
2638 	}
2639 
2640 	ixgbe_i2c_start(hw);
2641 
2642 	/* Put the i2c bus back to default state */
2643 	ixgbe_i2c_stop(hw);
2644 }
2645 
2646 /**
2647  *  ixgbe_tn_check_overtemp - Checks if an overtemp occurred.
2648  *  @hw: pointer to hardware structure
2649  *
2650  *  Checks if the LASI temp alarm status was triggered due to overtemp
2651  **/
ixgbe_tn_check_overtemp(struct ixgbe_hw * hw)2652 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw)
2653 {
2654 	s32 status = IXGBE_SUCCESS;
2655 	u16 phy_data = 0;
2656 
2657 	DEBUGFUNC("ixgbe_tn_check_overtemp");
2658 
2659 	if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM)
2660 		goto out;
2661 
2662 	/* Check that the LASI temp alarm status was triggered */
2663 	hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG,
2664 			     IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data);
2665 
2666 	if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM))
2667 		goto out;
2668 
2669 	status = IXGBE_ERR_OVERTEMP;
2670 	ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature");
2671 out:
2672 	return status;
2673 }
2674 
2675 /**
2676  * ixgbe_set_copper_phy_power - Control power for copper phy
2677  * @hw: pointer to hardware structure
2678  * @on: TRUE for on, FALSE for off
2679  */
ixgbe_set_copper_phy_power(struct ixgbe_hw * hw,bool on)2680 s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on)
2681 {
2682 	u32 status;
2683 	u16 reg;
2684 
2685 	if (!on && ixgbe_mng_present(hw))
2686 		return 0;
2687 
2688 	status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2689 				      IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2690 				      &reg);
2691 	if (status)
2692 		return status;
2693 
2694 	if (on) {
2695 		reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2696 	} else {
2697 		if (ixgbe_check_reset_blocked(hw))
2698 			return 0;
2699 		reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE;
2700 	}
2701 
2702 	status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL,
2703 				       IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE,
2704 				       reg);
2705 	return status;
2706 }
2707