1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_MAC_NXGE_MAC_HW_H
27 #define	_SYS_MAC_NXGE_MAC_HW_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 #include <nxge_defs.h>
34 
35 /* -------------------------- From May's template --------------------------- */
36 
37 #define	NXGE_1GETHERMIN			255
38 #define	NXGE_ETHERMIN			97
39 #define	NXGE_MAX_HEADER			250
40 
41 /* Hardware reset */
42 typedef enum  {
43 	NXGE_TX_DISABLE,			/* Disable Tx side */
44 	NXGE_RX_DISABLE,			/* Disable Rx side */
45 	NXGE_CHIP_RESET				/* Full chip reset */
46 } nxge_reset_t;
47 
48 #define	NXGE_DELAY_AFTER_TXRX		10000	/* 10ms after idling rx/tx */
49 #define	NXGE_DELAY_AFTER_RESET		1000	/* 1ms after the reset */
50 #define	NXGE_DELAY_AFTER_EE_RESET	10000	/* 10ms after EEPROM reset */
51 #define	NXGE_DELAY_AFTER_LINK_RESET	13	/* 13 Us after link reset */
52 #define	NXGE_LINK_RESETS		8	/* Max PHY resets to wait for */
53 						/* linkup */
54 
55 #define	FILTER_M_CTL 			0xDCEF1
56 #define	HASH_BITS			8
57 #define	NMCFILTER_BITS			(1 << HASH_BITS)
58 #define	HASH_REG_WIDTH			16
59 #define	BROADCAST_HASH_WORD		0x0f
60 #define	BROADCAST_HASH_BIT		0x8000
61 #define	NMCFILTER_REGS			NMCFILTER_BITS / HASH_REG_WIDTH
62 					/* Number of multicast filter regs */
63 
64 /* -------------------------------------------------------------------------- */
65 
66 #define	XMAC_PORT_0			0
67 #define	XMAC_PORT_1			1
68 #define	BMAC_PORT_0			2
69 #define	BMAC_PORT_1			3
70 
71 #define	MAC_RESET_WAIT			10	/* usecs */
72 
73 #define	MAC_ADDR_REG_MASK		0xFFFF
74 
75 /*
76  * Neptune port PHY type and Speed encoding.
77  *
78  * Per port, 4 bits are reserved for port speed (1G/10G) and 4 bits
79  * are reserved for port PHY type (Copper/Fibre). Bits 0 thru 3 are for port0
80  * speed, bits 4 thru 7 are for port1 speed, bits 8 thru 11 are for port2 speed
81  * and bits 12 thru 15 are for port3 speed. Thus, the first 16 bits hold the
82  * speed encoding for the 4 ports. The next 16 bits (16 thru 31) hold the phy
83  * type encoding for the ports 0 thru 3.
84  *
85  *  p3phy  p2phy  p1phy  p0phy  p3spd p2spd  p1spd p0spd
86  *    |      |      |      |      |     |      |     |
87  *   ---    ---    ---    ---    ---   ---    ---   ---
88  *  /   \  /   \  /   \  /   \  /   \ /   \  /   \ /   \
89  * 31..28 27..24 23..20 19..16 15..12 11.. 8 7.. 4 3.. 0
90  */
91 
92 #define	NXGE_PORT_SPD_NONE	0x0
93 #define	NXGE_PORT_SPD_1G	0x1
94 #define	NXGE_PORT_SPD_10G	0x2
95 #define	NXGE_PORT_SPD_RSVD	0x7
96 
97 #define	NXGE_PHY_NONE		0x0
98 #define	NXGE_PHY_COPPER		0x1
99 #define	NXGE_PHY_FIBRE		0x2
100 #define	NXGE_PHY_SERDES		0x3
101 #define	NXGE_PHY_RGMII_FIBER	0x4
102 #define	NXGE_PHY_TN1010		0x5
103 #define	NXGE_PHY_RSVD		0x7
104 
105 #define	NXGE_PORT_SPD_SHIFT	0
106 #define	NXGE_PORT_SPD_MASK	0x0f
107 
108 #define	NXGE_PHY_SHIFT		16
109 #define	NXGE_PHY_MASK		0x0f0000
110 
111 /*
112  * "xgc" as a possible value for the device property "phy-type"
113  * was intended for the portmode == PORT_10G_COPPER case. But
114  * the first 10G copper network I/O device available is the
115  * TN1010 based copper XAUI card and we use PORT_10G_TN1010 or
116  * PORT_1G_TN1010 as the portmode, so PORT_10G_COPPER is never
117  * used as portmode. The driver code related to PORT_10G_COPPER
118  * is kept in the driver as a place holder for possble future
119  * 10G copper devices.
120  */
121 #define	NXGE_PORT_10G_COPPER	(NXGE_PORT_SPD_10G |	\
122 	(NXGE_PHY_COPPER << NXGE_PHY_SHIFT))
123 
124 #define	NXGE_PORT_1G_COPPER	(NXGE_PORT_SPD_1G |	\
125 	(NXGE_PHY_COPPER << NXGE_PHY_SHIFT))
126 #define	NXGE_PORT_1G_FIBRE	(NXGE_PORT_SPD_1G |	\
127 	(NXGE_PHY_FIBRE << NXGE_PHY_SHIFT))
128 #define	NXGE_PORT_10G_FIBRE	(NXGE_PORT_SPD_10G |	\
129 	(NXGE_PHY_FIBRE << NXGE_PHY_SHIFT))
130 #define	NXGE_PORT_1G_SERDES	(NXGE_PORT_SPD_1G |	\
131 	(NXGE_PHY_SERDES << NXGE_PHY_SHIFT))
132 #define	NXGE_PORT_10G_SERDES	(NXGE_PORT_SPD_10G |	\
133 	(NXGE_PHY_SERDES << NXGE_PHY_SHIFT))
134 #define	NXGE_PORT_1G_RGMII_FIBER	(NXGE_PORT_SPD_1G |	\
135 	(NXGE_PHY_RGMII_FIBER << NXGE_PHY_SHIFT))
136 
137 /* The speed of TN1010 will be determined by each nxge instance */
138 #define	NXGE_PORT_TN1010	(NXGE_PORT_SPD_NONE |	\
139 	(NXGE_PHY_TN1010 << NXGE_PHY_SHIFT))
140 
141 #define	NXGE_PORT_NONE		(NXGE_PORT_SPD_NONE |	\
142 	(NXGE_PHY_NONE << NXGE_PHY_SHIFT))
143 #define	NXGE_PORT_RSVD		(NXGE_PORT_SPD_RSVD |	\
144 	(NXGE_PHY_RSVD << NXGE_PHY_SHIFT))
145 
146 #define	NXGE_PORT_TYPE_MASK	(NXGE_PORT_SPD_MASK | NXGE_PHY_MASK)
147 
148 /* number of bits used for phy/spd encoding per port */
149 #define	NXGE_PORT_TYPE_SHIFT	4
150 
151 /* Network Modes */
152 
153 typedef enum nxge_network_mode {
154 	NET_2_10GE_FIBER = 1,
155 	NET_2_10GE_COPPER,
156 	NET_1_10GE_FIBER_3_1GE_COPPER,
157 	NET_1_10GE_COPPER_3_1GE_COPPER,
158 	NET_1_10GE_FIBER_3_1GE_FIBER,
159 	NET_1_10GE_COPPER_3_1GE_FIBER,
160 	NET_2_1GE_FIBER_2_1GE_COPPER,
161 	NET_QGE_FIBER,
162 	NET_QGE_COPPER
163 } nxge_network_mode_t;
164 
165 typedef	enum nxge_port {
166 	PORT_TYPE_XMAC = 1,
167 	PORT_TYPE_BMAC,
168 	PORT_TYPE_LOGICAL
169 } nxge_port_t;
170 
171 typedef	enum nxge_port_mode {
172 	PORT_1G_COPPER = 1,
173 	PORT_1G_FIBER,
174 	PORT_10G_COPPER,
175 	PORT_10G_FIBER,
176 	PORT_10G_SERDES,	/* Port0 or 1 of Alonso or Monza */
177 	PORT_1G_SERDES,		/* Port0 or 1 of Alonso or Monza */
178 	PORT_1G_RGMII_FIBER,	/* Port2 or 3 of Alonso or ARTM  */
179 	PORT_HSP_MODE,
180 	PORT_LOGICAL,
181 	PORT_1G_TN1010,		/* Teranetics PHY in 1G mode */
182 	PORT_10G_TN1010		/* Teranetics PHY in 10G mode */
183 } nxge_port_mode_t;
184 
185 typedef	enum nxge_linkchk_mode {
186 	LINKCHK_INTR = 1,
187 	LINKCHK_TIMER
188 } nxge_linkchk_mode_t;
189 
190 typedef enum {
191 	LINK_INTR_STOP,
192 	LINK_INTR_START
193 } link_intr_enable_t, *link_intr_enable_pt;
194 
195 typedef	enum {
196 	LINK_MONITOR_STOP,
197 	LINK_MONITOR_START,
198 	LINK_MONITOR_STOPPING
199 } link_mon_enable_t, *link_mon_enable_pt;
200 
201 typedef enum {
202 	NO_XCVR,
203 	INT_MII_XCVR,
204 	EXT_MII_XCVR,
205 	PCS_XCVR,
206 	XPCS_XCVR,
207 	HSP_XCVR,
208 	LOGICAL_XCVR
209 } xcvr_inuse_t;
210 
211 /* macros for port offset calculations */
212 
213 #define	PORT_1_OFFSET			0x6000
214 #define	PORT_GT_1_OFFSET		0x4000
215 
216 /* XMAC address macros */
217 
218 #define	XMAC_ADDR_OFFSET_0		0
219 #define	XMAC_ADDR_OFFSET_1		0x6000
220 
221 #define	XMAC_ADDR_OFFSET(port_num)\
222 	(XMAC_ADDR_OFFSET_0 + ((port_num) * PORT_1_OFFSET))
223 
224 #define	XMAC_REG_ADDR(port_num, reg)\
225 	(FZC_MAC + (XMAC_ADDR_OFFSET(port_num)) + (reg))
226 
227 #define	XMAC_PORT_ADDR(port_num)\
228 	(FZC_MAC + XMAC_ADDR_OFFSET(port_num))
229 
230 /* BMAC address macros */
231 
232 #define	BMAC_ADDR_OFFSET_2		0x0C000
233 #define	BMAC_ADDR_OFFSET_3		0x10000
234 
235 #define	BMAC_ADDR_OFFSET(port_num)\
236 	(BMAC_ADDR_OFFSET_2 + (((port_num) - 2) * PORT_GT_1_OFFSET))
237 
238 #define	BMAC_REG_ADDR(port_num, reg)\
239 	(FZC_MAC + (BMAC_ADDR_OFFSET(port_num)) + (reg))
240 
241 #define	BMAC_PORT_ADDR(port_num)\
242 	(FZC_MAC + BMAC_ADDR_OFFSET(port_num))
243 
244 /* PCS address macros */
245 
246 #define	PCS_ADDR_OFFSET_0		0x04000
247 #define	PCS_ADDR_OFFSET_1		0x0A000
248 #define	PCS_ADDR_OFFSET_2		0x0E000
249 #define	PCS_ADDR_OFFSET_3		0x12000
250 
251 #define	PCS_ADDR_OFFSET(port_num)\
252 	((port_num <= 1) ? \
253 	(PCS_ADDR_OFFSET_0 + (port_num) * PORT_1_OFFSET) : \
254 	(PCS_ADDR_OFFSET_2 + (((port_num) - 2) * PORT_GT_1_OFFSET)))
255 
256 #define	PCS_REG_ADDR(port_num, reg)\
257 	(FZC_MAC + (PCS_ADDR_OFFSET((port_num)) + (reg)))
258 
259 #define	PCS_PORT_ADDR(port_num)\
260 	(FZC_MAC + (PCS_ADDR_OFFSET(port_num)))
261 
262 /* XPCS address macros */
263 
264 #define	XPCS_ADDR_OFFSET_0		0x02000
265 #define	XPCS_ADDR_OFFSET_1		0x08000
266 #define	XPCS_ADDR_OFFSET(port_num)\
267 	(XPCS_ADDR_OFFSET_0 + ((port_num) * PORT_1_OFFSET))
268 
269 #define	XPCS_ADDR(port_num, reg)\
270 	(FZC_MAC + (XPCS_ADDR_OFFSET((port_num)) + (reg)))
271 
272 #define	XPCS_PORT_ADDR(port_num)\
273 	(FZC_MAC + (XPCS_ADDR_OFFSET(port_num)))
274 
275 /* ESR address macro */
276 #define	ESR_ADDR_OFFSET		0x14000
277 #define	ESR_ADDR(reg)\
278 	(FZC_MAC + (ESR_ADDR_OFFSET) + (reg))
279 
280 /* MIF address macros */
281 #define	MIF_ADDR_OFFSET		0x16000
282 #define	MIF_ADDR(reg)\
283 	(FZC_MAC + (MIF_ADDR_OFFSET) + (reg))
284 
285 /* BMAC registers offset */
286 #define	BTXMAC_SW_RST_REG		0x000	/* TX MAC software reset */
287 #define	BRXMAC_SW_RST_REG		0x008	/* RX MAC software reset */
288 #define	MAC_SEND_PAUSE_REG		0x010	/* send pause command */
289 #define	BTXMAC_STATUS_REG		0x020	/* TX MAC status */
290 #define	BRXMAC_STATUS_REG		0x028	/* RX MAC status */
291 #define	BMAC_CTRL_STAT_REG		0x030	/* MAC control status */
292 #define	BTXMAC_STAT_MSK_REG		0x040	/* TX MAC mask */
293 #define	BRXMAC_STAT_MSK_REG		0x048	/* RX MAC mask */
294 #define	BMAC_C_S_MSK_REG		0x050	/* MAC control mask */
295 #define	TXMAC_CONFIG_REG		0x060	/* TX MAC config */
296 /* cfg register bitmap */
297 
298 typedef union _btxmac_config_t {
299 	uint64_t value;
300 
301 	struct {
302 #if defined(_BIG_ENDIAN)
303 		uint32_t msw;	/* Most significant word */
304 		uint32_t lsw;	/* Least significant word */
305 #elif defined(_LITTLE_ENDIAN)
306 		uint32_t lsw;	/* Least significant word */
307 		uint32_t msw;	/* Most significant word */
308 #endif
309 	} val;
310 	struct {
311 #if defined(_BIG_ENDIAN)
312 		uint32_t	w1;
313 #endif
314 		struct {
315 #if defined(_BIT_FIELDS_HTOL)
316 			uint32_t rsrvd	: 22;
317 			uint32_t hdx_ctrl2	: 1;
318 			uint32_t no_fcs	: 1;
319 			uint32_t hdx_ctrl	: 7;
320 			uint32_t txmac_enable	: 1;
321 #elif defined(_BIT_FIELDS_LTOH)
322 			uint32_t txmac_enable	: 1;
323 			uint32_t hdx_ctrl	: 7;
324 			uint32_t no_fcs	: 1;
325 			uint32_t hdx_ctrl2	: 1;
326 			uint32_t rsrvd	: 22;
327 #endif
328 		} w0;
329 
330 #if defined(_LITTLE_ENDIAN)
331 		uint32_t	w1;
332 #endif
333 	} bits;
334 } btxmac_config_t, *p_btxmac_config_t;
335 
336 #define	RXMAC_CONFIG_REG		0x068	/* RX MAC config */
337 
338 typedef union _brxmac_config_t {
339 	uint64_t value;
340 
341 	struct {
342 #if defined(_BIG_ENDIAN)
343 		uint32_t msw;	/* Most significant word */
344 		uint32_t lsw;	/* Least significant word */
345 #elif defined(_LITTLE_ENDIAN)
346 		uint32_t lsw;	/* Least significant word */
347 		uint32_t msw;	/* Most significant word */
348 #endif
349 	} val;
350 	struct {
351 #if defined(_BIG_ENDIAN)
352 		uint32_t	w1;
353 #endif
354 		struct {
355 #if defined(_BIT_FIELDS_HTOL)
356 			uint32_t rsrvd	: 20;
357 			uint32_t mac_reg_sw_test : 2;
358 			uint32_t mac2ipp_pkt_cnt_en : 1;
359 			uint32_t rx_crs_extend_en : 1;
360 			uint32_t error_chk_dis	: 1;
361 			uint32_t addr_filter_en	: 1;
362 			uint32_t hash_filter_en	: 1;
363 			uint32_t promiscuous_group	: 1;
364 			uint32_t promiscuous	: 1;
365 			uint32_t strip_fcs	: 1;
366 			uint32_t strip_pad	: 1;
367 			uint32_t rxmac_enable	: 1;
368 #elif defined(_BIT_FIELDS_LTOH)
369 			uint32_t rxmac_enable	: 1;
370 			uint32_t strip_pad	: 1;
371 			uint32_t strip_fcs	: 1;
372 			uint32_t promiscuous	: 1;
373 			uint32_t promiscuous_group	: 1;
374 			uint32_t hash_filter_en	: 1;
375 			uint32_t addr_filter_en	: 1;
376 			uint32_t error_chk_dis	: 1;
377 			uint32_t rx_crs_extend_en : 1;
378 			uint32_t mac2ipp_pkt_cnt_en : 1;
379 			uint32_t mac_reg_sw_test : 2;
380 			uint32_t rsrvd	: 20;
381 #endif
382 		} w0;
383 
384 #if defined(_LITTLE_ENDIAN)
385 		uint32_t	w1;
386 #endif
387 	} bits;
388 } brxmac_config_t, *p_brxmac_config_t;
389 
390 #define	MAC_CTRL_CONFIG_REG		0x070	/* MAC control config */
391 #define	MAC_XIF_CONFIG_REG		0x078	/* XIF config */
392 
393 typedef union _bxif_config_t {
394 	uint64_t value;
395 
396 	struct {
397 #if defined(_BIG_ENDIAN)
398 		uint32_t msw;	/* Most significant word */
399 		uint32_t lsw;	/* Least significant word */
400 #elif defined(_LITTLE_ENDIAN)
401 		uint32_t lsw;	/* Least significant word */
402 		uint32_t msw;	/* Most significant word */
403 #endif
404 	} val;
405 	struct {
406 #if defined(_BIG_ENDIAN)
407 		uint32_t	w1;
408 #endif
409 		struct {
410 #if defined(_BIT_FIELDS_HTOL)
411 			uint32_t rsrvd2		: 24;
412 			uint32_t sel_clk_25mhz	: 1;
413 			uint32_t led_polarity	: 1;
414 			uint32_t force_led_on	: 1;
415 			uint32_t used		: 1;
416 			uint32_t gmii_mode	: 1;
417 			uint32_t rsrvd		: 1;
418 			uint32_t loopback	: 1;
419 			uint32_t tx_output_en	: 1;
420 #elif defined(_BIT_FIELDS_LTOH)
421 			uint32_t tx_output_en	: 1;
422 			uint32_t loopback	: 1;
423 			uint32_t rsrvd		: 1;
424 			uint32_t gmii_mode	: 1;
425 			uint32_t used		: 1;
426 			uint32_t force_led_on	: 1;
427 			uint32_t led_polarity	: 1;
428 			uint32_t sel_clk_25mhz	: 1;
429 			uint32_t rsrvd2		: 24;
430 #endif
431 		} w0;
432 
433 #if defined(_LITTLE_ENDIAN)
434 		uint32_t	w1;
435 #endif
436 	} bits;
437 } bxif_config_t, *p_bxif_config_t;
438 
439 #define	BMAC_MIN_REG			0x0a0	/* min frame size */
440 #define	BMAC_MAX_REG			0x0a8	/* max frame size reg */
441 #define	MAC_PA_SIZE_REG			0x0b0	/* num of preamble bytes */
442 #define	MAC_CTRL_TYPE_REG		0x0c8	/* type field of MAC ctrl */
443 #define	BMAC_ADDR0_REG			0x100	/* MAC unique ad0 reg (HI 0) */
444 #define	BMAC_ADDR1_REG			0x108	/* MAC unique ad1 reg */
445 #define	BMAC_ADDR2_REG			0x110	/* MAC unique ad2 reg */
446 #define	BMAC_ADDR3_REG			0x118	/* MAC alt ad0 reg (HI 1) */
447 #define	BMAC_ADDR4_REG			0x120	/* MAC alt ad0 reg */
448 #define	BMAC_ADDR5_REG			0x128	/* MAC alt ad0 reg */
449 #define	BMAC_ADDR6_REG			0x130	/* MAC alt ad1 reg (HI 2) */
450 #define	BMAC_ADDR7_REG			0x138	/* MAC alt ad1 reg */
451 #define	BMAC_ADDR8_REG			0x140	/* MAC alt ad1 reg */
452 #define	BMAC_ADDR9_REG			0x148	/* MAC alt ad2 reg (HI 3) */
453 #define	BMAC_ADDR10_REG			0x150	/* MAC alt ad2 reg */
454 #define	BMAC_ADDR11_REG			0x158	/* MAC alt ad2 reg */
455 #define	BMAC_ADDR12_REG			0x160	/* MAC alt ad3 reg (HI 4) */
456 #define	BMAC_ADDR13_REG			0x168	/* MAC alt ad3 reg */
457 #define	BMAC_ADDR14_REG			0x170	/* MAC alt ad3 reg */
458 #define	BMAC_ADDR15_REG			0x178	/* MAC alt ad4 reg (HI 5) */
459 #define	BMAC_ADDR16_REG			0x180	/* MAC alt ad4 reg */
460 #define	BMAC_ADDR17_REG			0x188	/* MAC alt ad4 reg */
461 #define	BMAC_ADDR18_REG			0x190	/* MAC alt ad5 reg (HI 6) */
462 #define	BMAC_ADDR19_REG			0x198	/* MAC alt ad5 reg */
463 #define	BMAC_ADDR20_REG			0x1a0	/* MAC alt ad5 reg */
464 #define	BMAC_ADDR21_REG			0x1a8	/* MAC alt ad6 reg (HI 7) */
465 #define	BMAC_ADDR22_REG			0x1b0	/* MAC alt ad6 reg */
466 #define	BMAC_ADDR23_REG			0x1b8	/* MAC alt ad6 reg */
467 #define	MAC_FC_ADDR0_REG		0x268	/* FC frame addr0 (HI 0, p3) */
468 #define	MAC_FC_ADDR1_REG		0x270	/* FC frame addr1 */
469 #define	MAC_FC_ADDR2_REG		0x278	/* FC frame addr2 */
470 #define	MAC_ADDR_FILT0_REG		0x298	/* bits [47:32] (HI 0, p2) */
471 #define	MAC_ADDR_FILT1_REG		0x2a0	/* bits [31:16] */
472 #define	MAC_ADDR_FILT2_REG		0x2a8	/* bits [15:0]  */
473 #define	MAC_ADDR_FILT12_MASK_REG 	0x2b0	/* addr filter 2 & 1 mask */
474 #define	MAC_ADDR_FILT00_MASK_REG	0x2b8	/* addr filter 0 mask */
475 #define	MAC_HASH_TBL0_REG		0x2c0	/* hash table 0 reg */
476 #define	MAC_HASH_TBL1_REG		0x2c8	/* hash table 1 reg */
477 #define	MAC_HASH_TBL2_REG		0x2d0	/* hash table 2 reg */
478 #define	MAC_HASH_TBL3_REG		0x2d8	/* hash table 3 reg */
479 #define	MAC_HASH_TBL4_REG		0x2e0	/* hash table 4 reg */
480 #define	MAC_HASH_TBL5_REG		0x2e8	/* hash table 5 reg */
481 #define	MAC_HASH_TBL6_REG		0x2f0	/* hash table 6 reg */
482 #define	MAC_HASH_TBL7_REG		0x2f8	/* hash table 7 reg */
483 #define	MAC_HASH_TBL8_REG		0x300	/* hash table 8 reg */
484 #define	MAC_HASH_TBL9_REG		0x308	/* hash table 9 reg */
485 #define	MAC_HASH_TBL10_REG		0x310	/* hash table 10 reg */
486 #define	MAC_HASH_TBL11_REG		0x318	/* hash table 11 reg */
487 #define	MAC_HASH_TBL12_REG		0x320	/* hash table 12 reg */
488 #define	MAC_HASH_TBL13_REG		0x328	/* hash table 13 reg */
489 #define	MAC_HASH_TBL14_REG		0x330	/* hash table 14 reg */
490 #define	MAC_HASH_TBL15_REG		0x338	/* hash table 15 reg */
491 #define	RXMAC_FRM_CNT_REG		0x370	/* receive frame counter */
492 #define	MAC_LEN_ER_CNT_REG		0x378	/* length error counter */
493 #define	BMAC_AL_ER_CNT_REG		0x380	/* alignment error counter */
494 #define	BMAC_CRC_ER_CNT_REG		0x388	/* FCS error counter */
495 #define	BMAC_CD_VIO_CNT_REG		0x390	/* RX code violation err */
496 #define	BMAC_SM_REG			0x3a0	/* (ro) state machine reg */
497 #define	BMAC_ALTAD_CMPEN_REG		0x3f8	/* Alt addr compare enable */
498 #define	BMAC_HOST_INF0_REG		0x400	/* Host info */
499 						/* (own da, add filter, fc) */
500 #define	BMAC_HOST_INF1_REG		0x408	/* Host info (alt ad 0) */
501 #define	BMAC_HOST_INF2_REG		0x410	/* Host info (alt ad 1) */
502 #define	BMAC_HOST_INF3_REG		0x418	/* Host info (alt ad 2) */
503 #define	BMAC_HOST_INF4_REG		0x420	/* Host info (alt ad 3) */
504 #define	BMAC_HOST_INF5_REG		0x428	/* Host info (alt ad 4) */
505 #define	BMAC_HOST_INF6_REG		0x430	/* Host info (alt ad 5) */
506 #define	BMAC_HOST_INF7_REG		0x438	/* Host info (alt ad 6) */
507 #define	BMAC_HOST_INF8_REG		0x440	/* Host info (hash hit, miss) */
508 #define	BTXMAC_BYTE_CNT_REG		0x448	/* Tx byte count */
509 #define	BTXMAC_FRM_CNT_REG		0x450	/* frame count */
510 #define	BRXMAC_BYTE_CNT_REG		0x458	/* Rx byte count */
511 /* x ranges from 0 to 6 (BMAC_MAX_ALT_ADDR_ENTRY - 1) */
512 #define	BMAC_ALT_ADDR0N_REG_ADDR(x)	(BMAC_ADDR3_REG + (x) * 24)
513 #define	BMAC_ALT_ADDR1N_REG_ADDR(x)	(BMAC_ADDR3_REG + 8 + (x) * 24)
514 #define	BMAC_ALT_ADDR2N_REG_ADDR(x)	(BMAC_ADDR3_REG + 0x10 + (x) * 24)
515 #define	BMAC_HASH_TBLN_REG_ADDR(x)	(MAC_HASH_TBL0_REG + (x) * 8)
516 #define	BMAC_HOST_INFN_REG_ADDR(x)	(BMAC_HOST_INF0_REG + (x) * 8)
517 
518 /* XMAC registers offset */
519 #define	XTXMAC_SW_RST_REG		0x000	/* XTX MAC soft reset */
520 #define	XRXMAC_SW_RST_REG		0x008	/* XRX MAC soft reset */
521 #define	XTXMAC_STATUS_REG		0x020	/* XTX MAC status */
522 #define	XRXMAC_STATUS_REG		0x028	/* XRX MAC status */
523 #define	XMAC_CTRL_STAT_REG		0x030	/* Control / Status */
524 #define	XTXMAC_STAT_MSK_REG		0x040	/* XTX MAC Status mask */
525 #define	XRXMAC_STAT_MSK_REG		0x048	/* XRX MAC Status mask */
526 #define	XMAC_C_S_MSK_REG		0x050	/* Control / Status mask */
527 #define	XMAC_CONFIG_REG			0x060	/* Configuration */
528 
529 /* xmac config bit fields */
530 typedef union _xmac_cfg_t {
531 	uint64_t value;
532 
533 	struct {
534 #if defined(_BIG_ENDIAN)
535 		uint32_t msw;	/* Most significant word */
536 		uint32_t lsw;	/* Least significant word */
537 #elif defined(_LITTLE_ENDIAN)
538 		uint32_t lsw;	/* Least significant word */
539 		uint32_t msw;	/* Most significant word */
540 #endif
541 	} val;
542 	struct {
543 #if defined(_BIG_ENDIAN)
544 		uint32_t	w1;
545 #endif
546 		struct {
547 #if defined(_BIT_FIELDS_HTOL)
548 		uint32_t sel_clk_25mhz : 1;
549 		uint32_t pcs_bypass	: 1;
550 		uint32_t xpcs_bypass	: 1;
551 		uint32_t mii_gmii_mode	: 2;
552 		uint32_t lfs_disable	: 1;
553 		uint32_t loopback	: 1;
554 		uint32_t tx_output_en	: 1;
555 		uint32_t sel_por_clk_src : 1;
556 		uint32_t led_polarity	: 1;
557 		uint32_t force_led_on	: 1;
558 		uint32_t pass_fctl_frames : 1;
559 		uint32_t recv_pause_en	: 1;
560 		uint32_t mac2ipp_pkt_cnt_en : 1;
561 		uint32_t strip_crc	: 1;
562 		uint32_t addr_filter_en	: 1;
563 		uint32_t hash_filter_en	: 1;
564 		uint32_t code_viol_chk_dis	: 1;
565 		uint32_t reserved_mcast	: 1;
566 		uint32_t rx_crc_chk_dis	: 1;
567 		uint32_t error_chk_dis	: 1;
568 		uint32_t promisc_grp	: 1;
569 		uint32_t promiscuous	: 1;
570 		uint32_t rx_mac_enable	: 1;
571 		uint32_t warning_msg_en	: 1;
572 		uint32_t used		: 3;
573 		uint32_t always_no_crc	: 1;
574 		uint32_t var_min_ipg_en	: 1;
575 		uint32_t strech_mode	: 1;
576 		uint32_t tx_enable	: 1;
577 #elif defined(_BIT_FIELDS_LTOH)
578 		uint32_t tx_enable	: 1;
579 		uint32_t strech_mode	: 1;
580 		uint32_t var_min_ipg_en	: 1;
581 		uint32_t always_no_crc	: 1;
582 		uint32_t used		: 3;
583 		uint32_t warning_msg_en	: 1;
584 		uint32_t rx_mac_enable	: 1;
585 		uint32_t promiscuous	: 1;
586 		uint32_t promisc_grp	: 1;
587 		uint32_t error_chk_dis	: 1;
588 		uint32_t rx_crc_chk_dis	: 1;
589 		uint32_t reserved_mcast	: 1;
590 		uint32_t code_viol_chk_dis	: 1;
591 		uint32_t hash_filter_en	: 1;
592 		uint32_t addr_filter_en	: 1;
593 		uint32_t strip_crc	: 1;
594 		uint32_t mac2ipp_pkt_cnt_en : 1;
595 		uint32_t recv_pause_en	: 1;
596 		uint32_t pass_fctl_frames : 1;
597 		uint32_t force_led_on	: 1;
598 		uint32_t led_polarity	: 1;
599 		uint32_t sel_por_clk_src : 1;
600 		uint32_t tx_output_en	: 1;
601 		uint32_t loopback	: 1;
602 		uint32_t lfs_disable	: 1;
603 		uint32_t mii_gmii_mode	: 2;
604 		uint32_t xpcs_bypass	: 1;
605 		uint32_t pcs_bypass	: 1;
606 		uint32_t sel_clk_25mhz : 1;
607 #endif
608 		} w0;
609 
610 #if defined(_LITTLE_ENDIAN)
611 		uint32_t	w1;
612 #endif
613 	} bits;
614 } xmac_cfg_t, *p_xmac_cfg_t;
615 
616 #define	XMAC_IPG_REG			0x080	/* Inter-Packet-Gap */
617 #define	XMAC_MIN_REG			0x088	/* min frame size register */
618 #define	XMAC_MAX_REG			0x090	/* max frame/burst size */
619 #define	XMAC_ADDR0_REG			0x0a0	/* [47:32] of MAC addr (HI17) */
620 #define	XMAC_ADDR1_REG			0x0a8	/* [31:16] of MAC addr */
621 #define	XMAC_ADDR2_REG			0x0b0	/* [15:0] of MAC addr */
622 #define	XRXMAC_BT_CNT_REG		0x100	/* bytes received / 8 */
623 #define	XRXMAC_BC_FRM_CNT_REG		0x108	/* good BC frames received */
624 #define	XRXMAC_MC_FRM_CNT_REG		0x110	/* good MC frames received */
625 #define	XRXMAC_FRAG_CNT_REG		0x118	/* frag frames rejected */
626 #define	XRXMAC_HIST_CNT1_REG		0x120	/* 64 bytes frames */
627 #define	XRXMAC_HIST_CNT2_REG		0x128	/* 65-127 bytes frames */
628 #define	XRXMAC_HIST_CNT3_REG		0x130	/* 128-255 bytes frames */
629 #define	XRXMAC_HIST_CNT4_REG		0x138	/* 256-511 bytes frames */
630 #define	XRXMAC_HIST_CNT5_REG		0x140	/* 512-1023 bytes frames */
631 #define	XRXMAC_HIST_CNT6_REG		0x148	/* 1024-1522 bytes frames */
632 #define	XRXMAC_MPSZER_CNT_REG		0x150	/* frames > maxframesize */
633 #define	XRXMAC_CRC_ER_CNT_REG		0x158	/* frames failed CRC */
634 #define	XRXMAC_CD_VIO_CNT_REG		0x160	/* frames with code vio */
635 #define	XRXMAC_AL_ER_CNT_REG		0x168	/* frames with align error */
636 #define	XTXMAC_FRM_CNT_REG		0x170	/* tx frames */
637 #define	XTXMAC_BYTE_CNT_REG		0x178	/* tx bytes / 8 */
638 #define	XMAC_LINK_FLT_CNT_REG		0x180	/* link faults */
639 #define	XRXMAC_HIST_CNT7_REG		0x188	/* MAC2IPP/>1523 bytes frames */
640 #define	XMAC_SM_REG			0x1a8	/* State machine */
641 #define	XMAC_INTERN1_REG		0x1b0	/* internal signals for diag */
642 #define	XMAC_INTERN2_REG		0x1b8	/* internal signals for diag */
643 #define	XMAC_ADDR_CMPEN_REG		0x208	/* alt MAC addr check */
644 #define	XMAC_ADDR3_REG			0x218	/* alt MAC addr 0 (HI 0) */
645 #define	XMAC_ADDR4_REG			0x220	/* alt MAC addr 0 */
646 #define	XMAC_ADDR5_REG			0x228	/* alt MAC addr 0 */
647 #define	XMAC_ADDR6_REG			0x230	/* alt MAC addr 1 (HI 1) */
648 #define	XMAC_ADDR7_REG			0x238	/* alt MAC addr 1 */
649 #define	XMAC_ADDR8_REG			0x240	/* alt MAC addr 1 */
650 #define	XMAC_ADDR9_REG			0x248	/* alt MAC addr 2 (HI 2) */
651 #define	XMAC_ADDR10_REG			0x250	/* alt MAC addr 2 */
652 #define	XMAC_ADDR11_REG			0x258	/* alt MAC addr 2 */
653 #define	XMAC_ADDR12_REG			0x260	/* alt MAC addr 3 (HI 3) */
654 #define	XMAC_ADDR13_REG			0x268	/* alt MAC addr 3 */
655 #define	XMAC_ADDR14_REG			0x270	/* alt MAC addr 3 */
656 #define	XMAC_ADDR15_REG			0x278	/* alt MAC addr 4 (HI 4) */
657 #define	XMAC_ADDR16_REG			0x280	/* alt MAC addr 4 */
658 #define	XMAC_ADDR17_REG			0x288	/* alt MAC addr 4 */
659 #define	XMAC_ADDR18_REG			0x290	/* alt MAC addr 5 (HI 5) */
660 #define	XMAC_ADDR19_REG			0x298	/* alt MAC addr 5 */
661 #define	XMAC_ADDR20_REG			0x2a0	/* alt MAC addr 5 */
662 #define	XMAC_ADDR21_REG			0x2a8	/* alt MAC addr 6 (HI 6) */
663 #define	XMAC_ADDR22_REG			0x2b0	/* alt MAC addr 6 */
664 #define	XMAC_ADDR23_REG			0x2b8	/* alt MAC addr 6 */
665 #define	XMAC_ADDR24_REG			0x2c0	/* alt MAC addr 7 (HI 7) */
666 #define	XMAC_ADDR25_REG			0x2c8	/* alt MAC addr 7 */
667 #define	XMAC_ADDR26_REG			0x2d0	/* alt MAC addr 7 */
668 #define	XMAC_ADDR27_REG			0x2d8	/* alt MAC addr 8 (HI 8) */
669 #define	XMAC_ADDR28_REG			0x2e0	/* alt MAC addr 8 */
670 #define	XMAC_ADDR29_REG			0x2e8	/* alt MAC addr 8 */
671 #define	XMAC_ADDR30_REG			0x2f0	/* alt MAC addr 9 (HI 9) */
672 #define	XMAC_ADDR31_REG			0x2f8	/* alt MAC addr 9 */
673 #define	XMAC_ADDR32_REG			0x300	/* alt MAC addr 9 */
674 #define	XMAC_ADDR33_REG			0x308	/* alt MAC addr 10 (HI 10) */
675 #define	XMAC_ADDR34_REG			0x310	/* alt MAC addr 10 */
676 #define	XMAC_ADDR35_REG			0x318	/* alt MAC addr 10 */
677 #define	XMAC_ADDR36_REG			0x320	/* alt MAC addr 11 (HI 11) */
678 #define	XMAC_ADDR37_REG			0x328	/* alt MAC addr 11 */
679 #define	XMAC_ADDR38_REG			0x330	/* alt MAC addr 11 */
680 #define	XMAC_ADDR39_REG			0x338	/* alt MAC addr 12 (HI 12) */
681 #define	XMAC_ADDR40_REG			0x340	/* alt MAC addr 12 */
682 #define	XMAC_ADDR41_REG			0x348	/* alt MAC addr 12 */
683 #define	XMAC_ADDR42_REG			0x350	/* alt MAC addr 13 (HI 13) */
684 #define	XMAC_ADDR43_REG			0x358	/* alt MAC addr 13 */
685 #define	XMAC_ADDR44_REG			0x360	/* alt MAC addr 13 */
686 #define	XMAC_ADDR45_REG			0x368	/* alt MAC addr 14 (HI 14) */
687 #define	XMAC_ADDR46_REG			0x370	/* alt MAC addr 14 */
688 #define	XMAC_ADDR47_REG			0x378	/* alt MAC addr 14 */
689 #define	XMAC_ADDR48_REG			0x380	/* alt MAC addr 15 (HI 15) */
690 #define	XMAC_ADDR49_REG			0x388	/* alt MAC addr 15 */
691 #define	XMAC_ADDR50_REG			0x390	/* alt MAC addr 15 */
692 #define	XMAC_ADDR_FILT0_REG		0x818	/* [47:32] addr filter (HI18) */
693 #define	XMAC_ADDR_FILT1_REG		0x820	/* [31:16] of addr filter */
694 #define	XMAC_ADDR_FILT2_REG		0x828	/* [15:0] of addr filter */
695 #define	XMAC_ADDR_FILT12_MASK_REG 	0x830	/* addr filter 2 & 1 mask */
696 #define	XMAC_ADDR_FILT0_MASK_REG	0x838	/* addr filter 0 mask */
697 #define	XMAC_HASH_TBL0_REG		0x840	/* hash table 0 reg */
698 #define	XMAC_HASH_TBL1_REG		0x848	/* hash table 1 reg */
699 #define	XMAC_HASH_TBL2_REG		0x850	/* hash table 2 reg */
700 #define	XMAC_HASH_TBL3_REG		0x858	/* hash table 3 reg */
701 #define	XMAC_HASH_TBL4_REG		0x860	/* hash table 4 reg */
702 #define	XMAC_HASH_TBL5_REG		0x868	/* hash table 5 reg */
703 #define	XMAC_HASH_TBL6_REG		0x870	/* hash table 6 reg */
704 #define	XMAC_HASH_TBL7_REG		0x878	/* hash table 7 reg */
705 #define	XMAC_HASH_TBL8_REG		0x880	/* hash table 8 reg */
706 #define	XMAC_HASH_TBL9_REG		0x888	/* hash table 9 reg */
707 #define	XMAC_HASH_TBL10_REG		0x890	/* hash table 10 reg */
708 #define	XMAC_HASH_TBL11_REG		0x898	/* hash table 11 reg */
709 #define	XMAC_HASH_TBL12_REG		0x8a0	/* hash table 12 reg */
710 #define	XMAC_HASH_TBL13_REG		0x8a8	/* hash table 13 reg */
711 #define	XMAC_HASH_TBL14_REG		0x8b0	/* hash table 14 reg */
712 #define	XMAC_HASH_TBL15_REG		0x8b8	/* hash table 15 reg */
713 #define	XMAC_HOST_INF0_REG		0x900	/* Host info 0 (alt ad 0) */
714 #define	XMAC_HOST_INF1_REG		0x908	/* Host info 1 (alt ad 1) */
715 #define	XMAC_HOST_INF2_REG		0x910	/* Host info 2 (alt ad 2) */
716 #define	XMAC_HOST_INF3_REG		0x918	/* Host info 3 (alt ad 3) */
717 #define	XMAC_HOST_INF4_REG		0x920	/* Host info 4 (alt ad 4) */
718 #define	XMAC_HOST_INF5_REG		0x928	/* Host info 5 (alt ad 5) */
719 #define	XMAC_HOST_INF6_REG		0x930	/* Host info 6 (alt ad 6) */
720 #define	XMAC_HOST_INF7_REG		0x938	/* Host info 7 (alt ad 7) */
721 #define	XMAC_HOST_INF8_REG		0x940	/* Host info 8 (alt ad 8) */
722 #define	XMAC_HOST_INF9_REG		0x948	/* Host info 9 (alt ad 9) */
723 #define	XMAC_HOST_INF10_REG		0x950	/* Host info 10 (alt ad 10) */
724 #define	XMAC_HOST_INF11_REG		0x958	/* Host info 11 (alt ad 11) */
725 #define	XMAC_HOST_INF12_REG		0x960	/* Host info 12 (alt ad 12) */
726 #define	XMAC_HOST_INF13_REG		0x968	/* Host info 13 (alt ad 13) */
727 #define	XMAC_HOST_INF14_REG		0x970	/* Host info 14 (alt ad 14) */
728 #define	XMAC_HOST_INF15_REG		0x978	/* Host info 15 (alt ad 15) */
729 #define	XMAC_HOST_INF16_REG		0x980	/* Host info 16 (hash hit) */
730 #define	XMAC_HOST_INF17_REG		0x988	/* Host info 17 (own da) */
731 #define	XMAC_HOST_INF18_REG		0x990	/* Host info 18 (filter hit) */
732 #define	XMAC_HOST_INF19_REG		0x998	/* Host info 19 (fc hit) */
733 #define	XMAC_PA_DATA0_REG		0xb80	/* preamble [31:0] */
734 #define	XMAC_PA_DATA1_REG		0xb88	/* preamble [63:32] */
735 #define	XMAC_DEBUG_SEL_REG		0xb90	/* debug select */
736 #define	XMAC_TRAINING_VECT_REG		0xb98	/* training vector */
737 /* x ranges from 0 to 15 (XMAC_MAX_ALT_ADDR_ENTRY - 1) */
738 #define	XMAC_ALT_ADDR0N_REG_ADDR(x)	(XMAC_ADDR3_REG + (x) * 24)
739 #define	XMAC_ALT_ADDR1N_REG_ADDR(x)	(XMAC_ADDR3_REG + 8 + (x) * 24)
740 #define	XMAC_ALT_ADDR2N_REG_ADDR(x)	(XMAC_ADDR3_REG + 16 + (x) * 24)
741 #define	XMAC_HASH_TBLN_REG_ADDR(x)	(XMAC_HASH_TBL0_REG + (x) * 8)
742 #define	XMAC_HOST_INFN_REG_ADDR(x)	(XMAC_HOST_INF0_REG + (x) * 8)
743 
744 /* MIF registers offset */
745 #define	MIF_BB_MDC_REG			0	   /* MIF bit-bang clock */
746 #define	MIF_BB_MDO_REG			0x008	   /* MIF bit-bang data */
747 #define	MIF_BB_MDO_EN_REG		0x010	   /* MIF bit-bang output en */
748 #define	MIF_OUTPUT_FRAME_REG		0x018	   /* MIF frame/output reg */
749 #define	MIF_CONFIG_REG			0x020	   /* MIF config reg */
750 #define	MIF_POLL_STATUS_REG		0x028	   /* MIF poll status reg */
751 #define	MIF_POLL_MASK_REG		0x030	   /* MIF poll mask reg */
752 #define	MIF_STATE_MACHINE_REG		0x038	   /* MIF state machine reg */
753 #define	MIF_STATUS_REG			0x040	   /* MIF status reg */
754 #define	MIF_MASK_REG			0x048	   /* MIF mask reg */
755 
756 
757 /* PCS registers offset */
758 #define	PCS_MII_CTRL_REG		0	   /* PCS MII control reg */
759 #define	PCS_MII_STATUS_REG		0x008	   /* PCS MII status reg */
760 #define	PCS_MII_ADVERT_REG		0x010	   /* PCS MII advertisement */
761 #define	PCS_MII_LPA_REG			0x018	   /* link partner ability */
762 #define	PCS_CONFIG_REG			0x020	   /* PCS config reg */
763 #define	PCS_STATE_MACHINE_REG		0x028	   /* PCS state machine */
764 #define	PCS_INTR_STATUS_REG		0x030	/* PCS interrupt status */
765 #define	PCS_DATAPATH_MODE_REG		0x0a0	   /* datapath mode reg */
766 #define	PCS_PACKET_COUNT_REG		0x0c0	   /* PCS packet counter */
767 
768 #define	XPCS_CTRL_1_REG			0	/* Control */
769 #define	XPCS_STATUS_1_REG		0x008
770 #define	XPCS_DEV_ID_REG			0x010	/* 32bits IEEE manufacture ID */
771 #define	XPCS_SPEED_ABILITY_REG		0x018
772 #define	XPCS_DEV_IN_PKG_REG		0x020
773 #define	XPCS_CTRL_2_REG			0x028
774 #define	XPCS_STATUS_2_REG		0x030
775 #define	XPCS_PKG_ID_REG			0x038	/* Package ID */
776 #define	XPCS_STATUS_REG			0x040
777 #define	XPCS_TEST_CTRL_REG		0x048
778 #define	XPCS_CFG_VENDOR_1_REG		0x050
779 #define	XPCS_DIAG_VENDOR_2_REG		0x058
780 #define	XPCS_MASK_1_REG			0x060
781 #define	XPCS_PKT_CNTR_REG		0x068
782 #define	XPCS_TX_STATE_MC_REG		0x070
783 #define	XPCS_DESKEW_ERR_CNTR_REG	0x078
784 #define	XPCS_SYM_ERR_CNTR_L0_L1_REG	0x080
785 #define	XPCS_SYM_ERR_CNTR_L2_L3_REG	0x088
786 #define	XPCS_TRAINING_VECTOR_REG	0x090
787 
788 /* ESR registers offset */
789 #define	ESR_RESET_REG			0
790 #define	ESR_CONFIG_REG			0x008
791 #define	ESR_0_PLL_CONFIG_REG		0x010
792 #define	ESR_0_CONTROL_REG		0x018
793 #define	ESR_0_TEST_CONFIG_REG		0x020
794 #define	ESR_1_PLL_CONFIG_REG		0x028
795 #define	ESR_1_CONTROL_REG		0x030
796 #define	ESR_1_TEST_CONFIG_REG		0x038
797 #define	ESR_ENET_RGMII_CFG_REG		0x040
798 #define	ESR_INTERNAL_SIGNALS_REG	0x800
799 #define	ESR_DEBUG_SEL_REG		0x808
800 
801 
802 /* Reset Register */
803 #define	MAC_SEND_PAUSE_TIME_MASK	0x0000FFFF /* value of pause time */
804 #define	MAC_SEND_PAUSE_SEND		0x00010000 /* send pause flow ctrl */
805 
806 /* Tx MAC Status Register */
807 #define	MAC_TX_FRAME_XMIT		0x00000001 /* successful tx frame */
808 #define	MAC_TX_UNDERRUN			0x00000002 /* starvation in xmit */
809 #define	MAC_TX_MAX_PACKET_ERR		0x00000004 /* TX frame exceeds max */
810 #define	MAC_TX_BYTE_CNT_EXP		0x00000400 /* TX byte cnt overflow */
811 #define	MAC_TX_FRAME_CNT_EXP		0x00000800 /* Tx frame cnt overflow */
812 
813 /* Rx MAC Status Register */
814 #define	MAC_RX_FRAME_RECV		0x00000001 /* successful rx frame */
815 #define	MAC_RX_OVERFLOW			0x00000002 /* RX FIFO overflow */
816 #define	MAC_RX_FRAME_COUNT		0x00000004 /* rx frame cnt rollover */
817 #define	MAC_RX_ALIGN_ERR		0x00000008 /* alignment err rollover */
818 #define	MAC_RX_CRC_ERR			0x00000010 /* crc error cnt rollover */
819 #define	MAC_RX_LEN_ERR			0x00000020 /* length err cnt rollover */
820 #define	MAC_RX_VIOL_ERR			0x00000040 /* code vio err rollover */
821 #define	MAC_RX_BYTE_CNT_EXP		0x00000080 /* RX MAC byte rollover */
822 
823 /* MAC Control Status Register */
824 #define	MAC_CTRL_PAUSE_RECEIVED		0x00000001 /* successful pause frame */
825 #define	MAC_CTRL_PAUSE_STATE		0x00000002 /* notpause-->pause */
826 #define	MAC_CTRL_NOPAUSE_STATE		0x00000004 /* pause-->notpause */
827 #define	MAC_CTRL_PAUSE_TIME_MASK	0xFFFF0000 /* value of pause time */
828 #define	MAC_CTRL_PAUSE_TIME_SHIFT	16
829 
830 /* Tx MAC Configuration Register */
831 #define	MAC_TX_CFG_TXMAC_ENABLE		0x00000001 /* enable TX MAC. */
832 #define	MAC_TX_CFG_NO_FCS		0x00000100 /* TX not generate CRC */
833 
834 /* Rx MAC Configuration Register */
835 #define	MAC_RX_CFG_RXMAC_ENABLE		0x00000001 /* enable RX MAC */
836 #define	MAC_RX_CFG_STRIP_PAD		0x00000002 /* not supported, set to 0 */
837 #define	MAC_RX_CFG_STRIP_FCS		0x00000004 /* strip last 4bytes (CRC) */
838 #define	MAC_RX_CFG_PROMISC		0x00000008 /* promisc mode enable */
839 #define	MAC_RX_CFG_PROMISC_GROUP  	0x00000010 /* accept all MC frames */
840 #define	MAC_RX_CFG_HASH_FILTER_EN	0x00000020 /* use hash table */
841 #define	MAC_RX_CFG_ADDR_FILTER_EN    	0x00000040 /* use address filter */
842 #define	MAC_RX_CFG_DISABLE_DISCARD	0x00000080 /* do not set abort bit */
843 #define	MAC_RX_MAC2IPP_PKT_CNT_EN	0x00000200 /* rx pkt cnt -> BMAC-IPP */
844 #define	MAC_RX_MAC_REG_RW_TEST_MASK	0x00000c00 /* BMAC reg RW test */
845 #define	MAC_RX_MAC_REG_RW_TEST_SHIFT	10
846 
847 /* MAC Control Configuration Register */
848 #define	MAC_CTRL_CFG_SEND_PAUSE_EN	0x00000001 /* send pause flow ctrl */
849 #define	MAC_CTRL_CFG_RECV_PAUSE_EN	0x00000002 /* receive pause flow ctrl */
850 #define	MAC_CTRL_CFG_PASS_CTRL		0x00000004 /* accept MAC ctrl pkts */
851 
852 /* MAC XIF Configuration Register */
853 #define	MAC_XIF_TX_OUTPUT_EN		0x00000001 /* enable Tx output driver */
854 #define	MAC_XIF_MII_INT_LOOPBACK	0x00000002 /* loopback GMII xmit data */
855 #define	MAC_XIF_GMII_MODE		0x00000008 /* operates with GMII clks */
856 #define	MAC_XIF_LINK_LED		0x00000020 /* LINKLED# active (low) */
857 #define	MAC_XIF_LED_POLARITY		0x00000040 /* LED polarity */
858 #define	MAC_XIF_SEL_CLK_25MHZ		0x00000080 /* Select 10/100Mbps */
859 
860 /* MAC IPG Registers */
861 #define	BMAC_MIN_FRAME_MASK		0x3FF	   /* 10-bit reg */
862 
863 /* MAC Max Frame Size Register */
864 #define	BMAC_MAX_BURST_MASK    		0x3FFF0000 /* max burst size [30:16] */
865 #define	BMAC_MAX_BURST_SHIFT   		16
866 #define	BMAC_MAX_FRAME_MASK    		0x00007FFF /* max frame size [14:0] */
867 #define	BMAC_MAX_FRAME_SHIFT   		0
868 
869 /* MAC Preamble size register */
870 #define	BMAC_PA_SIZE_MASK		0x000003FF
871 	/* # of preable bytes TxMAC sends at the beginning of each frame */
872 
873 /*
874  * mac address registers:
875  *	register	contains			comparison
876  *	--------	--------			----------
877  *	0		16 MSB of primary MAC addr	[47:32] of DA field
878  *	1		16 middle bits ""		[31:16] of DA field
879  *	2		16 LSB ""			[15:0] of DA field
880  *	3*x		16MSB of alt MAC addr 1-7	[47:32] of DA field
881  *	4*x		16 middle bits ""		[31:16]
882  *	5*x		16 LSB ""			[15:0]
883  *	42		16 MSB of MAC CTRL addr		[47:32] of DA.
884  *	43		16 middle bits ""		[31:16]
885  *	44		16 LSB ""			[15:0]
886  *	MAC CTRL addr must be the reserved multicast addr for MAC CTRL frames.
887  *	if there is a match, MAC will set the bit for alternative address
888  *	filter pass [15]
889  *
890  *	here is the map of registers given MAC address notation: a:b:c:d:e:f
891  *			ab		cd		ef
892  *	primary addr	reg 2		reg 1		reg 0
893  *	alt addr 1	reg 5		reg 4		reg 3
894  *	alt addr x	reg 5*x		reg 4*x		reg 3*x
895  *	|		|		|		|
896  *	|		|		|		|
897  *	alt addr 7	reg 23		reg 22		reg 21
898  *	ctrl addr	reg 44		reg 43		reg 42
899  */
900 
901 #define	BMAC_ALT_ADDR_BASE		0x118
902 #define	BMAC_MAX_ALT_ADDR_ENTRY		7	   /* 7 alternate MAC addr */
903 #define	BMAC_MAX_ADDR_ENTRY		(BMAC_MAX_ALT_ADDR_ENTRY + 1)
904 
905 /* hash table registers */
906 #define	MAC_MAX_HASH_ENTRY		16
907 
908 /* 27-bit register has the current state for key state machines in the MAC */
909 #define	MAC_SM_RLM_MASK			0x07800000
910 #define	MAC_SM_RLM_SHIFT		23
911 #define	MAC_SM_RX_FC_MASK		0x00700000
912 #define	MAC_SM_RX_FC_SHIFT		20
913 #define	MAC_SM_TLM_MASK			0x000F0000
914 #define	MAC_SM_TLM_SHIFT		16
915 #define	MAC_SM_ENCAP_SM_MASK		0x0000F000
916 #define	MAC_SM_ENCAP_SM_SHIFT		12
917 #define	MAC_SM_TX_REQ_MASK		0x00000C00
918 #define	MAC_SM_TX_REQ_SHIFT		10
919 #define	MAC_SM_TX_FC_MASK		0x000003C0
920 #define	MAC_SM_TX_FC_SHIFT		6
921 #define	MAC_SM_FIFO_WRITE_SEL_MASK	0x00000038
922 #define	MAC_SM_FIFO_WRITE_SEL_SHIFT	3
923 #define	MAC_SM_TX_FIFO_EMPTY_MASK	0x00000007
924 #define	MAC_SM_TX_FIFO_EMPTY_SHIFT	0
925 
926 #define	BMAC_ADDR0_CMPEN		0x00000001
927 #define	BMAC_ADDRN_CMPEN(x)		(BMAC_ADDR0_CMP_EN << (x))
928 
929 /* MAC Host Info Table Registers */
930 #define	BMAC_MAX_HOST_INFO_ENTRY	9 	/* 9 host entries */
931 
932 /*
933  * ********************* XMAC registers *********************************
934  */
935 
936 /* Reset Register */
937 #define	XTXMAC_SOFT_RST			0x00000001 /* XTX MAC software reset */
938 #define	XTXMAC_REG_RST			0x00000002 /* XTX MAC registers reset */
939 #define	XRXMAC_SOFT_RST			0x00000001 /* XRX MAC software reset */
940 #define	XRXMAC_REG_RST			0x00000002 /* XRX MAC registers reset */
941 
942 /* XTX MAC Status Register */
943 #define	XMAC_TX_FRAME_XMIT		0x00000001 /* successful tx frame */
944 #define	XMAC_TX_UNDERRUN		0x00000002 /* starvation in xmit */
945 #define	XMAC_TX_MAX_PACKET_ERR		0x00000004 /* XTX frame exceeds max */
946 #define	XMAC_TX_OVERFLOW		0x00000008 /* XTX byte cnt overflow */
947 #define	XMAC_TX_FIFO_XFR_ERR		0x00000010 /* xtlm state mach error */
948 #define	XMAC_TX_BYTE_CNT_EXP		0x00000400 /* XTX byte cnt overflow */
949 #define	XMAC_TX_FRAME_CNT_EXP		0x00000800 /* XTX frame cnt overflow */
950 
951 /* XRX MAC Status Register */
952 #define	XMAC_RX_FRAME_RCVD		0x00000001 /* successful rx frame */
953 #define	XMAC_RX_OVERFLOW		0x00000002 /* RX FIFO overflow */
954 #define	XMAC_RX_UNDERFLOW		0x00000004 /* RX FIFO underrun */
955 #define	XMAC_RX_CRC_ERR_CNT_EXP		0x00000008 /* crc error cnt rollover */
956 #define	XMAC_RX_LEN_ERR_CNT_EXP		0x00000010 /* length err cnt rollover */
957 #define	XMAC_RX_VIOL_ERR_CNT_EXP	0x00000020 /* code vio err rollover */
958 #define	XMAC_RX_OCT_CNT_EXP		0x00000040 /* XRX MAC byte rollover */
959 #define	XMAC_RX_HST_CNT1_EXP		0x00000080 /* XRX MAC hist1 rollover */
960 #define	XMAC_RX_HST_CNT2_EXP		0x00000100 /* XRX MAC hist2 rollover */
961 #define	XMAC_RX_HST_CNT3_EXP		0x00000200 /* XRX MAC hist3 rollover */
962 #define	XMAC_RX_HST_CNT4_EXP		0x00000400 /* XRX MAC hist4 rollover */
963 #define	XMAC_RX_HST_CNT5_EXP		0x00000800 /* XRX MAC hist5 rollover */
964 #define	XMAC_RX_HST_CNT6_EXP		0x00001000 /* XRX MAC hist6 rollover */
965 #define	XMAC_RX_BCAST_CNT_EXP		0x00002000 /* XRX BC cnt rollover */
966 #define	XMAC_RX_MCAST_CNT_EXP		0x00004000 /* XRX MC cnt rollover */
967 #define	XMAC_RX_FRAG_CNT_EXP		0x00008000 /* fragment cnt rollover */
968 #define	XMAC_RX_ALIGNERR_CNT_EXP	0x00010000 /* framealign err rollover */
969 #define	XMAC_RX_LINK_FLT_CNT_EXP	0x00020000 /* link fault cnt rollover */
970 #define	XMAC_RX_REMOTE_FLT_DET		0x00040000 /* Remote Fault detected */
971 #define	XMAC_RX_LOCAL_FLT_DET		0x00080000 /* Local Fault detected */
972 #define	XMAC_RX_HST_CNT7_EXP		0x00100000 /* XRX MAC hist7 rollover */
973 
974 
975 #define	XMAC_CTRL_PAUSE_RCVD		0x00000001 /* successful pause frame */
976 #define	XMAC_CTRL_PAUSE_STATE		0x00000002 /* notpause-->pause */
977 #define	XMAC_CTRL_NOPAUSE_STATE		0x00000004 /* pause-->notpause */
978 #define	XMAC_CTRL_PAUSE_TIME_MASK	0xFFFF0000 /* value of pause time */
979 #define	XMAC_CTRL_PAUSE_TIME_SHIFT	16
980 
981 /* XMAC Configuration Register */
982 #define	XMAC_CONFIG_TX_BIT_MASK		0x000000ff /* bits [7:0] */
983 #define	XMAC_CONFIG_RX_BIT_MASK		0x001fff00 /* bits [20:8] */
984 #define	XMAC_CONFIG_XIF_BIT_MASK	0xffe00000 /* bits [31:21] */
985 
986 /* XTX MAC config bits */
987 #define	XMAC_TX_CFG_TX_ENABLE		0x00000001 /* enable XTX MAC */
988 #define	XMAC_TX_CFG_STRETCH_MD		0x00000002 /* WAN application */
989 #define	XMAC_TX_CFG_VAR_MIN_IPG_EN	0x00000004 /* Transmit pkts < minpsz */
990 #define	XMAC_TX_CFG_ALWAYS_NO_CRC	0x00000008 /* No CRC generated */
991 
992 #define	XMAC_WARNING_MSG_ENABLE		0x00000080 /* Sim warning msg enable */
993 
994 /* XRX MAC config bits */
995 #define	XMAC_RX_CFG_RX_ENABLE		0x00000100 /* enable XRX MAC */
996 #define	XMAC_RX_CFG_PROMISC		0x00000200 /* promisc mode enable */
997 #define	XMAC_RX_CFG_PROMISC_GROUP  	0x00000400 /* accept all MC frames */
998 #define	XMAC_RX_CFG_ERR_CHK_DISABLE	0x00000800 /* do not set abort bit */
999 #define	XMAC_RX_CFG_CRC_CHK_DISABLE	0x00001000 /* disable CRC logic */
1000 #define	XMAC_RX_CFG_RESERVED_MCAST	0x00002000 /* reserved MCaddr compare */
1001 #define	XMAC_RX_CFG_CD_VIO_CHK		0x00004000 /* rx code violation chk */
1002 #define	XMAC_RX_CFG_HASH_FILTER_EN	0x00008000 /* use hash table */
1003 #define	XMAC_RX_CFG_ADDR_FILTER_EN	0x00010000 /* use alt addr filter */
1004 #define	XMAC_RX_CFG_STRIP_CRC		0x00020000 /* strip last 4bytes (CRC) */
1005 #define	XMAC_RX_MAC2IPP_PKT_CNT_EN	0x00040000 /* histo_cntr7 cnt mode */
1006 #define	XMAC_RX_CFG_RX_PAUSE_EN		0x00080000 /* receive pause flow ctrl */
1007 #define	XMAC_RX_CFG_PASS_FLOW_CTRL	0x00100000 /* accept MAC ctrl pkts */
1008 
1009 
1010 /* MAC transceiver (XIF) configuration registers */
1011 
1012 #define	XMAC_XIF_FORCE_LED_ON		0x00200000 /* Force Link LED on */
1013 #define	XMAC_XIF_LED_POLARITY		0x00400000 /* LED polarity */
1014 #define	XMAC_XIF_SEL_POR_CLK_SRC	0x00800000 /* Select POR clk src */
1015 #define	XMAC_XIF_TX_OUTPUT_EN		0x01000000 /* enable MII/GMII modes */
1016 #define	XMAC_XIF_LOOPBACK		0x02000000 /* loopback xmac xgmii tx */
1017 #define	XMAC_XIF_LFS_DISABLE		0x04000000 /* disable link fault sig */
1018 #define	XMAC_XIF_MII_MODE_MASK		0x18000000 /* MII/GMII/XGMII mode */
1019 #define	XMAC_XIF_MII_MODE_SHIFT		27
1020 #define	XMAC_XIF_XGMII_MODE		0x00
1021 #define	XMAC_XIF_GMII_MODE		0x01
1022 #define	XMAC_XIF_MII_MODE		0x02
1023 #define	XMAC_XIF_ILLEGAL_MODE		0x03
1024 #define	XMAC_XIF_XPCS_BYPASS		0x20000000 /* use external xpcs */
1025 #define	XMAC_XIF_1G_PCS_BYPASS		0x40000000 /* use external pcs */
1026 #define	XMAC_XIF_SEL_CLK_25MHZ		0x80000000 /* 25Mhz clk for 100mbps */
1027 
1028 /* IPG register */
1029 #define	XMAC_IPG_VALUE_MASK		0x00000007 /* IPG in XGMII mode */
1030 #define	XMAC_IPG_VALUE_SHIFT		0
1031 #define	XMAC_IPG_VALUE1_MASK		0x0000ff00 /* IPG in GMII/MII mode */
1032 #define	XMAC_IPG_VALUE1_SHIFT		8
1033 #define	XMAC_IPG_STRETCH_RATIO_MASK	0x001f0000
1034 #define	XMAC_IPG_STRETCH_RATIO_SHIFT	16
1035 #define	XMAC_IPG_STRETCH_CONST_MASK	0x00e00000
1036 #define	XMAC_IPG_STRETCH_CONST_SHIFT	21
1037 
1038 #define	IPG_12_15_BYTE			3
1039 #define	IPG_16_19_BYTE			4
1040 #define	IPG_20_23_BYTE			5
1041 #define	IPG1_12_BYTES			10
1042 #define	IPG1_13_BYTES			11
1043 #define	IPG1_14_BYTES			12
1044 #define	IPG1_15_BYTES			13
1045 #define	IPG1_16_BYTES			14
1046 
1047 
1048 #define	XMAC_MIN_TX_FRM_SZ_MASK		0x3ff	   /* Min tx frame size */
1049 #define	XMAC_MIN_TX_FRM_SZ_SHIFT	0
1050 #define	XMAC_SLOT_TIME_MASK		0x0003fc00 /* slot time */
1051 #define	XMAC_SLOT_TIME_SHIFT		10
1052 #define	XMAC_MIN_RX_FRM_SZ_MASK		0x3ff00000 /* Min rx frame size */
1053 #define	XMAC_MIN_RX_FRM_SZ_SHIFT	20
1054 #define	XMAC_MAX_FRM_SZ_MASK		0x00003fff /* max tx frame size */
1055 
1056 /* State Machine Register */
1057 #define	XMAC_SM_TX_LNK_MGMT_MASK	0x00000007
1058 #define	XMAC_SM_TX_LNK_MGMT_SHIFT	0
1059 #define	XMAC_SM_SOP_DETECT		0x00000008
1060 #define	XMAC_SM_LNK_FLT_SIG_MASK	0x00000030
1061 #define	XMAC_SM_LNK_FLT_SIG_SHIFT	4
1062 #define	XMAC_SM_MII_GMII_MD_RX_LNK	0x00000040
1063 #define	XMAC_SM_XGMII_MD_RX_LNK		0x00000080
1064 #define	XMAC_SM_XGMII_ONLY_VAL_SIG	0x00000100
1065 #define	XMAC_SM_ALT_ADR_N_HSH_FN_SIG	0x00000200
1066 #define	XMAC_SM_RXMAC_IPP_STAT_MASK	0x00001c00
1067 #define	XMAC_SM_RXMAC_IPP_STAT_SHIFT	10
1068 #define	XMAC_SM_RXFIFO_WPTR_CLK_MASK	0x007c0000
1069 #define	XMAC_SM_RXFIFO_WPTR_CLK_SHIFT	18
1070 #define	XMAC_SM_RXFIFO_RPTR_CLK_MASK	0x0F800000
1071 #define	XMAC_SM_RXFIFO_RPTR_CLK_SHIFT	23
1072 #define	XMAC_SM_TXFIFO_FULL_CLK		0x10000000
1073 #define	XMAC_SM_TXFIFO_EMPTY_CLK	0x20000000
1074 #define	XMAC_SM_RXFIFO_FULL_CLK		0x40000000
1075 #define	XMAC_SM_RXFIFO_EMPTY_CLK	0x80000000
1076 
1077 /* Internal Signals 1 Register */
1078 #define	XMAC_IS1_OPP_TXMAC_STAT_MASK	0x0000000F
1079 #define	XMAC_IS1_OPP_TXMAC_STAT_SHIFT	0
1080 #define	XMAC_IS1_OPP_TXMAC_ABORT	0x00000010
1081 #define	XMAC_IS1_OPP_TXMAC_TAG 		0x00000020
1082 #define	XMAC_IS1_OPP_TXMAC_ACK		0x00000040
1083 #define	XMAC_IS1_TXMAC_OPP_REQ		0x00000080
1084 #define	XMAC_IS1_RXMAC_IPP_STAT_MASK	0x0FFFFF00
1085 #define	XMAC_IS1_RXMAC_IPP_STAT_SHIFT	8
1086 #define	XMAC_IS1_RXMAC_IPP_CTRL		0x10000000
1087 #define	XMAC_IS1_RXMAC_IPP_TAG		0x20000000
1088 #define	XMAC_IS1_IPP_RXMAC_REQ		0x40000000
1089 #define	XMAC_IS1_RXMAC_IPP_ACK		0x80000000
1090 
1091 /* Internal Signals 2 Register */
1092 #define	XMAC_IS2_TX_HB_TIMER_MASK	0x0000000F
1093 #define	XMAC_IS2_TX_HB_TIMER_SHIFT	0
1094 #define	XMAC_IS2_RX_HB_TIMER_MASK	0x000000F0
1095 #define	XMAC_IS2_RX_HB_TIMER_SHIFT	4
1096 #define	XMAC_IS2_XPCS_RXC_MASK		0x0000FF00
1097 #define	XMAC_IS2_XPCS_RXC_SHIFT		8
1098 #define	XMAC_IS2_XPCS_TXC_MASK		0x00FF0000
1099 #define	XMAC_IS2_XPCS_TXC_SHIFT		16
1100 #define	XMAC_IS2_LOCAL_FLT_OC_SYNC	0x01000000
1101 #define	XMAC_IS2_RMT_FLT_OC_SYNC	0x02000000
1102 
1103 /* Register size masking */
1104 
1105 #define	XTXMAC_FRM_CNT_MASK		0xFFFFFFFF
1106 #define	XTXMAC_BYTE_CNT_MASK		0xFFFFFFFF
1107 #define	XRXMAC_CRC_ER_CNT_MASK		0x000000FF
1108 #define	XRXMAC_MPSZER_CNT_MASK		0x000000FF
1109 #define	XRXMAC_CD_VIO_CNT_MASK		0x000000FF
1110 #define	XRXMAC_BT_CNT_MASK		0xFFFFFFFF
1111 #define	XRXMAC_HIST_CNT1_MASK		0x001FFFFF
1112 #define	XRXMAC_HIST_CNT2_MASK		0x001FFFFF
1113 #define	XRXMAC_HIST_CNT3_MASK		0x000FFFFF
1114 #define	XRXMAC_HIST_CNT4_MASK		0x0007FFFF
1115 #define	XRXMAC_HIST_CNT5_MASK		0x0003FFFF
1116 #define	XRXMAC_HIST_CNT6_MASK		0x0001FFFF
1117 #define	XRXMAC_HIST_CNT7_MASK		0x07FFFFFF
1118 #define	XRXMAC_BC_FRM_CNT_MASK		0x001FFFFF
1119 #define	XRXMAC_MC_FRM_CNT_MASK		0x001FFFFF
1120 #define	XRXMAC_FRAG_CNT_MASK		0x001FFFFF
1121 #define	XRXMAC_AL_ER_CNT_MASK		0x000000FF
1122 #define	XMAC_LINK_FLT_CNT_MASK		0x000000FF
1123 #define	BTXMAC_FRM_CNT_MASK		0x001FFFFF
1124 #define	BTXMAC_BYTE_CNT_MASK		0x07FFFFFF
1125 #define	RXMAC_FRM_CNT_MASK		0x0000FFFF
1126 #define	BRXMAC_BYTE_CNT_MASK		0x07FFFFFF
1127 #define	BMAC_AL_ER_CNT_MASK		0x0000FFFF
1128 #define	MAC_LEN_ER_CNT_MASK		0x0000FFFF
1129 #define	BMAC_CRC_ER_CNT_MASK		0x0000FFFF
1130 #define	BMAC_CD_VIO_CNT_MASK		0x0000FFFF
1131 #define	XMAC_XPCS_DESKEW_ERR_CNT_MASK	0x000000FF
1132 #define	XMAC_XPCS_SYM_ERR_CNT_L0_MASK	0x0000FFFF
1133 #define	XMAC_XPCS_SYM_ERR_CNT_L1_MASK	0xFFFF0000
1134 #define	XMAC_XPCS_SYM_ERR_CNT_L1_SHIFT	16
1135 #define	XMAC_XPCS_SYM_ERR_CNT_L2_MASK	0x0000FFFF
1136 #define	XMAC_XPCS_SYM_ERR_CNT_L3_MASK	0xFFFF0000
1137 #define	XMAC_XPCS_SYM_ERR_CNT_L3_SHIFT	16
1138 
1139 /* Alternate MAC address registers */
1140 #define	XMAC_MAX_ALT_ADDR_ENTRY		16	   /* 16 alternate MAC addrs */
1141 #define	XMAC_MAX_ADDR_ENTRY		(XMAC_MAX_ALT_ADDR_ENTRY + 1)
1142 
1143 /* Max / Min parameters for Neptune MAC */
1144 
1145 #define	MAC_MAX_ALT_ADDR_ENTRY		XMAC_MAX_ALT_ADDR_ENTRY
1146 #define	MAC_MAX_HOST_INFO_ENTRY		XMAC_MAX_HOST_INFO_ENTRY
1147 
1148 /* HostInfo entry for the unique MAC address */
1149 #define	XMAC_UNIQUE_HOST_INFO_ENTRY	17
1150 #define	BMAC_UNIQUE_HOST_INFO_ENTRY	0
1151 
1152 /* HostInfo entry for the multicat address */
1153 #define	XMAC_MULTI_HOST_INFO_ENTRY	16
1154 #define	BMAC_MULTI_HOST_INFO_ENTRY	8
1155 
1156 /* XMAC Host Info Register */
1157 typedef union hostinfo {
1158 
1159 	uint64_t value;
1160 
1161 	struct {
1162 #if defined(_BIG_ENDIAN)
1163 		uint32_t msw;	/* Most significant word */
1164 		uint32_t lsw;	/* Least significant word */
1165 #elif defined(_LITTLE_ENDIAN)
1166 		uint32_t lsw;	/* Least significant word */
1167 		uint32_t msw;	/* Most significant word */
1168 #endif
1169 	} val;
1170 	struct {
1171 #if defined(_BIG_ENDIAN)
1172 		uint32_t	w1;
1173 #endif
1174 		struct {
1175 #if defined(_BIT_FIELDS_HTOL)
1176 		uint32_t reserved2	: 23;
1177 		uint32_t mac_pref	: 1;
1178 		uint32_t reserved1	: 5;
1179 		uint32_t rdc_tbl_num	: 3;
1180 #elif defined(_BIT_FIELDS_LTOH)
1181 		uint32_t rdc_tbl_num	: 3;
1182 		uint32_t reserved1	: 5;
1183 		uint32_t mac_pref	: 1;
1184 		uint32_t reserved2	: 23;
1185 #endif
1186 		} w0;
1187 
1188 #if defined(_LITTLE_ENDIAN)
1189 		uint32_t	w1;
1190 #endif
1191 	} bits;
1192 
1193 } hostinfo_t;
1194 
1195 typedef union hostinfo *hostinfo_pt;
1196 
1197 #define	XMAC_HI_RDC_TBL_NUM_MASK	0x00000007
1198 #define	XMAC_HI_MAC_PREF		0x00000100
1199 
1200 #define	XMAC_MAX_HOST_INFO_ENTRY	20	   /* 20 host entries */
1201 
1202 /*
1203  * ******************** MIF registers *********************************
1204  */
1205 
1206 /*
1207  * 32-bit register serves as an instruction register when the MIF is
1208  * programmed in frame mode. load this register w/ a valid instruction
1209  * (as per IEEE 802.3u MII spec). poll this register to check for instruction
1210  * execution completion. during a read operation, this register will also
1211  * contain the 16-bit data returned by the transceiver. unless specified
1212  * otherwise, fields are considered "don't care" when polling for
1213  * completion.
1214  */
1215 
1216 #define	MIF_FRAME_START_MASK		0xC0000000 /* start of frame mask */
1217 #define	MIF_FRAME_ST_22			0x40000000 /* STart of frame, Cl 22 */
1218 #define	MIF_FRAME_ST_45			0x00000000 /* STart of frame, Cl 45 */
1219 #define	MIF_FRAME_OPCODE_MASK		0x30000000 /* opcode */
1220 #define	MIF_FRAME_OP_READ_22		0x20000000 /* read OPcode, Cl 22 */
1221 #define	MIF_FRAME_OP_WRITE_22		0x10000000 /* write OPcode, Cl 22 */
1222 #define	MIF_FRAME_OP_ADDR_45		0x00000000 /* addr of reg to access */
1223 #define	MIF_FRAME_OP_READ_45		0x30000000 /* read OPcode, Cl 45 */
1224 #define	MIF_FRAME_OP_WRITE_45		0x10000000 /* write OPcode, Cl 45 */
1225 #define	MIF_FRAME_OP_P_R_I_A_45		0x10000000 /* post-read-inc-addr */
1226 #define	MIF_FRAME_PHY_ADDR_MASK		0x0F800000 /* phy address mask */
1227 #define	MIF_FRAME_PHY_ADDR_SHIFT	23
1228 #define	MIF_FRAME_REG_ADDR_MASK		0x007C0000 /* reg addr in Cl 22 */
1229 						/* dev addr in Cl 45 */
1230 #define	MIF_FRAME_REG_ADDR_SHIFT	18
1231 #define	MIF_FRAME_TURN_AROUND_MSB	0x00020000 /* turn around, MSB. */
1232 #define	MIF_FRAME_TURN_AROUND_LSB	0x00010000 /* turn around, LSB. */
1233 #define	MIF_FRAME_DATA_MASK		0x0000FFFF /* instruction payload */
1234 
1235 /* Clause 45 frame field values */
1236 #define	FRAME45_ST		0
1237 #define	FRAME45_OP_ADDR		0
1238 #define	FRAME45_OP_WRITE	1
1239 #define	FRAME45_OP_READ_INC	2
1240 #define	FRAME45_OP_READ		3
1241 
1242 typedef union _mif_frame_t {
1243 
1244 	uint64_t value;
1245 
1246 	struct {
1247 #if defined(_BIG_ENDIAN)
1248 		uint32_t msw;	/* Most significant word */
1249 		uint32_t lsw;	/* Least significant word */
1250 #elif defined(_LITTLE_ENDIAN)
1251 		uint32_t lsw;	/* Least significant word */
1252 		uint32_t msw;	/* Most significant word */
1253 #endif
1254 	} val;
1255 	struct {
1256 #if defined(_BIG_ENDIAN)
1257 		uint32_t	w1;
1258 #endif
1259 		struct {
1260 #if defined(_BIT_FIELDS_HTOL)
1261 		uint32_t st		: 2;
1262 		uint32_t op		: 2;
1263 		uint32_t phyad		: 5;
1264 		uint32_t regad		: 5;
1265 		uint32_t ta_msb		: 1;
1266 		uint32_t ta_lsb		: 1;
1267 		uint32_t data		: 16;
1268 #elif defined(_BIT_FIELDS_LTOH)
1269 		uint32_t data		: 16;
1270 		uint32_t ta_lsb		: 1;
1271 		uint32_t ta_msb		: 1;
1272 		uint32_t regad		: 5;
1273 		uint32_t phyad		: 5;
1274 		uint32_t op		: 2;
1275 		uint32_t st		: 2;
1276 #endif
1277 		} w0;
1278 
1279 #if defined(_LITTLE_ENDIAN)
1280 		uint32_t	w1;
1281 #endif
1282 	} bits;
1283 } mif_frame_t;
1284 
1285 #define	MIF_CFG_POLL_EN			0x00000008 /* enable polling */
1286 #define	MIF_CFG_BB_MODE			0x00000010 /* bit-bang mode */
1287 #define	MIF_CFG_POLL_REG_MASK		0x000003E0 /* reg addr to be polled */
1288 #define	MIF_CFG_POLL_REG_SHIFT		5
1289 #define	MIF_CFG_POLL_PHY_MASK		0x00007C00 /* XCVR addr to be polled */
1290 #define	MIF_CFG_POLL_PHY_SHIFT		10
1291 #define	MIF_CFG_INDIRECT_MODE		0x0000800
1292 					/* used to decide if Cl 22 */
1293 					/* or Cl 45 frame is */
1294 					/* constructed. */
1295 					/* 1 = Clause 45,ST = '00' */
1296 					/* 0 = Clause 22,ST = '01' */
1297 #define	MIF_CFG_ATCE_GE_EN	0x00010000 /* Enable ATCA gigabit mode */
1298 
1299 typedef union _mif_cfg_t {
1300 
1301 	uint64_t value;
1302 
1303 	struct {
1304 #if defined(_BIG_ENDIAN)
1305 		uint32_t msw;	/* Most significant word */
1306 		uint32_t lsw;	/* Least significant word */
1307 
1308 #elif defined(_LITTLE_ENDIAN)
1309 		uint32_t lsw;	/* Least significant word */
1310 		uint32_t msw;	/* Most significant word */
1311 #endif
1312 	} val;
1313 	struct {
1314 #if defined(_BIG_ENDIAN)
1315 		uint32_t	w1;
1316 #endif
1317 		struct {
1318 #if defined(_BIT_FIELDS_HTOL)
1319 		uint32_t res2		: 15;
1320 		uint32_t atca_ge	: 1;
1321 		uint32_t indirect_md	: 1;
1322 		uint32_t phy_addr	: 5;
1323 		uint32_t reg_addr	: 5;
1324 		uint32_t bb_mode	: 1;
1325 		uint32_t poll_en	: 1;
1326 		uint32_t res1		: 2;
1327 		uint32_t res		: 1;
1328 #elif defined(_BIT_FIELDS_LTOH)
1329 		uint32_t res		: 1;
1330 		uint32_t res1		: 2;
1331 		uint32_t poll_en	: 1;
1332 		uint32_t bb_mode	: 1;
1333 		uint32_t reg_addr	: 5;
1334 		uint32_t phy_addr	: 5;
1335 		uint32_t indirect_md	: 1;
1336 		uint32_t atca_ge	: 1;
1337 		uint32_t res2		: 15;
1338 #endif
1339 		} w0;
1340 
1341 #if defined(_LITTLE_ENDIAN)
1342 		uint32_t	w1;
1343 #endif
1344 	} bits;
1345 
1346 } mif_cfg_t;
1347 
1348 #define	MIF_POLL_STATUS_DATA_MASK	0xffff0000
1349 #define	MIF_POLL_STATUS_STAT_MASK	0x0000ffff
1350 
1351 typedef union _mif_poll_stat_t {
1352 	uint64_t value;
1353 
1354 	struct {
1355 #if defined(_BIG_ENDIAN)
1356 		uint32_t msw;	/* Most significant word */
1357 		uint32_t lsw;	/* Least significant word */
1358 #elif defined(_LITTLE_ENDIAN)
1359 		uint32_t lsw;	/* Least significant word */
1360 		uint32_t msw;	/* Most significant word */
1361 #endif
1362 	} val;
1363 	struct {
1364 #if defined(_BIG_ENDIAN)
1365 		uint32_t	w1;
1366 #endif
1367 		struct {
1368 #if defined(_BIT_FIELDS_HTOL)
1369 		uint16_t data;
1370 		uint16_t status;
1371 #elif defined(_BIT_FIELDS_LTOH)
1372 		uint16_t status;
1373 		uint16_t data;
1374 #endif
1375 		} w0;
1376 
1377 #if defined(_LITTLE_ENDIAN)
1378 		uint32_t	w1;
1379 #endif
1380 	} bits;
1381 } mif_poll_stat_t;
1382 
1383 
1384 #define	MIF_POLL_MASK_MASK	0x0000ffff
1385 
1386 typedef union _mif_poll_mask_t {
1387 	uint64_t value;
1388 
1389 	struct {
1390 #if defined(_BIG_ENDIAN)
1391 		uint32_t msw;	/* Most significant word */
1392 		uint32_t lsw;	/* Least significant word */
1393 #elif defined(_LITTLE_ENDIAN)
1394 		uint32_t lsw;	/* Least significant word */
1395 		uint32_t msw;	/* Most significant word */
1396 #endif
1397 	} val;
1398 	struct {
1399 #if defined(_BIG_ENDIAN)
1400 		uint32_t	w1;
1401 #endif
1402 		struct {
1403 #if defined(_BIT_FIELDS_HTOL)
1404 		uint16_t rsvd;
1405 		uint16_t mask;
1406 #elif defined(_BIT_FIELDS_LTOH)
1407 		uint16_t mask;
1408 		uint16_t rsvd;
1409 #endif
1410 		} w0;
1411 
1412 #if defined(_LITTLE_ENDIAN)
1413 		uint32_t	w1;
1414 #endif
1415 	} bits;
1416 } mif_poll_mask_t;
1417 
1418 #define	MIF_STATUS_INIT_DONE_MASK	0x00000001
1419 #define	MIF_STATUS_XGE_ERR0_MASK	0x00000002
1420 #define	MIF_STATUS_XGE_ERR1_MASK	0x00000004
1421 #define	MIF_STATUS_PEU_ERR_MASK		0x00000008
1422 #define	MIF_STATUS_EXT_PHY_INTR0_MASK	0x00000010
1423 #define	MIF_STATUS_EXT_PHY_INTR1_MASK	0x00000020
1424 
1425 typedef union _mif_stat_t {
1426 	uint64_t value;
1427 
1428 	struct {
1429 #if defined(_BIG_ENDIAN)
1430 		uint32_t msw;	/* Most significant word */
1431 		uint32_t lsw;	/* Least significant word */
1432 #elif defined(_LITTLE_ENDIAN)
1433 		uint32_t lsw;	/* Least significant word */
1434 		uint32_t msw;	/* Most significant word */
1435 #endif
1436 	} val;
1437 	struct {
1438 #if defined(_BIG_ENDIAN)
1439 		uint32_t	w1;
1440 #endif
1441 		struct {
1442 #if defined(_BIT_FIELDS_HTOL)
1443 		uint32_t rsvd:26;
1444 		uint32_t ext_phy_intr_flag1:1;
1445 		uint32_t ext_phy_intr_flag0:1;
1446 		uint32_t peu_err:1;
1447 		uint32_t xge_err1:1;
1448 		uint32_t xge_err0:1;
1449 		uint32_t mif_init_done_stat:1;
1450 
1451 #elif defined(_BIT_FIELDS_LTOH)
1452 		uint32_t mif_init_done_stat:1;
1453 		uint32_t xge_err0:1;
1454 		uint32_t xge_err1:1;
1455 		uint32_t ext_phy_intr_flag0:1;
1456 		uint32_t ext_phy_intr_flag1:1;
1457 		uint32_t rsvd:26;
1458 #endif
1459 		} w0;
1460 
1461 #if defined(_LITTLE_ENDIAN)
1462 		uint32_t	w1;
1463 #endif
1464 	} bits;
1465 } mif_stat_t;
1466 
1467 /* MIF State Machine Register */
1468 
1469 #define	MIF_SM_EXECUTION_MASK		0x0000003f /* execution state */
1470 #define	MIF_SM_EXECUTION_SHIFT		0
1471 #define	MIF_SM_CONTROL_MASK		0x000001c0 /* control state */
1472 #define	MIF_SM_CONTROL_MASK_SHIFT	6
1473 #define	MIF_SM_MDI			0x00000200
1474 #define	MIF_SM_MDO			0x00000400
1475 #define	MIF_SM_MDO_EN			0x00000800
1476 #define	MIF_SM_MDC			0x00001000
1477 #define	MIF_SM_MDI_0			0x00002000
1478 #define	MIF_SM_MDI_1			0x00004000
1479 #define	MIF_SM_MDI_2			0x00008000
1480 #define	MIF_SM_PORT_ADDR_MASK		0x001f0000
1481 #define	MIF_SM_PORT_ADDR_SHIFT		16
1482 #define	MIF_SM_INT_SIG_MASK		0xffe00000
1483 #define	MIF_SM_INT_SIG_SHIFT		21
1484 
1485 
1486 /*
1487  * ******************** PCS registers *********************************
1488  */
1489 
1490 /* PCS Registers */
1491 #define	PCS_MII_CTRL_1000_SEL		0x0040	   /* reads 1. ignored on wr */
1492 #define	PCS_MII_CTRL_COLLISION_TEST	0x0080	   /* COL signal */
1493 #define	PCS_MII_CTRL_DUPLEX		0x0100	   /* forced 0x0. */
1494 #define	PCS_MII_RESTART_AUTONEG		0x0200	   /* self clearing. */
1495 #define	PCS_MII_ISOLATE			0x0400	   /* read 0. ignored on wr */
1496 #define	PCS_MII_POWER_DOWN		0x0800	   /* read 0. ignored on wr */
1497 #define	PCS_MII_AUTONEG_EN		0x1000	   /* autonegotiation */
1498 #define	PCS_MII_10_100_SEL		0x2000	   /* read 0. ignored on wr */
1499 #define	PCS_MII_RESET			0x8000	   /* reset PCS. */
1500 
1501 typedef union _pcs_ctrl_t {
1502 	uint64_t value;
1503 
1504 	struct {
1505 #if defined(_BIG_ENDIAN)
1506 		uint32_t msw;	/* Most significant word */
1507 		uint32_t lsw;	/* Least significant word */
1508 #elif defined(_LITTLE_ENDIAN)
1509 		uint32_t lsw;	/* Least significant word */
1510 		uint32_t msw;	/* Most significant word */
1511 #endif
1512 	} val;
1513 	struct {
1514 #if defined(_BIG_ENDIAN)
1515 		uint32_t	w1;
1516 #endif
1517 		struct {
1518 #if defined(_BIT_FIELDS_HTOL)
1519 			uint32_t res0		: 16;
1520 			uint32_t reset		: 1;
1521 			uint32_t res1		: 1;
1522 			uint32_t sel_10_100	: 1;
1523 			uint32_t an_enable	: 1;
1524 			uint32_t pwr_down	: 1;
1525 			uint32_t isolate	: 1;
1526 			uint32_t restart_an	: 1;
1527 			uint32_t duplex		: 1;
1528 			uint32_t col_test	: 1;
1529 			uint32_t sel_1000	: 1;
1530 			uint32_t res2		: 6;
1531 #elif defined(_BIT_FIELDS_LTOH)
1532 			uint32_t res2		: 6;
1533 			uint32_t sel_1000	: 1;
1534 			uint32_t col_test	: 1;
1535 			uint32_t duplex		: 1;
1536 			uint32_t restart_an	: 1;
1537 			uint32_t isolate	: 1;
1538 			uint32_t pwr_down	: 1;
1539 			uint32_t an_enable	: 1;
1540 			uint32_t sel_10_100	: 1;
1541 			uint32_t res1		: 1;
1542 			uint32_t reset		: 1;
1543 			uint32_t res0		: 16;
1544 #endif
1545 		} w0;
1546 
1547 #if defined(_LITTLE_ENDIAN)
1548 		uint32_t	w1;
1549 #endif
1550 	} bits;
1551 } pcs_ctrl_t;
1552 
1553 #define	PCS_MII_STATUS_EXTEND_CAP	0x0001	   /* reads 0 */
1554 #define	PCS_MII_STATUS_JABBER_DETECT	0x0002	   /* reads 0 */
1555 #define	PCS_MII_STATUS_LINK_STATUS	0x0004	   /* link status */
1556 #define	PCS_MII_STATUS_AUTONEG_ABLE	0x0008	   /* reads 1 */
1557 #define	PCS_MII_STATUS_REMOTE_FAULT	0x0010	   /* remote fault detected */
1558 #define	PCS_MII_STATUS_AUTONEG_COMP	0x0020	   /* auto-neg completed */
1559 #define	PCS_MII_STATUS_EXTEND_STATUS	0x0100	   /* 1000 Base-X PHY */
1560 
1561 typedef union _pcs_stat_t {
1562 	uint64_t value;
1563 
1564 	struct {
1565 #if defined(_BIG_ENDIAN)
1566 		uint32_t msw;	/* Most significant word */
1567 		uint32_t lsw;	/* Least significant word */
1568 #elif defined(_LITTLE_ENDIAN)
1569 		uint32_t lsw;	/* Least significant word */
1570 		uint32_t msw;	/* Most significant word */
1571 #endif
1572 	} val;
1573 	struct {
1574 #if defined(_BIG_ENDIAN)
1575 		uint32_t	w1;
1576 #endif
1577 		struct {
1578 #if defined(_BIT_FIELDS_HTOL)
1579 		uint32_t res0		: 23;
1580 		uint32_t ext_stat	: 1;
1581 		uint32_t res1		: 2;
1582 		uint32_t an_complete	: 1;
1583 		uint32_t remote_fault	: 1;
1584 		uint32_t an_able	: 1;
1585 		uint32_t link_stat	: 1;
1586 		uint32_t jabber_detect	: 1;
1587 		uint32_t ext_cap	: 1;
1588 #elif defined(_BIT_FIELDS_LTOH)
1589 		uint32_t ext_cap	: 1;
1590 		uint32_t jabber_detect	: 1;
1591 		uint32_t link_stat	: 1;
1592 		uint32_t an_able	: 1;
1593 		uint32_t remote_fault	: 1;
1594 		uint32_t an_complete	: 1;
1595 		uint32_t res1		: 2;
1596 		uint32_t ext_stat	: 1;
1597 		uint32_t res0		: 23;
1598 #endif
1599 		} w0;
1600 
1601 #if defined(_LITTLE_ENDIAN)
1602 		uint32_t	w1;
1603 #endif
1604 	} bits;
1605 } pcs_stat_t;
1606 
1607 #define	PCS_MII_ADVERT_FD		0x0020	   /* advertise full duplex */
1608 #define	PCS_MII_ADVERT_HD		0x0040	   /* advertise half-duplex */
1609 #define	PCS_MII_ADVERT_SYM_PAUSE	0x0080	   /* advertise PAUSE sym */
1610 #define	PCS_MII_ADVERT_ASYM_PAUSE	0x0100	   /* advertises PAUSE asym */
1611 #define	PCS_MII_ADVERT_RF_MASK		0x3000	   /* remote fault */
1612 #define	PCS_MII_ADVERT_RF_SHIFT		12
1613 #define	PCS_MII_ADVERT_ACK		0x4000	   /* (ro) */
1614 #define	PCS_MII_ADVERT_NEXT_PAGE	0x8000	   /* (ro) forced 0x0 */
1615 
1616 #define	PCS_MII_LPA_FD			PCS_MII_ADVERT_FD
1617 #define	PCS_MII_LPA_HD			PCS_MII_ADVERT_HD
1618 #define	PCS_MII_LPA_SYM_PAUSE		PCS_MII_ADVERT_SYM_PAUSE
1619 #define	PCS_MII_LPA_ASYM_PAUSE		PCS_MII_ADVERT_ASYM_PAUSE
1620 #define	PCS_MII_LPA_RF_MASK		PCS_MII_ADVERT_RF_MASK
1621 #define	PCS_MII_LPA_RF_SHIFT		PCS_MII_ADVERT_RF_SHIFT
1622 #define	PCS_MII_LPA_ACK			PCS_MII_ADVERT_ACK
1623 #define	PCS_MII_LPA_NEXT_PAGE		PCS_MII_ADVERT_NEXT_PAGE
1624 
1625 typedef union _pcs_anar_t {
1626 	uint64_t value;
1627 
1628 	struct {
1629 #if defined(_BIG_ENDIAN)
1630 		uint32_t msw;	/* Most significant word */
1631 		uint32_t lsw;	/* Least significant word */
1632 #elif defined(_LITTLE_ENDIAN)
1633 		uint32_t lsw;	/* Least significant word */
1634 		uint32_t msw;	/* Most significant word */
1635 #endif
1636 	} val;
1637 	struct {
1638 #if defined(_BIG_ENDIAN)
1639 		uint32_t	w1;
1640 #endif
1641 		struct {
1642 #if defined(_BIT_FIELDS_HTOL)
1643 		uint32_t res0		: 16;
1644 		uint32_t next_page	: 1;
1645 		uint32_t ack		: 1;
1646 		uint32_t remote_fault	: 2;
1647 		uint32_t res1		: 3;
1648 		uint32_t asm_pause	: 1;
1649 		uint32_t pause		: 1;
1650 		uint32_t half_duplex	: 1;
1651 		uint32_t full_duplex	: 1;
1652 		uint32_t res2		: 5;
1653 #elif defined(_BIT_FIELDS_LTOH)
1654 		uint32_t res2		: 5;
1655 		uint32_t full_duplex	: 1;
1656 		uint32_t half_duplex	: 1;
1657 		uint32_t pause		: 1;
1658 		uint32_t asm_pause	: 1;
1659 		uint32_t res1		: 3;
1660 		uint32_t remore_fault	: 2;
1661 		uint32_t ack		: 1;
1662 		uint32_t next_page	: 1;
1663 		uint32_t res0		: 16;
1664 #endif
1665 		} w0;
1666 
1667 #if defined(_LITTLE_ENDIAN)
1668 		uint32_t	w1;
1669 #endif
1670 	} bits;
1671 } pcs_anar_t, *p_pcs_anar_t;
1672 
1673 #define	PCS_CFG_EN			0x0001	   /* enable PCS. */
1674 #define	PCS_CFG_SD_OVERRIDE		0x0002
1675 #define	PCS_CFG_SD_ACTIVE_LOW		0x0004	   /* sig detect active low */
1676 #define	PCS_CFG_JITTER_STUDY_MASK	0x0018	   /* jitter measurements */
1677 #define	PCS_CFG_JITTER_STUDY_SHIFT	4
1678 #define	PCS_CFG_10MS_TIMER_OVERRIDE	0x0020	   /* shortens autoneg timer */
1679 #define	PCS_CFG_MASK			0x0040	   /* PCS global mask bit */
1680 
1681 typedef union _pcs_cfg_t {
1682 	uint64_t value;
1683 
1684 	struct {
1685 #if defined(_BIG_ENDIAN)
1686 		uint32_t msw;	/* Most significant word */
1687 		uint32_t lsw;	/* Least significant word */
1688 #elif defined(_LITTLE_ENDIAN)
1689 		uint32_t lsw;	/* Least significant word */
1690 		uint32_t msw;	/* Most significant word */
1691 #endif
1692 	} val;
1693 	struct {
1694 #if defined(_BIG_ENDIAN)
1695 		uint32_t	w1;
1696 #endif
1697 		struct {
1698 #if defined(_BIT_FIELDS_HTOL)
1699 		uint32_t res0			: 25;
1700 		uint32_t mask			: 1;
1701 		uint32_t override_10ms_timer	: 1;
1702 		uint32_t jitter_study		: 2;
1703 		uint32_t sig_det_a_low		: 1;
1704 		uint32_t sig_det_override	: 1;
1705 		uint32_t enable			: 1;
1706 #elif defined(_BIT_FIELDS_LTOH)
1707 		uint32_t enable			: 1;
1708 		uint32_t sig_det_override	: 1;
1709 		uint32_t sig_det_a_low		: 1;
1710 		uint32_t jitter_study		: 2;
1711 		uint32_t override_10ms_timer	: 1;
1712 		uint32_t mask			: 1;
1713 		uint32_t res0			: 25;
1714 #endif
1715 		} w0;
1716 
1717 #if defined(_LITTLE_ENDIAN)
1718 		uint32_t	w1;
1719 #endif
1720 	} bits;
1721 } pcs_cfg_t, *p_pcs_cfg_t;
1722 
1723 
1724 /* used for diagnostic purposes. bits 20-22 autoclear on read */
1725 #define	PCS_SM_TX_STATE_MASK		0x0000000F /* Tx idle state mask */
1726 #define	PCS_SM_TX_STATE_SHIFT		0
1727 #define	PCS_SM_RX_STATE_MASK		0x000000F0 /* Rx idle state mask */
1728 #define	PCS_SM_RX_STATE_SHIFT		4
1729 #define	PCS_SM_WORD_SYNC_STATE_MASK	0x00000700 /* loss of sync state mask */
1730 #define	PCS_SM_WORD_SYNC_STATE_SHIFT	8
1731 #define	PCS_SM_SEQ_DETECT_STATE_MASK	0x00001800 /* sequence detect */
1732 #define	PCS_SM_SEQ_DETECT_STATE_SHIFT	11
1733 #define	PCS_SM_LINK_STATE_MASK		0x0001E000 /* link state */
1734 #define	PCS_SM_LINK_STATE_SHIFT		13
1735 #define	PCS_SM_LOSS_LINK_C		0x00100000 /* loss of link */
1736 #define	PCS_SM_LOSS_LINK_SYNC		0x00200000 /* loss of sync */
1737 #define	PCS_SM_LOSS_SIGNAL_DETECT	0x00400000 /* signal detect fail */
1738 #define	PCS_SM_NO_LINK_BREAKLINK	0x01000000 /* receipt of breaklink */
1739 #define	PCS_SM_NO_LINK_SERDES		0x02000000 /* serdes initializing */
1740 #define	PCS_SM_NO_LINK_C		0x04000000 /* C codes not stable */
1741 #define	PCS_SM_NO_LINK_SYNC		0x08000000 /* word sync not achieved */
1742 #define	PCS_SM_NO_LINK_WAIT_C		0x10000000 /* waiting for C codes */
1743 #define	PCS_SM_NO_LINK_NO_IDLE		0x20000000 /* linkpartner send C code */
1744 
1745 typedef union _pcs_stat_mc_t {
1746 	uint64_t value;
1747 
1748 	struct {
1749 #if defined(_BIG_ENDIAN)
1750 		uint32_t msw;	/* Most significant word */
1751 		uint32_t lsw;	/* Least significant word */
1752 #elif defined(_LITTLE_ENDIAN)
1753 		uint32_t lsw;	/* Least significant word */
1754 		uint32_t msw;	/* Most significant word */
1755 #endif
1756 	} val;
1757 	struct {
1758 #if defined(_BIG_ENDIAN)
1759 		uint32_t	w1;
1760 #endif
1761 		struct {
1762 #if defined(_BIT_FIELDS_HTOL)
1763 		uint32_t res2		: 2;
1764 		uint32_t lnk_dwn_ni	: 1;
1765 		uint32_t lnk_dwn_wc	: 1;
1766 		uint32_t lnk_dwn_ls	: 1;
1767 		uint32_t lnk_dwn_nc	: 1;
1768 		uint32_t lnk_dwn_ser	: 1;
1769 		uint32_t lnk_loss_bc	: 1;
1770 		uint32_t res1		: 1;
1771 		uint32_t loss_sd	: 1;
1772 		uint32_t lnk_loss_sync	: 1;
1773 		uint32_t lnk_loss_c	: 1;
1774 		uint32_t res0		: 3;
1775 		uint32_t link_cfg_stat	: 4;
1776 		uint32_t seq_detc_stat	: 2;
1777 		uint32_t word_sync	: 3;
1778 		uint32_t rx_ctrl	: 4;
1779 		uint32_t tx_ctrl	: 4;
1780 #elif defined(_BIT_FIELDS_LTOH)
1781 		uint32_t tx_ctrl	: 4;
1782 		uint32_t rx_ctrl	: 4;
1783 		uint32_t word_sync	: 3;
1784 		uint32_t seq_detc_stat	: 2;
1785 		uint32_t link_cfg_stat	: 4;
1786 		uint32_t res0		: 3;
1787 		uint32_t lnk_loss_c	: 1;
1788 		uint32_t lnk_loss_sync	: 1;
1789 		uint32_t loss_sd	: 1;
1790 		uint32_t res1		: 1;
1791 		uint32_t lnk_loss_bc	: 1;
1792 		uint32_t lnk_dwn_ser	: 1;
1793 		uint32_t lnk_dwn_nc	: 1;
1794 		uint32_t lnk_dwn_ls	: 1;
1795 		uint32_t lnk_dwn_wc	: 1;
1796 		uint32_t lnk_dwn_ni	: 1;
1797 		uint32_t res2		: 2;
1798 #endif
1799 		} w0;
1800 
1801 #if defined(_LITTLE_ENDIAN)
1802 		uint32_t	w1;
1803 #endif
1804 	} bits;
1805 } pcs_stat_mc_t, *p_pcs_stat_mc_t;
1806 
1807 #define	PCS_INTR_STATUS_LINK_CHANGE	0x04	/* link status has changed */
1808 
1809 /*
1810  * control which network interface is used. no more than one bit should
1811  * be set.
1812  */
1813 #define	PCS_DATAPATH_MODE_PCS		0	   /* Internal PCS is used */
1814 #define	PCS_DATAPATH_MODE_MII		0x00000002 /* GMII/RGMII is selected. */
1815 
1816 #define	PCS_PACKET_COUNT_TX_MASK	0x000007FF /* pkts xmitted by PCS */
1817 #define	PCS_PACKET_COUNT_RX_MASK	0x07FF0000 /* pkts recvd by PCS */
1818 #define	PCS_PACKET_COUNT_RX_SHIFT	16
1819 
1820 /*
1821  * ******************** XPCS registers *********************************
1822  */
1823 
1824 /* XPCS Base 10G Control1 Register */
1825 #define	XPCS_CTRL1_RST			0x8000 /* Self clearing reset. */
1826 #define	XPCS_CTRL1_LOOPBK		0x4000 /* xpcs Loopback */
1827 #define	XPCS_CTRL1_SPEED_SEL_3		0x2000 /* 1 indicates 10G speed */
1828 #define	XPCS_CTRL1_LOW_PWR		0x0800 /* low power mode. */
1829 #define	XPCS_CTRL1_SPEED_SEL_1		0x0040 /* 1 indicates 10G speed */
1830 #define	XPCS_CTRL1_SPEED_SEL_0_MASK	0x003c /* 0 indicates 10G speed. */
1831 #define	XPCS_CTRL1_SPEED_SEL_0_SHIFT	2
1832 
1833 
1834 
1835 typedef union _xpcs_ctrl1_t {
1836 	uint64_t value;
1837 
1838 	struct {
1839 #if defined(_BIG_ENDIAN)
1840 		uint32_t msw;	/* Most significant word */
1841 		uint32_t lsw;	/* Least significant word */
1842 #elif defined(_LITTLE_ENDIAN)
1843 		uint32_t lsw;	/* Least significant word */
1844 		uint32_t msw;	/* Most significant word */
1845 #endif
1846 	} val;
1847 	struct {
1848 #if defined(_BIG_ENDIAN)
1849 		uint32_t	w1;
1850 #endif
1851 		struct {
1852 #if defined(_BIT_FIELDS_HTOL)
1853 		uint32_t res3		: 16;
1854 		uint32_t reset		: 1;
1855 		uint32_t csr_lb		: 1;
1856 		uint32_t csr_speed_sel3	: 1;
1857 		uint32_t res2		: 1;
1858 		uint32_t csr_low_pwr	: 1;
1859 		uint32_t res1		: 4;
1860 		uint32_t csr_speed_sel1	: 1;
1861 		uint32_t csr_speed_sel0	: 4;
1862 		uint32_t res0		: 2;
1863 #elif defined(_BIT_FIELDS_LTOH)
1864 		uint32_t res0		: 2;
1865 		uint32_t csr_speed_sel0	: 4;
1866 		uint32_t csr_speed_sel1	: 1;
1867 		uint32_t res1		: 4;
1868 		uint32_t csr_low_pwr	: 1;
1869 		uint32_t res2		: 1;
1870 		uint32_t csr_speed_sel3	: 1;
1871 		uint32_t csr_lb		: 1;
1872 		uint32_t reset		: 1;
1873 		uint32_t res3		: 16;
1874 #endif
1875 		} w0;
1876 
1877 #if defined(_LITTLE_ENDIAN)
1878 		uint32_t	w1;
1879 #endif
1880 	} bits;
1881 } xpcs_ctrl1_t;
1882 
1883 
1884 /* XPCS Base 10G Status1 Register (Read Only) */
1885 #define	XPCS_STATUS1_FAULT		0x0080
1886 #define	XPCS_STATUS1_RX_LINK_STATUS_UP	0x0004 /* Link status interrupt */
1887 #define	XPCS_STATUS1_LOW_POWER_ABILITY	0x0002 /* low power mode */
1888 #define	XPCS_STATUS_RX_LINK_STATUS_UP	0x1000 /* Link status interrupt */
1889 
1890 
1891 typedef	union _xpcs_stat1_t {
1892 	uint64_t value;
1893 
1894 	struct {
1895 #if defined(_BIG_ENDIAN)
1896 		uint32_t msw;	/* Most significant word */
1897 		uint32_t lsw;	/* Least significant word */
1898 #elif defined(_LITTLE_ENDIAN)
1899 		uint32_t lsw;	/* Least significant word */
1900 		uint32_t msw;	/* Most significant word */
1901 #endif
1902 	} val;
1903 	struct {
1904 #if defined(_BIG_ENDIAN)
1905 		uint32_t	w1;
1906 #endif
1907 		struct {
1908 #if defined(_BIT_FIELDS_HTOL)
1909 		uint32_t res4			: 16;
1910 		uint32_t res3			: 8;
1911 		uint32_t csr_fault		: 1;
1912 		uint32_t res1			: 4;
1913 		uint32_t csr_rx_link_stat	: 1;
1914 		uint32_t csr_low_pwr_ability	: 1;
1915 		uint32_t res0			: 1;
1916 #elif defined(_BIT_FIELDS_LTOH)
1917 		uint32_t res0			: 1;
1918 		uint32_t csr_low_pwr_ability	: 1;
1919 		uint32_t csr_rx_link_stat	: 1;
1920 		uint32_t res1			: 4;
1921 		uint32_t csr_fault		: 1;
1922 		uint32_t res3			: 8;
1923 		uint32_t res4			: 16;
1924 #endif
1925 		} w0;
1926 
1927 #if defined(_LITTLE_ENDIAN)
1928 		uint32_t	w1;
1929 #endif
1930 	} bits;
1931 } xpcs_stat1_t;
1932 
1933 
1934 /* XPCS Base Speed Ability Register. Indicates 10G capability */
1935 #define	XPCS_SPEED_ABILITY_10_GIG	0x0001
1936 
1937 
1938 typedef	union _xpcs_speed_ab_t {
1939 	uint64_t value;
1940 
1941 	struct {
1942 #if defined(_BIG_ENDIAN)
1943 		uint32_t msw;	/* Most significant word */
1944 		uint32_t lsw;	/* Least significant word */
1945 #elif defined(_LITTLE_ENDIAN)
1946 		uint32_t lsw;	/* Least significant word */
1947 		uint32_t msw;	/* Most significant word */
1948 #endif
1949 	} val;
1950 	struct {
1951 #if defined(_BIG_ENDIAN)
1952 		uint32_t	w1;
1953 #endif
1954 		struct {
1955 #if defined(_BIT_FIELDS_HTOL)
1956 		uint32_t res1		: 16;
1957 		uint32_t res0		: 15;
1958 		uint32_t csr_10gig	: 1;
1959 #elif defined(_BIT_FIELDS_LTOH)
1960 		uint32_t csr_10gig	: 1;
1961 		uint32_t res0		: 15;
1962 		uint32_t res1		: 16;
1963 #endif
1964 		} w0;
1965 
1966 #if defined(_LITTLE_ENDIAN)
1967 		uint32_t	w1;
1968 #endif
1969 	} bits;
1970 } xpcs_speed_ab_t;
1971 
1972 
1973 /* XPCS Base 10G Devices in Package Register */
1974 #define	XPCS_DEV_IN_PKG_CSR_VENDOR2	0x80000000
1975 #define	XPCS_DEV_IN_PKG_CSR_VENDOR1	0x40000000
1976 #define	XPCS_DEV_IN_PKG_DTE_XS		0x00000020
1977 #define	XPCS_DEV_IN_PKG_PHY_XS		0x00000010
1978 #define	XPCS_DEV_IN_PKG_PCS		0x00000008
1979 #define	XPCS_DEV_IN_PKG_WIS		0x00000004
1980 #define	XPCS_DEV_IN_PKG_PMD_PMA		0x00000002
1981 #define	XPCS_DEV_IN_PKG_CLS_22_REG	0x00000000
1982 
1983 
1984 
1985 typedef	union _xpcs_dev_in_pkg_t {
1986 	uint64_t value;
1987 
1988 	struct {
1989 #if defined(_BIG_ENDIAN)
1990 		uint32_t msw;	/* Most significant word */
1991 		uint32_t lsw;	/* Least significant word */
1992 #elif defined(_LITTLE_ENDIAN)
1993 		uint32_t lsw;	/* Least significant word */
1994 		uint32_t msw;	/* Most significant word */
1995 #endif
1996 	} val;
1997 	struct {
1998 #if defined(_BIG_ENDIAN)
1999 		uint32_t	w1;
2000 #endif
2001 		struct {
2002 #if defined(_BIT_FIELDS_HTOL)
2003 		uint32_t csr_vendor2	: 1;
2004 		uint32_t csr_vendor1	: 1;
2005 		uint32_t res1		: 14;
2006 		uint32_t res0		: 10;
2007 		uint32_t dte_xs		: 1;
2008 		uint32_t phy_xs		: 1;
2009 		uint32_t pcs		: 1;
2010 		uint32_t wis		: 1;
2011 		uint32_t pmd_pma	: 1;
2012 		uint32_t clause_22_reg	: 1;
2013 #elif defined(_BIT_FIELDS_LTOH)
2014 		uint32_t clause_22_reg	: 1;
2015 		uint32_t pmd_pma	: 1;
2016 		uint32_t wis		: 1;
2017 		uint32_t pcs		: 1;
2018 		uint32_t phy_xs		: 1;
2019 		uint32_t dte_xs		: 1;
2020 		uint32_t res0		: 10;
2021 		uint32_t res1		: 14;
2022 		uint32_t csr_vendor1	: 1;
2023 		uint32_t csr_vendor2	: 1;
2024 #endif
2025 		} w0;
2026 
2027 #if defined(_LITTLE_ENDIAN)
2028 		uint32_t	w1;
2029 #endif
2030 	} bits;
2031 } xpcs_dev_in_pkg_t;
2032 
2033 
2034 /* XPCS Base 10G Control2 Register */
2035 #define	XPCS_PSC_SEL_MASK		0x0003
2036 #define	PSC_SEL_10G_BASE_X_PCS		0x0001
2037 
2038 
2039 typedef	union _xpcs_ctrl2_t {
2040 	uint64_t value;
2041 
2042 	struct {
2043 #if defined(_BIG_ENDIAN)
2044 		uint32_t msw;	/* Most significant word */
2045 		uint32_t lsw;	/* Least significant word */
2046 #elif defined(_LITTLE_ENDIAN)
2047 		uint32_t lsw;	/* Least significant word */
2048 		uint32_t msw;	/* Most significant word */
2049 #endif
2050 	} val;
2051 	struct {
2052 #if defined(_BIG_ENDIAN)
2053 		uint32_t	w1;
2054 #endif
2055 		struct {
2056 #if defined(_BIT_FIELDS_HTOL)
2057 		uint32_t res1		: 16;
2058 		uint32_t res0		: 14;
2059 		uint32_t csr_psc_sel	: 2;
2060 #elif defined(_BIT_FIELDS_LTOH)
2061 		uint32_t csr_psc_sel	: 2;
2062 		uint32_t res0		: 14;
2063 		uint32_t res1		: 16;
2064 #endif
2065 		} w0;
2066 
2067 #if defined(_LITTLE_ENDIAN)
2068 		uint32_t	w1;
2069 #endif
2070 	} bits;
2071 } xpcs_ctrl2_t;
2072 
2073 
2074 /* XPCS Base10G Status2 Register */
2075 #define	XPCS_STATUS2_DEV_PRESENT_MASK	0xc000	/* ?????? */
2076 #define	XPCS_STATUS2_TX_FAULT		0x0800	/* Fault on tx path */
2077 #define	XPCS_STATUS2_RX_FAULT		0x0400	/* Fault on rx path */
2078 #define	XPCS_STATUS2_TEN_GBASE_W	0x0004	/* 10G-Base-W */
2079 #define	XPCS_STATUS2_TEN_GBASE_X	0x0002	/* 10G-Base-X */
2080 #define	XPCS_STATUS2_TEN_GBASE_R	0x0001	/* 10G-Base-R */
2081 
2082 typedef	union _xpcs_stat2_t {
2083 	uint64_t value;
2084 
2085 	struct {
2086 #if defined(_BIG_ENDIAN)
2087 		uint32_t msw;	/* Most significant word */
2088 		uint32_t lsw;	/* Least significant word */
2089 #elif defined(_LITTLE_ENDIAN)
2090 		uint32_t lsw;	/* Least significant word */
2091 		uint32_t msw;	/* Most significant word */
2092 #endif
2093 	} val;
2094 	struct {
2095 #if defined(_BIG_ENDIAN)
2096 		uint32_t	w1;
2097 #endif
2098 		struct {
2099 #if defined(_BIT_FIELDS_HTOL)
2100 		uint32_t res2		: 16;
2101 		uint32_t csr_dev_pres	: 2;
2102 		uint32_t res1		: 2;
2103 		uint32_t csr_tx_fault	: 1;
2104 		uint32_t csr_rx_fault	: 1;
2105 		uint32_t res0		: 7;
2106 		uint32_t ten_gbase_w	: 1;
2107 		uint32_t ten_gbase_x	: 1;
2108 		uint32_t ten_gbase_r	: 1;
2109 #elif defined(_BIT_FIELDS_LTOH)
2110 		uint32_t ten_gbase_r	: 1;
2111 		uint32_t ten_gbase_x	: 1;
2112 		uint32_t ten_gbase_w	: 1;
2113 		uint32_t res0		: 7;
2114 		uint32_t csr_rx_fault	: 1;
2115 		uint32_t csr_tx_fault	: 1;
2116 		uint32_t res1		: 2;
2117 		uint32_t csr_dev_pres	: 2;
2118 		uint32_t res2		: 16;
2119 #endif
2120 		} w0;
2121 
2122 #if defined(_LITTLE_ENDIAN)
2123 		uint32_t	w1;
2124 #endif
2125 	} bits;
2126 } xpcs_stat2_t;
2127 
2128 
2129 
2130 /* XPCS Base10G Status Register */
2131 #define	XPCS_STATUS_LANE_ALIGN		0x1000 /* 10GBaseX PCS rx lanes align */
2132 #define	XPCS_STATUS_PATTERN_TEST_ABLE	0x0800 /* able to generate patterns. */
2133 #define	XPCS_STATUS_LANE3_SYNC		0x0008 /* Lane 3 is synchronized */
2134 #define	XPCS_STATUS_LANE2_SYNC		0x0004 /* Lane 2 is synchronized */
2135 #define	XPCS_STATUS_LANE1_SYNC		0x0002 /* Lane 1 is synchronized */
2136 #define	XPCS_STATUS_LANE0_SYNC		0x0001 /* Lane 0 is synchronized */
2137 
2138 typedef	union _xpcs_stat_t {
2139 	uint64_t value;
2140 
2141 	struct {
2142 #if defined(_BIG_ENDIAN)
2143 		uint32_t msw;	/* Most significant word */
2144 		uint32_t lsw;	/* Least significant word */
2145 #elif defined(_LITTLE_ENDIAN)
2146 		uint32_t lsw;	/* Least significant word */
2147 		uint32_t msw;	/* Most significant word */
2148 #endif
2149 	} val;
2150 	struct {
2151 #if defined(_BIG_ENDIAN)
2152 		uint32_t	w1;
2153 #endif
2154 		struct {
2155 #if defined(_BIT_FIELDS_HTOL)
2156 		uint32_t res2			: 16;
2157 		uint32_t res1			: 3;
2158 		uint32_t csr_lane_align		: 1;
2159 		uint32_t csr_pattern_test_able	: 1;
2160 		uint32_t res0			: 7;
2161 		uint32_t csr_lane3_sync		: 1;
2162 		uint32_t csr_lane2_sync		: 1;
2163 		uint32_t csr_lane1_sync		: 1;
2164 		uint32_t csr_lane0_sync		: 1;
2165 #elif defined(_BIT_FIELDS_LTOH)
2166 		uint32_t csr_lane0_sync		: 1;
2167 		uint32_t csr_lane1_sync		: 1;
2168 		uint32_t csr_lane2_sync		: 1;
2169 		uint32_t csr_lane3_sync		: 1;
2170 		uint32_t res0			: 7;
2171 		uint32_t csr_pat_test_able	: 1;
2172 		uint32_t csr_lane_align		: 1;
2173 		uint32_t res1			: 3;
2174 		uint32_t res2			: 16;
2175 #endif
2176 		} w0;
2177 
2178 #if defined(_LITTLE_ENDIAN)
2179 		uint32_t	w1;
2180 #endif
2181 	} bits;
2182 } xpcs_stat_t;
2183 
2184 /* XPCS Base10G Test Control Register */
2185 #define	XPCS_TEST_CTRL_TX_TEST_ENABLE		0x0004
2186 #define	XPCS_TEST_CTRL_TEST_PATTERN_SEL_MASK	0x0003
2187 #define	TEST_PATTERN_HIGH_FREQ			0
2188 #define	TEST_PATTERN_LOW_FREQ			1
2189 #define	TEST_PATTERN_MIXED_FREQ			2
2190 
2191 typedef	union _xpcs_test_ctl_t {
2192 	uint64_t value;
2193 
2194 	struct {
2195 #if defined(_BIG_ENDIAN)
2196 		uint32_t msw;	/* Most significant word */
2197 		uint32_t lsw;	/* Least significant word */
2198 #elif defined(_LITTLE_ENDIAN)
2199 		uint32_t lsw;	/* Least significant word */
2200 		uint32_t msw;	/* Most significant word */
2201 #endif
2202 	} val;
2203 	struct {
2204 #if defined(_BIG_ENDIAN)
2205 		uint32_t	w1;
2206 #endif
2207 		struct {
2208 #if defined(_BIT_FIELDS_HTOL)
2209 		uint32_t res1			: 16;
2210 		uint32_t res0			: 13;
2211 		uint32_t csr_tx_test_en		: 1;
2212 		uint32_t csr_test_pat_sel	: 2;
2213 #elif defined(_BIT_FIELDS_LTOH)
2214 		uint32_t csr_test_pat_sel	: 2;
2215 		uint32_t csr_tx_test_en		: 1;
2216 		uint32_t res0			: 13;
2217 		uint32_t res1			: 16;
2218 #endif
2219 		} w0;
2220 
2221 #if defined(_LITTLE_ENDIAN)
2222 		uint32_t	w1;
2223 #endif
2224 	} bits;
2225 } xpcs_test_ctl_t;
2226 
2227 /* XPCS Base10G Diagnostic Register */
2228 #define	XPCS_DIAG_EB_ALIGN_ERR3		0x40
2229 #define	XPCS_DIAG_EB_ALIGN_ERR2		0x20
2230 #define	XPCS_DIAG_EB_ALIGN_ERR1		0x10
2231 #define	XPCS_DIAG_EB_DESKEW_OK		0x08
2232 #define	XPCS_DIAG_EB_ALIGN_DET3		0x04
2233 #define	XPCS_DIAG_EB_ALIGN_DET2		0x02
2234 #define	XPCS_DIAG_EB_ALIGN_DET1		0x01
2235 #define	XPCS_DIAG_EB_DESKEW_LOSS	0
2236 
2237 #define	XPCS_DIAG_SYNC_3_INVALID	0x8
2238 #define	XPCS_DIAG_SYNC_2_INVALID	0x4
2239 #define	XPCS_DIAG_SYNC_1_INVALID	0x2
2240 #define	XPCS_DIAG_SYNC_IN_SYNC		0x1
2241 #define	XPCS_DIAG_SYNC_LOSS_SYNC	0
2242 
2243 #define	XPCS_RX_SM_RECEIVE_STATE	1
2244 #define	XPCS_RX_SM_FAULT_STATE		0
2245 
2246 typedef	union _xpcs_diag_t {
2247 	uint64_t value;
2248 
2249 	struct {
2250 #if defined(_BIG_ENDIAN)
2251 		uint32_t msw;	/* Most significant word */
2252 		uint32_t lsw;	/* Least significant word */
2253 #elif defined(_LITTLE_ENDIAN)
2254 		uint32_t lsw;	/* Least significant word */
2255 		uint32_t msw;	/* Most significant word */
2256 #endif
2257 	} val;
2258 	struct {
2259 #if defined(_BIG_ENDIAN)
2260 		uint32_t	w1;
2261 #endif
2262 		struct {
2263 #if defined(_BIT_FIELDS_HTOL)
2264 		uint32_t res1			: 7;
2265 		uint32_t sync_sm_lane3		: 4;
2266 		uint32_t sync_sm_lane2		: 4;
2267 		uint32_t sync_sm_lane1		: 4;
2268 		uint32_t sync_sm_lane0		: 4;
2269 		uint32_t elastic_buffer_sm	: 8;
2270 		uint32_t receive_sm		: 1;
2271 #elif defined(_BIT_FIELDS_LTOH)
2272 		uint32_t receive_sm		: 1;
2273 		uint32_t elastic_buffer_sm	: 8;
2274 		uint32_t sync_sm_lane0		: 4;
2275 		uint32_t sync_sm_lane1		: 4;
2276 		uint32_t sync_sm_lane2		: 4;
2277 		uint32_t sync_sm_lane3		: 4;
2278 		uint32_t res1			: 7;
2279 #endif
2280 		} w0;
2281 
2282 #if defined(_LITTLE_ENDIAN)
2283 		uint32_t	w1;
2284 #endif
2285 	} bits;
2286 } xpcs_diag_t;
2287 
2288 /* XPCS Base10G Tx State Machine Register */
2289 #define	XPCS_TX_SM_SEND_UNDERRUN	0x9
2290 #define	XPCS_TX_SM_SEND_RANDOM_Q	0x8
2291 #define	XPCS_TX_SM_SEND_RANDOM_K	0x7
2292 #define	XPCS_TX_SM_SEND_RANDOM_A	0x6
2293 #define	XPCS_TX_SM_SEND_RANDOM_R	0x5
2294 #define	XPCS_TX_SM_SEND_Q		0x4
2295 #define	XPCS_TX_SM_SEND_K		0x3
2296 #define	XPCS_TX_SM_SEND_A		0x2
2297 #define	XPCS_TX_SM_SEND_SDP		0x1
2298 #define	XPCS_TX_SM_SEND_DATA		0
2299 
2300 /* XPCS Base10G Configuration Register */
2301 #define	XPCS_CFG_VENDOR_DBG_SEL_MASK	0x78
2302 #define	XPCS_CFG_VENDOR_DBG_SEL_SHIFT	3
2303 #define	XPCS_CFG_BYPASS_SIG_DETECT	0x0004
2304 #define	XPCS_CFG_ENABLE_TX_BUFFERS	0x0002
2305 #define	XPCS_CFG_XPCS_ENABLE		0x0001
2306 
2307 typedef	union _xpcs_config_t {
2308 	uint64_t value;
2309 
2310 	struct {
2311 #if defined(_BIG_ENDIAN)
2312 		uint32_t msw;	/* Most significant word */
2313 		uint32_t lsw;	/* Least significant word */
2314 #elif defined(_LITTLE_ENDIAN)
2315 		uint32_t lsw;	/* Least significant word */
2316 		uint32_t msw;	/* Most significant word */
2317 #endif
2318 	} val;
2319 	struct {
2320 #if defined(_BIG_ENDIAN)
2321 		uint32_t	w1;
2322 #endif
2323 		struct {
2324 #if defined(_BIT_FIELDS_HTOL)
2325 		uint32_t res1			: 16;
2326 		uint32_t res0			: 9;
2327 		uint32_t csr_vendor_dbg_sel	: 4;
2328 		uint32_t csr_bypass_sig_detect	: 1;
2329 		uint32_t csr_en_tx_buf		: 1;
2330 		uint32_t csr_xpcs_en		: 1;
2331 #elif defined(_BIT_FIELDS_LTOH)
2332 		uint32_t csr_xpcs_en		: 1;
2333 		uint32_t csr_en_tx_buf		: 1;
2334 		uint32_t csr_bypass_sig_detect	: 1;
2335 		uint32_t csr_vendor_dbg_sel	: 4;
2336 		uint32_t res0			: 9;
2337 		uint32_t res1			: 16;
2338 #endif
2339 		} w0;
2340 
2341 #if defined(_LITTLE_ENDIAN)
2342 		uint32_t	w1;
2343 #endif
2344 	} bits;
2345 } xpcs_config_t;
2346 
2347 
2348 
2349 /* XPCS Base10G Mask1 Register */
2350 #define	XPCS_MASK1_FAULT_MASK		0x0080	/* mask fault interrupt. */
2351 #define	XPCS_MASK1_RX_LINK_STATUS_MASK	0x0040	/* mask linkstat interrupt */
2352 
2353 /* XPCS Base10G Packet Counter */
2354 #define	XPCS_PKT_CNTR_TX_PKT_CNT_MASK	0xffff0000
2355 #define	XPCS_PKT_CNTR_TX_PKT_CNT_SHIFT	16
2356 #define	XPCS_PKT_CNTR_RX_PKT_CNT_MASK	0x0000ffff
2357 #define	XPCS_PKT_CNTR_RX_PKT_CNT_SHIFT	0
2358 
2359 /* XPCS Base10G TX State Machine status register */
2360 #define	XPCS_TX_STATE_MC_TX_STATE_MASK	0x0f
2361 #define	XPCS_DESKEW_ERR_CNTR_MASK	0xff
2362 
2363 /* XPCS Base10G Lane symbol error counters */
2364 #define	XPCS_SYM_ERR_CNT_L1_MASK  0xffff0000
2365 #define	XPCS_SYM_ERR_CNT_L0_MASK  0x0000ffff
2366 #define	XPCS_SYM_ERR_CNT_L3_MASK  0xffff0000
2367 #define	XPCS_SYM_ERR_CNT_L2_MASK  0x0000ffff
2368 
2369 #define	XPCS_SYM_ERR_CNT_MULTIPLIER	16
2370 
2371 /* ESR Reset Register */
2372 #define	ESR_RESET_1			2
2373 #define	ESR_RESET_0			1
2374 
2375 /* ESR Configuration Register */
2376 #define	ESR_BLUNT_END_LOOPBACK		2
2377 #define	ESR_FORCE_SERDES_SERDES_RDY	1
2378 
2379 /* ESR Neptune Serdes PLL Configuration */
2380 #define	ESR_PLL_CFG_FBDIV_0		0x1
2381 #define	ESR_PLL_CFG_FBDIV_1		0x2
2382 #define	ESR_PLL_CFG_FBDIV_2		0x4
2383 #define	ESR_PLL_CFG_HALF_RATE_0		0x8
2384 #define	ESR_PLL_CFG_HALF_RATE_1		0x10
2385 #define	ESR_PLL_CFG_HALF_RATE_2		0x20
2386 #define	ESR_PLL_CFG_HALF_RATE_3		0x40
2387 #define	ESR_PLL_CFG_1G_SERDES		(ESR_PLL_CFG_FBDIV_0 |		\
2388 					ESR_PLL_CFG_HALF_RATE_0 |	\
2389 					ESR_PLL_CFG_HALF_RATE_1 |	\
2390 					ESR_PLL_CFG_HALF_RATE_2 |	\
2391 					ESR_PLL_CFG_HALF_RATE_3)
2392 
2393 #define	ESR_PLL_CFG_10G_SERDES		ESR_PLL_CFG_FBDIV_2
2394 
2395 /* ESR Neptune Serdes Control Register */
2396 #define	ESR_CTL_EN_SYNCDET_0		0x00000001
2397 #define	ESR_CTL_EN_SYNCDET_1		0x00000002
2398 #define	ESR_CTL_EN_SYNCDET_2		0x00000004
2399 #define	ESR_CTL_EN_SYNCDET_3		0x00000008
2400 #define	ESR_CTL_OUT_EMPH_0_MASK		0x00000070
2401 #define	ESR_CTL_OUT_EMPH_0_SHIFT	4
2402 #define	ESR_CTL_OUT_EMPH_1_MASK		0x00000380
2403 #define	ESR_CTL_OUT_EMPH_1_SHIFT	7
2404 #define	ESR_CTL_OUT_EMPH_2_MASK		0x00001c00
2405 #define	ESR_CTL_OUT_EMPH_2_SHIFT	10
2406 #define	ESR_CTL_OUT_EMPH_3_MASK		0x0000e000
2407 #define	ESR_CTL_OUT_EMPH_3_SHIFT	13
2408 #define	ESR_CTL_LOSADJ_0_MASK		0x00070000
2409 #define	ESR_CTL_LOSADJ_0_SHIFT		16
2410 #define	ESR_CTL_LOSADJ_1_MASK		0x00380000
2411 #define	ESR_CTL_LOSADJ_1_SHIFT		19
2412 #define	ESR_CTL_LOSADJ_2_MASK		0x01c00000
2413 #define	ESR_CTL_LOSADJ_2_SHIFT		22
2414 #define	ESR_CTL_LOSADJ_3_MASK		0x0e000000
2415 #define	ESR_CTL_LOSADJ_3_SHIFT		25
2416 #define	ESR_CTL_RXITERM_0		0x10000000
2417 #define	ESR_CTL_RXITERM_1		0x20000000
2418 #define	ESR_CTL_RXITERM_2		0x40000000
2419 #define	ESR_CTL_RXITERM_3		0x80000000
2420 #define	ESR_CTL_1G_SERDES		(ESR_CTL_EN_SYNCDET_0 | \
2421 					ESR_CTL_EN_SYNCDET_1 |	\
2422 					ESR_CTL_EN_SYNCDET_2 |	\
2423 					ESR_CTL_EN_SYNCDET_3 |  \
2424 					(0x1 << ESR_CTL_OUT_EMPH_0_SHIFT) | \
2425 					(0x1 << ESR_CTL_OUT_EMPH_1_SHIFT) | \
2426 					(0x1 << ESR_CTL_OUT_EMPH_2_SHIFT) | \
2427 					(0x1 << ESR_CTL_OUT_EMPH_3_SHIFT) | \
2428 					(0x1 << ESR_CTL_OUT_EMPH_3_SHIFT) | \
2429 					(0x1 << ESR_CTL_LOSADJ_0_SHIFT) | \
2430 					(0x1 << ESR_CTL_LOSADJ_1_SHIFT) | \
2431 					(0x1 << ESR_CTL_LOSADJ_2_SHIFT) | \
2432 					(0x1 << ESR_CTL_LOSADJ_3_SHIFT))
2433 
2434 /* ESR Neptune Serdes Test Configuration Register */
2435 #define	ESR_TSTCFG_LBTEST_MD_0_MASK	0x00000003
2436 #define	ESR_TSTCFG_LBTEST_MD_0_SHIFT	0
2437 #define	ESR_TSTCFG_LBTEST_MD_1_MASK	0x0000000c
2438 #define	ESR_TSTCFG_LBTEST_MD_1_SHIFT	2
2439 #define	ESR_TSTCFG_LBTEST_MD_2_MASK	0x00000030
2440 #define	ESR_TSTCFG_LBTEST_MD_2_SHIFT	4
2441 #define	ESR_TSTCFG_LBTEST_MD_3_MASK	0x000000c0
2442 #define	ESR_TSTCFG_LBTEST_MD_3_SHIFT	6
2443 #define	ESR_TSTCFG_LBTEST_PAD		(ESR_PAD_LOOPBACK_CH3 | \
2444 					ESR_PAD_LOOPBACK_CH2 | \
2445 					ESR_PAD_LOOPBACK_CH1 | \
2446 					ESR_PAD_LOOPBACK_CH0)
2447 
2448 /* ESR Neptune Ethernet RGMII Configuration Register */
2449 #define	ESR_RGMII_PT0_IN_USE		0x00000001
2450 #define	ESR_RGMII_PT1_IN_USE		0x00000002
2451 #define	ESR_RGMII_PT2_IN_USE		0x00000004
2452 #define	ESR_RGMII_PT3_IN_USE		0x00000008
2453 #define	ESR_RGMII_REG_RW_TEST		0x00000010
2454 
2455 /* ESR Internal Signals Observation Register */
2456 #define	ESR_SIG_MASK			0xFFFFFFFF
2457 #define	ESR_SIG_P0_BITS_MASK		0x33E0000F
2458 #define	ESR_SIG_P1_BITS_MASK		0x0C1F00F0
2459 #define	ESR_SIG_SERDES_RDY0_P0		0x20000000
2460 #define	ESR_SIG_DETECT0_P0		0x10000000
2461 #define	ESR_SIG_SERDES_RDY0_P1		0x08000000
2462 #define	ESR_SIG_DETECT0_P1		0x04000000
2463 #define	ESR_SIG_XSERDES_RDY_P0		0x02000000
2464 #define	ESR_SIG_XDETECT_P0_CH3		0x01000000
2465 #define	ESR_SIG_XDETECT_P0_CH2		0x00800000
2466 #define	ESR_SIG_XDETECT_P0_CH1		0x00400000
2467 #define	ESR_SIG_XDETECT_P0_CH0		0x00200000
2468 #define	ESR_SIG_XSERDES_RDY_P1		0x00100000
2469 #define	ESR_SIG_XDETECT_P1_CH3		0x00080000
2470 #define	ESR_SIG_XDETECT_P1_CH2		0x00040000
2471 #define	ESR_SIG_XDETECT_P1_CH1		0x00020000
2472 #define	ESR_SIG_XDETECT_P1_CH0		0x00010000
2473 #define	ESR_SIG_LOS_P1_CH3		0x00000080
2474 #define	ESR_SIG_LOS_P1_CH2		0x00000040
2475 #define	ESR_SIG_LOS_P1_CH1		0x00000020
2476 #define	ESR_SIG_LOS_P1_CH0		0x00000010
2477 #define	ESR_SIG_LOS_P0_CH3		0x00000008
2478 #define	ESR_SIG_LOS_P0_CH2		0x00000004
2479 #define	ESR_SIG_LOS_P0_CH1		0x00000002
2480 #define	ESR_SIG_LOS_P0_CH0		0x00000001
2481 #define	ESR_SIG_P0_BITS_MASK_1G		(ESR_SIG_SERDES_RDY0_P0 | \
2482 					ESR_SIG_DETECT0_P0)
2483 #define	ESR_SIG_P1_BITS_MASK_1G		(ESR_SIG_SERDES_RDY0_P1 | \
2484 					ESR_SIG_DETECT0_P1)
2485 
2486 /* ESR Debug Selection Register */
2487 #define	ESR_DEBUG_SEL_MASK		0x00000003f
2488 
2489 /* ESR Test Configuration Register */
2490 #define	ESR_NO_LOOPBACK_CH3		(0x0 << 6)
2491 #define	ESR_EWRAP_CH3			(0x1 << 6)
2492 #define	ESR_PAD_LOOPBACK_CH3		(0x2 << 6)
2493 #define	ESR_REVLOOPBACK_CH3		(0x3 << 6)
2494 #define	ESR_NO_LOOPBACK_CH2		(0x0 << 4)
2495 #define	ESR_EWRAP_CH2			(0x1 << 4)
2496 #define	ESR_PAD_LOOPBACK_CH2		(0x2 << 4)
2497 #define	ESR_REVLOOPBACK_CH2		(0x3 << 4)
2498 #define	ESR_NO_LOOPBACK_CH1		(0x0 << 2)
2499 #define	ESR_EWRAP_CH1			(0x1 << 2)
2500 #define	ESR_PAD_LOOPBACK_CH1		(0x2 << 2)
2501 #define	ESR_REVLOOPBACK_CH1		(0x3 << 2)
2502 #define	ESR_NO_LOOPBACK_CH0		0x0
2503 #define	ESR_EWRAP_CH0			0x1
2504 #define	ESR_PAD_LOOPBACK_CH0		0x2
2505 #define	ESR_REVLOOPBACK_CH0		0x3
2506 
2507 /* convert values */
2508 #define	NXGE_BASE(x, y)	\
2509 	(((y) << (x ## _SHIFT)) & (x ## _MASK))
2510 
2511 #define	NXGE_VAL_GET(fieldname, regval)		\
2512 	(((regval) & ((fieldname) ## _MASK)) >> ((fieldname) ## _SHIFT))
2513 
2514 #define	NXGE_VAL_SET(fieldname, regval, val)		\
2515 {							\
2516 	(regval) &= ~((fieldname) ## _MASK);		\
2517 	(regval) |= ((val) << (fieldname ## _SHIFT)); 	\
2518 }
2519 
2520 
2521 #ifdef	__cplusplus
2522 }
2523 #endif
2524 
2525 #endif	/* _SYS_MAC_NXGE_MAC_HW_H */
2526