xref: /illumos-gate/usr/src/uts/common/io/sfe/sfereg.h (revision 915ebf8d)
1 /*
2  *  sfereg.h: SiS900/DP83815 register definition
3  *
4  * Copyright (c) 2002-2007 Masayuki Murayama.  All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions are met:
8  *
9  * 1. Redistributions of source code must retain the above copyright notice,
10  *    this list of conditions and the following disclaimer.
11  *
12  * 2. Redistributions in binary form must reproduce the above copyright notice,
13  *    this list of conditions and the following disclaimer in the documentation
14  *    and/or other materials provided with the distribution.
15  *
16  * 3. Neither the name of the author nor the names of its contributors may be
17  *    used to endorse or promote products derived from this software without
18  *    specific prior written permission.
19  *
20  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
22  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
23  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
24  * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
25  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
26  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
27  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
28  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
29  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
30  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
31  * DAMAGE.
32  */
33 
34 #ifndef	_SFEREG_H_
35 #define	_SFEREG_H_
36 /*
37  * Tx/Rx descriptor
38  */
39 struct sfe_desc {
40 	volatile uint32_t	d_link;		/* link to the next */
41 	volatile uint32_t	d_cmdsts;	/* command/status field */
42 	volatile uint32_t	d_bufptr;	/* ptr to the first fragment */
43 };
44 
45 /* CMDSTS common Bit Definition */
46 #define	CMDSTS_OWN	0x80000000U	/* 1: data consumer owns */
47 #define	CMDSTS_MORE	0x40000000U	/* Not the last descriptor */
48 #define	CMDSTS_INTR	0x20000000U
49 #define	CMDSTS_SUPCRC	0x10000000U
50 #define	CMDSTS_INCCRC	CMDSTS_SUPCRC
51 #define	CMDSTS_OK	0x08000000U	/* Packet is OK */
52 #define	CMDSTS_SIZE	0x00000fffU	/* Descriptor byte count */
53 
54 /* Transmit Status Bit Definition */
55 #define	CMDSTS_TXA	0x04000000U	/* Transmit abort */
56 #define	CMDSTS_TFU	0x02000000U	/* Transmit FIFO Underrun */
57 #define	CMDSTS_CRS	0x01000000U	/* Carrier sense lost */
58 #define	CMDSTS_TD	0x00800000U	/* Transmit deferred */
59 #define	CMDSTS_ED	0x00400000U	/* Exessive deferrral */
60 #define	CMDSTS_OWC	0x00200000U	/* Out of window collision */
61 #define	CMDSTS_EC	0x00100000U	/* Excessive collision */
62 #define	CMDSTS_CCNT	0x000f0000U	/* Collision count */
63 #define	CMDSTS_CCNT_SHIFT	(16)
64 #define		CCNT_MASK	0xfU	/* Collision count mask */
65 
66 #define	TXSTAT_BITS	\
67 	"\020"		\
68 	"\040Own"	\
69 	"\037More"	\
70 	"\036Intr"	\
71 	"\035SupCrc"	\
72 	"\034Ok"	\
73 	"\033Abort"	\
74 	"\032UnderRun"	\
75 	"\031NoCarrier"	\
76 	"\030Deferd"	\
77 	"\027ExcDefer"	\
78 	"\026OWColl"	\
79 	"\025ExcColl"
80 
81 #define	RXSTAT_BITS	\
82 	"\020"		\
83 	"\040Own"	\
84 	"\037More"	\
85 	"\036Intr"	\
86 	"\035IncCrc"	\
87 	"\034Ok"	\
88 	"\032OverRun"	\
89 	"\031MCast"	\
90 	"\030UniMatch"	\
91 	"\027TooLong"	\
92 	"\026Runt"	\
93 	"\025RxISErr"	\
94 	"\024CrcErr"	\
95 	"\023FaErr"	\
96 	"\022LoopBk"	\
97 	"\021RxCol"
98 
99 
100 /* Receive Status Bit Definitions */
101 #define	CMDSTS_RXA	0x04000000U	/* Receive abort */
102 #define	CMDSTS_RXO	0x02000000U	/* Receive overrun */
103 #define	CMDSTS_DEST	0x01800000U	/* Destination class */
104 #define	CMDSTS_DEST_SHIFT	23	/* Destination class */
105 #define		DEST_REJECT	0U
106 #define		DEST_NODE	1U
107 #define		DEST_MULTI	2U
108 #define		DEST_BROAD	3U
109 #define	CMDSTS_LONG	0x00400000U	/* Too long packet received */
110 #define	CMDSTS_RUNT	0x00200000U	/* Runt packet received */
111 #define	CMDSTS_ISE	0x00100000U	/* Invalid symbol error */
112 #define	CMDSTS_CRCE	0x00080000U	/* CRC error */
113 #define	CMDSTS_FAE	0x00040000U	/* Frame alignment */
114 #define	CMDSTS_LBP	0x00020000U	/* Loopback packet */
115 #define	CMDSTS_COL	0x00010000U	/* Collision activety */
116 
117 /*
118  * Offsets of MAC Operational Registers
119  */
120 #define	CR		0x00	/* Command register */
121 #define	CFG		0x04	/* Configuration register */
122 #define	EROMAR		0x08	/* EEPROM access register */
123 #define	MEAR		0x08	/* alias for MII access register (sis900) */
124 #define	PTSCR		0x0c	/* PCI test control register */
125 #define	ISR		0x10	/* Interrupt status register */
126 #define	IMR		0x14	/* Interrupt mask register */
127 #define	IER		0x18	/* Interrupt enable register */
128 #define	ENPHY		0x1c	/* Enhanced PHY access register */
129 #define	TXDP		0x20	/* Transmit descriptor pointer reg */
130 #define	TXCFG		0x24	/* Transmit configuration register */
131 #define	RXDP		0x30	/* Receive descriptor pointer reg */
132 #define	RXCFG		0x34	/* Receive configration register */
133 #define	FLOWCTL		0x38	/* Flow control register (sis900) */
134 #define	CCSR		0x3c	/* Clock run status register (dp83815) */
135 #define	PCR		0x44	/* Pause control register (dp83815) */
136 #define	RFCR		0x48	/* Receive filter control register */
137 #define	RFDR		0x4c	/* Receive filter data register */
138 #define	SRR		0x58	/* silicon revision register */
139 #define	MII_REGS_BASE	0x80	/* DP83815 only */
140 #define	PMCTL		0xb0	/* Power management control register */
141 #define	PMEVT		0xb4	/* Power management wake-up event reg */
142 #define	WAKECRC		0xbc	/* Wake-up sample frame CRC register */
143 #define	WAKEMASK	0xc0	/* Wake-up sample frame mask register */
144 
145 
146 /* Command register */
147 #define	CR_RELOAD	0x0400U		/* reload mac address */
148 #define	CR_ACCESSMODE	0x0200U		/* mii access mode */
149 #define	CR_RST		0x0100U		/* Reset */
150 #define	CR_SWI		0x0080U		/* Software interrupt */
151 #define	CR_RXR		0x0020U		/* Receiver reset */
152 #define	CR_TXR		0x0010U		/* Transmit reset */
153 #define	CR_RXD		0x0008U		/* Receiver disable */
154 #define	CR_RXE		0x0004U		/* Receiver enable */
155 #define	CR_TXD		0x0002U		/* Transmit disable */
156 #define	CR_TXE		0x0001U		/* Transmit enable */
157 
158 #define	CR_BITS	\
159 	"\020"		\
160 	"\011Reset"	\
161 	"\010SWI"	\
162 	"\006RxReset"	\
163 	"\005TxReset"	\
164 	"\004RxDisable"	\
165 	"\003RxEnable"	\
166 	"\002TxDisable"	\
167 	"\001TxEnable"
168 
169 /* Configration register */
170 #define	CFG_LNKSTS	0x80000000U	/* Link up (83815) */
171 #define	CFG_SPEED100	0x40000000U	/* 100Mbps (83815) */
172 #define	CFG_FDUP	0x20000000U	/* full duplex (83815) */
173 #define	CFG_POL		0x10000000U	/* 10Mbps polarity indication (83815) */
174 #define	CFG_ANEG_DN	0x08000000U	/* auto negotiation done (83815) */
175 #define	CFG_PHY_CFG	0x00fc0000U	/* internal PHY configuration (83815) */
176 #define	CFG_PINT_ACEN	0x00020000U	/* PHY interrupt auto clear (83815) */
177 #define	CFG_PAUSE_ADV	0x00010000U	/* Advertise pause (83815) */
178 #define	CFG_ANEG_SEL	0x0000e000U	/* Auto-nego default (83815) */
179 #define	CFG_EDB_MASTER	0x00002000U	/* sis635, sis900B, sis96x */
180 #define	CFG_EXT_PHY	0x00001000U	/* External PHY support (83815) */
181 #define	CFG_PHY_RST	0x00000400U	/* Internal PHY reset (83815) */
182 #define	CFG_RND_CNT	0x00000400U	/* sis635 & 900B */
183 #define	CFG_PHY_DIS	0x00000200U	/* Internal PHY disable (83815) */
184 #define	CFG_FAIR_BCKOFF	0x00000200U	/* sis635 & 900B */
185 #define	CFG_EUPHCOMP	0x00000100U	/* DP83810 compatibility (83815) */
186 #define	CFG_DESCRFMT	0x00000100U	/* sis7016 */
187 #define	CFG_REQALG	0x00000080U	/* PCI Bus request algorithm */
188 #define	CFG_SB		0x00000040U	/* Single backoff */
189 #define	CFG_POW		0x00000020U	/* Program out of window timer */
190 #define	CFG_EXD		0x00000010U	/* Excessive deferral timer disable */
191 #define	CFG_PESEL	0x00000008U	/* Parity error detection action */
192 #define	CFG_BROM_DIS	0x00000004U	/* BootRom disable (83815) */
193 #define	CFG_BEM		0x00000001U	/* Big endian mode */
194 
195 #define	CFG_BITS_DP83815	\
196 	"\020"	\
197 	"\040CFG_LNKSTS"	\
198 	"\037SPEED100"	\
199 	"\036FDUP"	\
200 	"\035POL"	\
201 	"\034ANEG_DN"	\
202 	"\022PINT_ACEN"	\
203 	"\021PAUSE_ADV"	\
204 	"\015EXT_PHY"	\
205 	"\013PHY_RST"	\
206 	"\012PHY_DIS"	\
207 	"\011EUPHCOMP"	\
208 	"\010REQALG"	\
209 	"\007SB"	\
210 	"\006POW"	\
211 	"\005EXD"	\
212 	"\004PESEL"	\
213 	"\003BROM_DIS"	\
214 	"\001BEM"
215 
216 #define	CFG_BITS_SIS900	\
217 	"\020"	\
218 	"\016EDB_EN"	\
219 	"\013RND_CNT"	\
220 	"\010REQALG"	\
221 	"\007SB"	\
222 	"\006POW"	\
223 	"\005EXD"	\
224 	"\004PESEL"	\
225 	"\001BEM"
226 
227 /* Serial EEPROM access register */
228 #define	EROMAR_EECS	0x00000008U	/* EEPROM chip select */
229 #define	EROMAR_EESK	0x00000004U	/* EEPROM serial clock */
230 #define	EROMAR_EEDO	0x00000002U	/* EEPROM data out */
231 #define	EROMAR_EEDO_SHIFT	1
232 #define	EROMAR_EEDI	0x00000001U	/* EEPROM data in + */
233 #define	EROMAR_EEDI_SHIFT	0
234 #define	EROMAR_EEREQ	0x00000400U	/* for sis963 eeprom mamagement */
235 #define	EROMAR_EEDONE	0x00000200U	/* for sis963 eeprom mamagement */
236 #define	EROMAR_EEGNT	0x00000100U	/* for sis963 eeprom mamagement */
237 
238 #define	MEAR_MDC	0x00000040U
239 #define	MEAR_MDDIR	0x00000020U
240 #define	MEAR_MDIO	0x00000010U
241 #define	MEAR_MDIO_SHIFT	4
242 
243 /* PCI Test Control register */
244 #define	DISCARD_TEST	0x40000000U	/* Discard timer test mode */
245 
246 /* Interrupt status register */
247 #define	ISR_WAKEEVT	0x10000000U	/* sis900 */
248 #define	ISR_PAUSE_END	0x08000000U	/* sis900 */
249 #define	ISR_PAUSE_ST	0x04000000U	/* sis900 */
250 #define	ISR_TXRCMP	0x02000000U
251 #define	ISR_RXRCMP	0x01000000U
252 #define	ISR_DPERR	0x00800000U	/* Detected parity error */
253 #define	ISR_SSERR	0x00400000U	/* Signaled system error */
254 #define	ISR_RMABT	0x00200000U	/* Received master abort */
255 #define	ISR_RTABT	0x00100000U	/* Received target abort */
256 #define	ISR_RXSOVR	0x00010000U	/* Received status FIFO overrun */
257 #define	ISR_HIBERR	0x00008000U
258 #define	ISR_SWI		0x00001000U
259 #define	ISR_TXURN	0x00000400U
260 #define	ISR_TXIDLE	0x00000200U
261 #define	ISR_TXERR	0x00000100U
262 #define	ISR_TXDESC	0x00000080U
263 #define	ISR_TXOK	0x00000040U
264 #define	ISR_RXORN	0x00000020U
265 #define	ISR_RXIDLE	0x00000010U
266 #define	ISR_RXEARLY	0x00000008U
267 #define	ISR_RXERR	0x00000004U
268 #define	ISR_RXDESC	0x00000002U
269 #define	ISR_RXOK	0x00000001U
270 
271 #define	INTR_BITS	\
272 	"\020"		\
273 	"\035WakeEvt"	\
274 	"\034PauseEnd"	\
275 	"\033PauseST"	\
276 	"\032TXRCMP"	\
277 	"\031RXRCMP"	\
278 	"\030DPErr"	\
279 	"\027SSErr"	\
280 	"\026RMAbt"	\
281 	"\025RTAbt"	\
282 	"\021RxSOVR"	\
283 	"\020HIBErr"	\
284 	"\015SWI"	\
285 	"\013TxUrn"	\
286 	"\012TxIdle"	\
287 	"\011TxErr"	\
288 	"\010TxDesc"	\
289 	"\007TxOk"	\
290 	"\006RxORN"	\
291 	"\005RxIdle"	\
292 	"\004RxEarly"	\
293 	"\003RxErr"	\
294 	"\002RxDesc"	\
295 	"\001RxOk"
296 
297 
298 /* Interrupt enable reigster */
299 #define	IER_IE		0x00000001	/* Interrupt enable */
300 
301 /* Enhanced PHY acces register */
302 #define	ENPHY_DATA		0xffff0000U	/* data */
303 #define		ENPHY_DATA_SHIFT	16
304 #define	ENPHY_ADDR		0x0000f800U	/* phy address */
305 #define		ENPHY_ADDR_SHIFT	11
306 #define	ENPHY_OFFSET		0x000007c0U	/* offset */
307 #define		ENPHY_OFFSET_SHIFT	6
308 #define	ENPHY_RDCMD		0x00000020U	/* read */
309 #define	ENPHY_ACCESS		0x00000010U	/* busy */
310 
311 
312 /* Transmit configuration register */
313 #define	TXCFG_CSI		0x80000000U	/* carrier sense ignore */
314 #define	TXCFG_HBI		0x40000000U	/* heart beat ignore */
315 #define	TXCFG_MLB		0x20000000U	/* MAC loop back */
316 #define	TXCFG_ATP		0x10000000U	/* Automatic transmit padding */
317 #define	TXCFG_MXDMA		0x00700000U	/* max dma burst size */
318 #define		TXCFG_MXDMA_SHIFT	20
319 #define		TXCFG_MXDMA_512		(0U << TXCFG_MXDMA_SHIFT)
320 #define		TXCFG_MXDMA_4		(1U << TXCFG_MXDMA_SHIFT)
321 #define		TXCFG_MXDMA_8		(2U << TXCFG_MXDMA_SHIFT)
322 #define		TXCFG_MXDMA_16		(3U << TXCFG_MXDMA_SHIFT)
323 #define		TXCFG_MXDMA_32		(4U << TXCFG_MXDMA_SHIFT)
324 #define		TXCFG_MXDMA_64		(5U << TXCFG_MXDMA_SHIFT)
325 #define		TXCFG_MXDMA_128		(6U << TXCFG_MXDMA_SHIFT)
326 #define		TXCFG_MXDMA_256		(7U << TXCFG_MXDMA_SHIFT)
327 #define	TXCFG_FLTH		0x00003f00U	/* Tx fill threshold */
328 #define		TXCFG_FLTH_SHIFT	8
329 #define	TXCFG_DRTH		0x0000003fU	/* Tx drain threshold */
330 
331 #define	TXFIFOSIZE	2048U
332 #define	TXCFG_FIFO_UNIT	32U
333 
334 #define	TXCFG_BITS	"\020\040CSI\037HBI\036MLB\035ATP"
335 
336 /* RXCFG:43 Reveive configuration register */
337 #define	RXCFG_AEP		0x80000000U	/* accept error packets */
338 #define	RXCFG_ARP		0x40000000U	/* accept runt packets */
339 #define	RXCFG_ATX		0x10000000U	/* accept transmit packets */
340 #define	RXCFG_AJAB		0x08000000U	/* accept jabber packets */
341 #define	RXCFG_ALP_DP83815	0x08000000U	/* accept long pakets */
342 #define	RXCFG_MXDMA		0x00700000U	/* max dma burst size */
343 #define		RXCFG_MXDMA_SHIFT	(20)
344 #define		RXCFG_MXDMA_512	(0U << RXCFG_MXDMA_SHIFT)
345 #define		RXCFG_MXDMA_4	(1U << RXCFG_MXDMA_SHIFT)
346 #define		RXCFG_MXDMA_8	(2U << RXCFG_MXDMA_SHIFT)
347 #define		RXCFG_MXDMA_16	(3U << RXCFG_MXDMA_SHIFT)
348 #define		RXCFG_MXDMA_32	(4U << RXCFG_MXDMA_SHIFT)
349 #define		RXCFG_MXDMA_64	(5U << RXCFG_MXDMA_SHIFT)
350 #define		RXCFG_MXDMA_128	(6U << RXCFG_MXDMA_SHIFT)
351 #define		RXCFG_MXDMA_256	(7U << RXCFG_MXDMA_SHIFT)
352 #define	RXCFG_DRTH		0x0000003eU	/* Rx drain threshold */
353 #define		RXCFG_DRTH_SHIFT	1
354 
355 #define	RXFIFOSIZE	2048U
356 #define	RXCFG_FIFO_UNIT	8U
357 
358 #define	RXCFG_BITS	"\020\040AEP\037ARP\035ATX\034AJAB"
359 
360 
361 /* FLWCRL:0x38 Flow Control register */
362 #define	FLOWCTL_PAUSE		0x00000002U	/* PAUSE flag */
363 #define	FLOWCTL_FLOWEN		0x00000001U	/* flow control enable */
364 
365 #define	FLOWCTL_BITS	"\020\002PAUSE\001FLOWEN"
366 
367 /* CCSR:0x3c Clock run Control status register */
368 #define	CCSR_PMESTS	0x00008000U
369 #define	CCSR_PMEEN	0x00000100U
370 #define	CCSR_CLKRUN_EN	0x00000001U
371 
372 /* PCR:0x44 Pause control/status register (DP83815) */
373 #define	PCR_PSEN		0x80000000U	/* Pause Enable */
374 #define	PCR_PS_MCAST		0x40000000U	/* Pause on multicast */
375 #define	PCR_PS_DA		0x20000000U	/* Pause on DA */
376 #define	PCR_PS_ACT		0x00800000U	/* Pause active */
377 #define	PCR_PS_RCVD		0x00400000U	/* Pause frame receved */
378 #define	PCR_PSNEG		0x00200000U	/* Pause negotiated */
379 #define	PCR_MLD_EN		0x00010000U	/* Manual load enable */
380 #define	PCR_PAUSE_CNT		0x0000ffffU	/* Pause counter value */
381 
382 #define	PCR_BITS	\
383 	"\020" \
384 	"\040PCR_PSEN" \
385 	"\037PCR_PS_MCAST" \
386 	"\036PCR_PS_DA" \
387 	"\030PCR_PS_ACT" \
388 	"\027PCR_PS_RCVD" \
389 	"\026PCR_PSNEG" \
390 	"\021PCR_MLD_EN"
391 
392 /* RFCR:0x48 Receive filter control register */
393 #define	RFCR_RFEN		0x80000000U	/* receive filter enable */
394 #define	RFCR_AAB		0x40000000U	/* accept all broadcast */
395 #define	RFCR_AAM		0x20000000U	/* accept all multicast */
396 #define	RFCR_AAP		0x10000000U	/* accept all physical */
397 #define	RFCR_APM_DP83815	0x08000000U	/* accept perfect match */
398 #define	RFCR_APAT_DP83815	0x07800000U	/* accept on pattern match */
399 #define	RFCR_APAT_SHIFT		23		/* pattern match base */
400 #define	RFCR_AARP_DP83815	0x00400000U	/* accept arp packets */
401 #define	RFCR_MHEN_DP83815	0x00200000U	/* multicast hash enable */
402 #define	RFCR_UHEN_DP83815	0x00100000U	/* unicast hash enable */
403 #define	RFCR_ULM_DP83815	0x00080000U	/* U/L bit mask */
404 #define	RFCR_RFADDR_SIS900	0x000f0000U	/* receive filter address */
405 #define	RFCR_RFADDR_SHIFT_SIS900	16
406 #define	RFCR_RFADDR_DP83815	0x000003ffU
407 #define	RFCR_RFADDR_SHIFT_DP83815	0
408 
409 /* Receive filter offset */
410 #define	RFADDR_MAC_SIS900		0U
411 #define	RFADDR_MULTICAST_SIS900		4U
412 
413 #define	RFADDR_MAC_DP83815		0x000U
414 #define	RFADDR_PCOUNT01_DP83815		0x006U
415 #define	RFADDR_PCOUNT23_DP83815		0x008U
416 #define	RFADDR_MULTICAST_DP83815	0x200U
417 #define	RFADDR_PMATCH0_DP83815		0x280U
418 #define	RFADDR_PMATCH1_DP83815		0x282U
419 #define	RFADDR_PMATCH2_DP83815		0x300U
420 #define	RFADDR_PMATCH3_DP83815		0x302U
421 
422 /* Receive filter data register */
423 
424 /* dp83815 Silicon revision register */
425 #define	SRR_REV			0x0000ffffU
426 #define	SRR_REV_DP83815CVNG	0x0302U
427 #define	SRR_REV_DP83815DVNG	0x0403U
428 #define	SRR_REV_DP83816AVNG	0x0505U
429 
430 /* sis900 revisions */
431 #define	SIS630A_900_REV		0x80
432 #define	SIS630E_900_REV		0x81
433 #define	SIS630S_900_REV		0x82
434 #define	SIS630EA1_900_REV	0x83
435 #define	SIS630ET_900_REV	0x84
436 #define	SIS635A_900_REV		0x90
437 #define	SIS962_900_REV		0X91
438 #define	SIS900B_900_REV		0x03
439 
440 #define	SIS630A0	0x00
441 #define	SIS630A1	0x01
442 #define	SIS630B0	0x10
443 #define	SIS630B1	0x11
444 
445 
446 #endif	/* _SFEREG_H_ */
447