xref: /illumos-gate/usr/src/uts/common/io/rwd/rt2661_reg.h (revision 10115c80)
1 /*
2  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
3  * Use is subject to license terms.
4  */
5 
6 /*
7  * Copyright (c) 2006
8  *	Damien Bergamini <damien.bergamini@free.fr>
9  *
10  * Permission to use, copy, modify, and distribute this software for any
11  * purpose with or without fee is hereby granted, provided that the above
12  * copyright notice and this permission notice appear in all copies.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15  * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16  * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17  * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18  * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
19  * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20  * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21  */
22 
23 #ifndef _RT2661_REG_H
24 #define	_RT2661_REG_H
25 
26 #ifdef __cplusplus
27 extern "C" {
28 #endif
29 
30 #define	RT2661_NOISE_FLOOR	-95
31 
32 #define	RT2661_TX_RING_COUNT	32
33 #define	RT2661_MGT_RING_COUNT	32
34 #define	RT2661_RX_RING_COUNT	64
35 
36 #define	RT2661_TX_DESC_SIZE	(sizeof (struct rt2661_tx_desc))
37 #define	RT2661_TX_DESC_WSIZE	(RT2661_TX_DESC_SIZE / 4)
38 #define	RT2661_RX_DESC_SIZE	(sizeof (struct rt2661_rx_desc))
39 #define	RT2661_RX_DESC_WSIZE	(RT2661_RX_DESC_SIZE / 4)
40 
41 #define	RT2661_MAX_SCATTER	5
42 
43 /*
44  * Control and status registers.
45  */
46 #define	RT2661_HOST_CMD_CSR		0x0008
47 #define	RT2661_MCU_CNTL_CSR		0x000c
48 #define	RT2661_SOFT_RESET_CSR		0x0010
49 #define	RT2661_MCU_INT_SOURCE_CSR	0x0014
50 #define	RT2661_MCU_INT_MASK_CSR		0x0018
51 #define	RT2661_PCI_USEC_CSR		0x001c
52 #define	RT2661_H2M_MAILBOX_CSR		0x2100
53 #define	RT2661_M2H_CMD_DONE_CSR		0x2104
54 #define	RT2661_HW_BEACON_BASE0		0x2c00
55 #define	RT2661_MAC_CSR0			0x3000
56 #define	RT2661_MAC_CSR1			0x3004
57 #define	RT2661_MAC_CSR2			0x3008
58 #define	RT2661_MAC_CSR3			0x300c
59 #define	RT2661_MAC_CSR4			0x3010
60 #define	RT2661_MAC_CSR5			0x3014
61 #define	RT2661_MAC_CSR6			0x3018
62 #define	RT2661_MAC_CSR7			0x301c
63 #define	RT2661_MAC_CSR8			0x3020
64 #define	RT2661_MAC_CSR9			0x3024
65 #define	RT2661_MAC_CSR10		0x3028
66 #define	RT2661_MAC_CSR11		0x302c
67 #define	RT2661_MAC_CSR12		0x3030
68 #define	RT2661_MAC_CSR13		0x3034
69 #define	RT2661_MAC_CSR14		0x3038
70 #define	RT2661_MAC_CSR15		0x303c
71 #define	RT2661_TXRX_CSR0		0x3040
72 #define	RT2661_TXRX_CSR1		0x3044
73 #define	RT2661_TXRX_CSR2		0x3048
74 #define	RT2661_TXRX_CSR3		0x304c
75 #define	RT2661_TXRX_CSR4		0x3050
76 #define	RT2661_TXRX_CSR5		0x3054
77 #define	RT2661_TXRX_CSR6		0x3058
78 #define	RT2661_TXRX_CSR7		0x305c
79 #define	RT2661_TXRX_CSR8		0x3060
80 #define	RT2661_TXRX_CSR9		0x3064
81 #define	RT2661_TXRX_CSR10		0x3068
82 #define	RT2661_TXRX_CSR11		0x306c
83 #define	RT2661_TXRX_CSR12		0x3070
84 #define	RT2661_TXRX_CSR13		0x3074
85 #define	RT2661_TXRX_CSR14		0x3078
86 #define	RT2661_TXRX_CSR15		0x307c
87 #define	RT2661_PHY_CSR0			0x3080
88 #define	RT2661_PHY_CSR1			0x3084
89 #define	RT2661_PHY_CSR2			0x3088
90 #define	RT2661_PHY_CSR3			0x308c
91 #define	RT2661_PHY_CSR4			0x3090
92 #define	RT2661_PHY_CSR5			0x3094
93 #define	RT2661_PHY_CSR6			0x3098
94 #define	RT2661_PHY_CSR7			0x309c
95 #define	RT2661_SEC_CSR0			0x30a0
96 #define	RT2661_SEC_CSR1			0x30a4
97 #define	RT2661_SEC_CSR2			0x30a8
98 #define	RT2661_SEC_CSR3			0x30ac
99 #define	RT2661_SEC_CSR4			0x30b0
100 #define	RT2661_SEC_CSR5			0x30b4
101 #define	RT2661_STA_CSR0			0x30c0
102 #define	RT2661_STA_CSR1			0x30c4
103 #define	RT2661_STA_CSR2			0x30c8
104 #define	RT2661_STA_CSR3			0x30cc
105 #define	RT2661_STA_CSR4			0x30d0
106 #define	RT2661_AC0_BASE_CSR		0x3400
107 #define	RT2661_AC1_BASE_CSR		0x3404
108 #define	RT2661_AC2_BASE_CSR		0x3408
109 #define	RT2661_AC3_BASE_CSR		0x340c
110 #define	RT2661_MGT_BASE_CSR		0x3410
111 #define	RT2661_TX_RING_CSR0		0x3418
112 #define	RT2661_TX_RING_CSR1		0x341c
113 #define	RT2661_AIFSN_CSR		0x3420
114 #define	RT2661_CWMIN_CSR		0x3424
115 #define	RT2661_CWMAX_CSR		0x3428
116 #define	RT2661_TX_DMA_DST_CSR		0x342c
117 #define	RT2661_TX_CNTL_CSR		0x3430
118 #define	RT2661_LOAD_TX_RING_CSR		0x3434
119 #define	RT2661_RX_BASE_CSR		0x3450
120 #define	RT2661_RX_RING_CSR		0x3454
121 #define	RT2661_RX_CNTL_CSR		0x3458
122 #define	RT2661_PCI_CFG_CSR		0x3460
123 #define	RT2661_INT_SOURCE_CSR		0x3468
124 #define	RT2661_INT_MASK_CSR		0x346c
125 #define	RT2661_E2PROM_CSR		0x3470
126 #define	RT2661_AC_TXOP_CSR0		0x3474
127 #define	RT2661_AC_TXOP_CSR1		0x3478
128 #define	RT2661_TEST_MODE_CSR		0x3484
129 #define	RT2661_IO_CNTL_CSR		0x3498
130 #define	RT2661_MCU_CODE_BASE		0x4000
131 
132 /* possible flags for register HOST_CMD_CSR */
133 #define	RT2661_KICK_CMD		(1 << 7)
134 /* Host to MCU (8051) command identifiers */
135 #define	RT2661_MCU_CMD_SLEEP	0x30
136 #define	RT2661_MCU_CMD_WAKEUP	0x31
137 #define	RT2661_MCU_SET_LED	0x50
138 #define	RT2661_MCU_SET_RSSI_LED	0x52
139 
140 /* possible flags for register MCU_CNTL_CSR */
141 #define	RT2661_MCU_SEL		(1 << 0)
142 #define	RT2661_MCU_RESET	(1 << 1)
143 #define	RT2661_MCU_READY	(1 << 2)
144 
145 /* possible flags for register MCU_INT_SOURCE_CSR */
146 #define	RT2661_MCU_CMD_DONE		0xff
147 #define	RT2661_MCU_WAKEUP		(1 << 8)
148 #define	RT2661_MCU_BEACON_EXPIRE	(1 << 9)
149 
150 /* possible flags for register H2M_MAILBOX_CSR */
151 #define	RT2661_H2M_BUSY		(1 << 24)
152 #define	RT2661_TOKEN_NO_INTR	0xff
153 
154 /* possible flags for register MAC_CSR5 */
155 #define	RT2661_ONE_BSSID	3
156 
157 /* possible flags for register TXRX_CSR0 */
158 /* Tx filter flags are in the low 16 bits */
159 #define	RT2661_AUTO_TX_SEQ	(1 << 15)
160 /* Rx filter flags are in the high 16 bits */
161 #define	RT2661_DISABLE_RX	(1 << 16)
162 #define	RT2661_DROP_CRC_ERROR	(1 << 17)
163 #define	RT2661_DROP_PHY_ERROR	(1 << 18)
164 #define	RT2661_DROP_CTL		(1 << 19)
165 #define	RT2661_DROP_NOT_TO_ME	(1 << 20)
166 #define	RT2661_DROP_TODS	(1 << 21)
167 #define	RT2661_DROP_VER_ERROR	(1 << 22)
168 #define	RT2661_DROP_MULTICAST	(1 << 23)
169 #define	RT2661_DROP_BROADCAST	(1 << 24)
170 #define	RT2661_DROP_ACKCTS	(1 << 25)
171 
172 /* possible flags for register TXRX_CSR4 */
173 #define	RT2661_SHORT_PREAMBLE	(1 << 19)
174 #define	RT2661_MRR_ENABLED	(1 << 20)
175 #define	RT2661_MRR_CCK_FALLBACK	(1 << 23)
176 
177 /* possible flags for register TXRX_CSR9 */
178 #define	RT2661_TSF_TICKING	(1 << 16)
179 #define	RT2661_TSF_MODE(x)	(((x) & 0x3) << 17)
180 /* TBTT stands for Target Beacon Transmission Time */
181 #define	RT2661_ENABLE_TBTT	(1 << 19)
182 #define	RT2661_GENERATE_BEACON	(1 << 20)
183 
184 /* possible flags for register PHY_CSR0 */
185 #define	RT2661_PA_PE_2GHZ	(1 << 16)
186 #define	RT2661_PA_PE_5GHZ	(1 << 17)
187 
188 /* possible flags for register PHY_CSR3 */
189 #define	RT2661_BBP_READ	(1 << 15)
190 #define	RT2661_BBP_BUSY	(1 << 16)
191 
192 /* possible flags for register PHY_CSR4 */
193 #define	RT2661_RF_21BIT	(21 << 24)
194 #define	RT2661_RF_BUSY	((uint32_t)1 << 31)
195 
196 /* possible values for register STA_CSR4 */
197 #define	RT2661_TX_STAT_VALID	(1 << 0)
198 #define	RT2661_TX_RESULT(v)	(((v) >> 1) & 0x7)
199 #define	RT2661_TX_RETRYCNT(v)	(((v) >> 4) & 0xf)
200 #define	RT2661_TX_QID(v)	(((v) >> 8) & 0xf)
201 #define	RT2661_TX_SUCCESS	0
202 #define	RT2661_TX_RETRY_FAIL	6
203 
204 /* possible flags for register TX_CNTL_CSR */
205 #define	RT2661_KICK_MGT	(1 << 4)
206 
207 /* possible flags for register INT_SOURCE_CSR */
208 #define	RT2661_TX_DONE		(1 << 0)
209 #define	RT2661_RX_DONE		(1 << 1)
210 #define	RT2661_TX0_DMA_DONE	(1 << 16)
211 #define	RT2661_TX1_DMA_DONE	(1 << 17)
212 #define	RT2661_TX2_DMA_DONE	(1 << 18)
213 #define	RT2661_TX3_DMA_DONE	(1 << 19)
214 #define	RT2661_MGT_DONE		(1 << 20)
215 
216 /* possible flags for register E2PROM_CSR */
217 #define	RT2661_C	(1 << 1)
218 #define	RT2661_S	(1 << 2)
219 #define	RT2661_D	(1 << 3)
220 #define	RT2661_Q	(1 << 4)
221 #define	RT2661_93C46	(1 << 5)
222 
223 #pragma pack(1)
224 /* Tx descriptor */
225 struct rt2661_tx_desc {
226 	uint32_t	flags;
227 #define	RT2661_TX_BUSY		(1 << 0)
228 #define	RT2661_TX_VALID		(1 << 1)
229 #define	RT2661_TX_MORE_FRAG	(1 << 2)
230 #define	RT2661_TX_NEED_ACK	(1 << 3)
231 #define	RT2661_TX_TIMESTAMP	(1 << 4)
232 #define	RT2661_TX_OFDM		(1 << 5)
233 #define	RT2661_TX_IFS		(1 << 6)
234 #define	RT2661_TX_LONG_RETRY	(1 << 7)
235 #define	RT2661_TX_BURST		(1 << 28)
236 
237 	uint16_t	wme;
238 #define	RT2661_QID(v)		(v)
239 #define	RT2661_AIFSN(v)		((v) << 4)
240 #define	RT2661_LOGCWMIN(v)	((v) << 8)
241 #define	RT2661_LOGCWMAX(v)	((v) << 12)
242 
243 	uint16_t	xflags;
244 #define	RT2661_TX_HWSEQ		(1 << 12)
245 
246 	uint8_t		plcp_signal;
247 	uint8_t		plcp_service;
248 #define	RT2661_PLCP_LENGEXT	0x80
249 
250 	uint8_t		plcp_length_lo;
251 	uint8_t		plcp_length_hi;
252 
253 	uint32_t	iv;
254 	uint32_t	eiv;
255 
256 	uint8_t		offset;
257 	uint8_t		qid;
258 #define	RT2661_QID_MGT	13
259 
260 	uint8_t		txpower;
261 #define	RT2661_DEFAULT_TXPOWER	0
262 
263 	uint8_t		reserved1;
264 
265 	uint32_t	addr[RT2661_MAX_SCATTER];
266 	uint16_t	len[RT2661_MAX_SCATTER];
267 
268 	uint16_t	reserved2;
269 };
270 #pragma pack()
271 
272 #pragma pack(1)
273 /* Rx descriptor */
274 struct rt2661_rx_desc {
275 	uint32_t	flags;
276 #define	RT2661_RX_BUSY		(1 << 0)
277 #define	RT2661_RX_DROP		(1 << 1)
278 #define	RT2661_RX_CRC_ERROR	(1 << 6)
279 #define	RT2661_RX_OFDM		(1 << 7)
280 #define	RT2661_RX_PHY_ERROR	(1 << 8)
281 #define	RT2661_RX_CIPHER_MASK	0x00000600
282 
283 	uint8_t		rate;
284 	uint8_t		rssi;
285 	uint8_t		reserved1;
286 	uint8_t		offset;
287 	uint32_t	iv;
288 	uint32_t	eiv;
289 	uint32_t	reserved2;
290 	uint32_t	physaddr;
291 	uint32_t	reserved3[10];
292 };
293 #pragma pack()
294 
295 #define	RT2661_RF1	0
296 #define	RT2661_RF2	2
297 #define	RT2661_RF3	1
298 #define	RT2661_RF4	3
299 
300 /* dual-band RF */
301 #define	RT2661_RF_5225	1
302 #define	RT2661_RF_5325	2
303 /* single-band RF */
304 #define	RT2661_RF_2527	3
305 #define	RT2661_RF_2529	4
306 
307 #define	RT2661_RX_DESC_BACK	4
308 
309 #define	RT2661_SMART_MODE	(1 << 0)
310 
311 #define	RT2661_BBPR94_DEFAULT	6
312 
313 #define	RT2661_SHIFT_D	3
314 #define	RT2661_SHIFT_Q	4
315 
316 #define	RT2661_EEPROM_MAC01		0x02
317 #define	RT2661_EEPROM_MAC23		0x03
318 #define	RT2661_EEPROM_MAC45		0x04
319 #define	RT2661_EEPROM_ANTENNA		0x10
320 #define	RT2661_EEPROM_CONFIG2		0x11
321 #define	RT2661_EEPROM_BBP_BASE		0x13
322 #define	RT2661_EEPROM_TXPOWER		0x23
323 #define	RT2661_EEPROM_FREQ_OFFSET	0x2f
324 #define	RT2661_EEPROM_RSSI_2GHZ_OFFSET	0x4d
325 #define	RT2661_EEPROM_RSSI_5GHZ_OFFSET	0x4e
326 
327 #define	RT2661_EEPROM_DELAY	1	/* minimum hold time (microsecond) */
328 
329 /*
330  * control and status registers access macros
331  */
332 #define	RT2661_READ(sc, reg)						\
333 	ddi_get32((sc)->sc_io_handle,					\
334 	    (uint32_t *)((uintptr_t)(sc)->sc_io_base + (reg)))
335 
336 #define	RT2661_WRITE(sc, reg, val)					\
337 	ddi_put32((sc)->sc_io_handle,					\
338 	    (uint32_t *)((uintptr_t)(sc)->sc_io_base + (reg)), (val))
339 
340 #define	RT2661_MEM_WRITE1(sc, reg, val)					\
341 	ddi_put8((sc)->sc_io_handle,					\
342 	    (uint8_t *)((sc)->sc_io_base + (reg)), (val))
343 
344 #define	RT2661_MEM_READ1(sc, reg)					\
345 	ddi_get8((sc)->sc_io_handle,					\
346 	    (uint8_t *)((sc)->sc_io_base + (reg)))
347 
348 /*
349  * EEPROM access macro
350  */
351 #define	RT2661_EEPROM_CTL(sc, val) do {					\
352 	RT2661_WRITE((sc), RT2661_E2PROM_CSR, (val));			\
353 	DELAY(RT2661_EEPROM_DELAY);					\
354 	_NOTE(CONSTCOND)						\
355 } while (0)
356 
357 /*
358  * Default values for MAC registers; values taken from the reference driver.
359  */
360 #define	RT2661_DEF_MAC					\
361 	{ RT2661_TXRX_CSR0,	0x0000b032 },	\
362 	{ RT2661_TXRX_CSR1,	0x9eb39eb3 },	\
363 	{ RT2661_TXRX_CSR2,	0x8a8b8c8d },	\
364 	{ RT2661_TXRX_CSR3,	0x00858687 },	\
365 	{ RT2661_TXRX_CSR7,	0x2e31353b },	\
366 	{ RT2661_TXRX_CSR8,	0x2a2a2a2c },	\
367 	{ RT2661_TXRX_CSR15,	0x0000000f },	\
368 	{ RT2661_MAC_CSR6,	0x00000fff },	\
369 	{ RT2661_MAC_CSR8,	0x016c030a },	\
370 	{ RT2661_MAC_CSR10,	0x00000718 },	\
371 	{ RT2661_MAC_CSR12,	0x00000004 },	\
372 	{ RT2661_MAC_CSR13,	0x0000e000 },	\
373 	{ RT2661_SEC_CSR0,	0x00000000 },	\
374 	{ RT2661_SEC_CSR1,	0x00000000 },	\
375 	{ RT2661_SEC_CSR5,	0x00000000 },	\
376 	{ RT2661_PHY_CSR1,	0x000023b0 },	\
377 	{ RT2661_PHY_CSR5,	0x060a100c },	\
378 	{ RT2661_PHY_CSR6,	0x00080606 },	\
379 	{ RT2661_PHY_CSR7,	0x00000a08 },	\
380 	{ RT2661_PCI_CFG_CSR,	0x3cca4808 },	\
381 	{ RT2661_AIFSN_CSR,	0x00002273 },	\
382 	{ RT2661_CWMIN_CSR,	0x00002344 },	\
383 	{ RT2661_CWMAX_CSR,	0x000034aa },	\
384 	{ RT2661_TEST_MODE_CSR,	0x00000200 },	\
385 	{ RT2661_M2H_CMD_DONE_CSR,	0xffffffff }
386 
387 /*
388  * Default values for BBP registers; values taken from the reference driver.
389  */
390 #define	RT2661_DEF_BBP	\
391 	{   3, 0x00 },	\
392 	{  15, 0x30 },	\
393 	{  17, 0x20 },	\
394 	{  21, 0xc8 },	\
395 	{  22, 0x38 },	\
396 	{  23, 0x06 },	\
397 	{  24, 0xfe },	\
398 	{  25, 0x0a },	\
399 	{  26, 0x0d },	\
400 	{  34, 0x12 },	\
401 	{  37, 0x07 },	\
402 	{  39, 0xf8 },	\
403 	{  41, 0x60 },	\
404 	{  53, 0x10 },	\
405 	{  54, 0x18 },	\
406 	{  60, 0x10 },	\
407 	{  61, 0x04 },	\
408 	{  62, 0x04 },	\
409 	{  75, 0xfe },	\
410 	{  86, 0xfe },	\
411 	{  88, 0xfe },	\
412 	{  90, 0x0f },	\
413 	{  99, 0x00 },	\
414 	{ 102, 0x16 },	\
415 	{ 107, 0x04 }
416 
417 /*
418  * Default settings for RF registers; values taken from the reference driver.
419  */
420 #define	RT2661_RF5225_1					\
421 	{   1, 0x00b33, 0x011e1, 0x1a014, 0x30282 },	\
422 	{   2, 0x00b33, 0x011e1, 0x1a014, 0x30287 },	\
423 	{   3, 0x00b33, 0x011e2, 0x1a014, 0x30282 },	\
424 	{   4, 0x00b33, 0x011e2, 0x1a014, 0x30287 },	\
425 	{   5, 0x00b33, 0x011e3, 0x1a014, 0x30282 },	\
426 	{   6, 0x00b33, 0x011e3, 0x1a014, 0x30287 },	\
427 	{   7, 0x00b33, 0x011e4, 0x1a014, 0x30282 },	\
428 	{   8, 0x00b33, 0x011e4, 0x1a014, 0x30287 },	\
429 	{   9, 0x00b33, 0x011e5, 0x1a014, 0x30282 },	\
430 	{  10, 0x00b33, 0x011e5, 0x1a014, 0x30287 },	\
431 	{  11, 0x00b33, 0x011e6, 0x1a014, 0x30282 },	\
432 	{  12, 0x00b33, 0x011e6, 0x1a014, 0x30287 },	\
433 	{  13, 0x00b33, 0x011e7, 0x1a014, 0x30282 },	\
434 	{  14, 0x00b33, 0x011e8, 0x1a014, 0x30284 },	\
435 							\
436 	{  36, 0x00b33, 0x01266, 0x26014, 0x30288 },	\
437 	{  40, 0x00b33, 0x01268, 0x26014, 0x30280 },	\
438 	{  44, 0x00b33, 0x01269, 0x26014, 0x30282 },	\
439 	{  48, 0x00b33, 0x0126a, 0x26014, 0x30284 },	\
440 	{  52, 0x00b33, 0x0126b, 0x26014, 0x30286 },	\
441 	{  56, 0x00b33, 0x0126c, 0x26014, 0x30288 },	\
442 	{  60, 0x00b33, 0x0126e, 0x26014, 0x30280 },	\
443 	{  64, 0x00b33, 0x0126f, 0x26014, 0x30282 },	\
444 							\
445 	{ 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 },	\
446 	{ 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 },	\
447 	{ 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 },	\
448 	{ 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 },	\
449 	{ 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 },	\
450 	{ 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 },	\
451 	{ 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 },	\
452 	{ 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 },	\
453 	{ 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 },	\
454 	{ 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 },	\
455 	{ 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 },	\
456 							\
457 	{ 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 },	\
458 	{ 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 },	\
459 	{ 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 },	\
460 	{ 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 },	\
461 	{ 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 }
462 
463 #define	RT2661_RF5225_2					\
464 	{   1, 0x00b33, 0x011e1, 0x1a014, 0x30282 },	\
465 	{   2, 0x00b33, 0x011e1, 0x1a014, 0x30287 },	\
466 	{   3, 0x00b33, 0x011e2, 0x1a014, 0x30282 },	\
467 	{   4, 0x00b33, 0x011e2, 0x1a014, 0x30287 },	\
468 	{   5, 0x00b33, 0x011e3, 0x1a014, 0x30282 },	\
469 	{   6, 0x00b33, 0x011e3, 0x1a014, 0x30287 },	\
470 	{   7, 0x00b33, 0x011e4, 0x1a014, 0x30282 },	\
471 	{   8, 0x00b33, 0x011e4, 0x1a014, 0x30287 },	\
472 	{   9, 0x00b33, 0x011e5, 0x1a014, 0x30282 },	\
473 	{  10, 0x00b33, 0x011e5, 0x1a014, 0x30287 },	\
474 	{  11, 0x00b33, 0x011e6, 0x1a014, 0x30282 },	\
475 	{  12, 0x00b33, 0x011e6, 0x1a014, 0x30287 },	\
476 	{  13, 0x00b33, 0x011e7, 0x1a014, 0x30282 },	\
477 	{  14, 0x00b33, 0x011e8, 0x1a014, 0x30284 },	\
478 							\
479 	{  36, 0x00b35, 0x11206, 0x26014, 0x30280 },	\
480 	{  40, 0x00b34, 0x111a0, 0x26014, 0x30280 },	\
481 	{  44, 0x00b34, 0x111a1, 0x26014, 0x30286 },	\
482 	{  48, 0x00b34, 0x111a3, 0x26014, 0x30282 },	\
483 	{  52, 0x00b34, 0x111a4, 0x26014, 0x30288 },	\
484 	{  56, 0x00b34, 0x111a6, 0x26014, 0x30284 },	\
485 	{  60, 0x00b34, 0x111a8, 0x26014, 0x30280 },	\
486 	{  64, 0x00b34, 0x111a9, 0x26014, 0x30286 },	\
487 							\
488 	{ 100, 0x00b35, 0x11226, 0x2e014, 0x30280 },	\
489 	{ 104, 0x00b35, 0x11228, 0x2e014, 0x30280 },	\
490 	{ 108, 0x00b35, 0x1122a, 0x2e014, 0x30280 },	\
491 	{ 112, 0x00b35, 0x1122c, 0x2e014, 0x30280 },	\
492 	{ 116, 0x00b35, 0x1122e, 0x2e014, 0x30280 },	\
493 	{ 120, 0x00b34, 0x111c0, 0x2e014, 0x30280 },	\
494 	{ 124, 0x00b34, 0x111c1, 0x2e014, 0x30286 },	\
495 	{ 128, 0x00b34, 0x111c3, 0x2e014, 0x30282 },	\
496 	{ 132, 0x00b34, 0x111c4, 0x2e014, 0x30288 },	\
497 	{ 136, 0x00b34, 0x111c6, 0x2e014, 0x30284 },	\
498 	{ 140, 0x00b34, 0x111c8, 0x2e014, 0x30280 },	\
499 							\
500 	{ 149, 0x00b34, 0x111cb, 0x2e014, 0x30286 },	\
501 	{ 153, 0x00b34, 0x111cd, 0x2e014, 0x30282 },	\
502 	{ 157, 0x00b35, 0x11242, 0x2e014, 0x30285 },	\
503 	{ 161, 0x00b35, 0x11244, 0x2e014, 0x30285 },	\
504 	{ 165, 0x00b35, 0x11246, 0x2e014, 0x30285 }
505 
506 #ifdef __cplusplus
507 }
508 #endif
509 
510 #endif /* _RT2661_REG_H */
511