xref: /illumos-gate/usr/src/uts/common/io/udmf/dm9601reg.h (revision 6716431b)
1 /*
2  * Macro definitions for Davicom DM9601 USB to fast ethernet controler
3  * based on Davicom DM9601E data sheet
4  * This file is public domain. Coded by M.Murayama (KHF04453@nifty.com)
5  */
6 
7 #ifndef __DM9601_H__
8 #define	__DM9601_H__
9 
10 /*
11  * offset of registers
12  */
13 #define	NCR	0x00U	/* network control register */
14 #define	NSR	0x01U	/* network status register */
15 #define	TCR	0x02U	/* tx control register */
16 #define	TSR1	0x03U	/* tx status register 1 */
17 #define	TSR2	0x04U	/* tx status register 2 */
18 #define	RCR	0x05U	/* rx control register */
19 #define	RSR	0x06U	/* rx status register */
20 #define	ROCR	0x07U	/* rx overflow counter register */
21 #define	BPTR	0x08U	/* back pressure threshold regster */
22 #define	FCTR	0x09U	/* flow control threshold regster */
23 #define	FCR	0x0aU	/* flow control threshold regster */
24 #define	EPCR	0x0bU	/* eeprom & phy control register */
25 #define	EPAR	0x0cU	/* eeprom & phy address register */
26 #define	EPDR	0x0dU	/* eeprom & phy data register (2byte) */
27 #define	WCR	0x0fU	/* wake up control register */
28 #define	PAR	0x10U	/* physical address register (6byte) */
29 #define	MAR	0x16U	/* multicast address register (8byte) */
30 #define	GPCR	0x1eU	/* general purpose control register */
31 #define	GPR	0x1fU	/* general purpose register */
32 #define	VID	0x28U	/* vendor ID (2byte) */
33 #define	PID	0x2aU	/* product ID (2byte) */
34 #define	CHIPR	0x2cU	/* chip revision */
35 #define	USBDA	0xf0U	/* usb device address register */
36 #define	RXC	0xf1U	/* received packet counter register */
37 #define	TUSC	0xf2U	/* tx packet counter/usb status register */
38 #define	USBC	0xf4U	/* usb control register */
39 
40 /*
41  * register definitions
42  */
43 /* network control register */
44 #define	NCR_EXT_PHY	0x80U	/* 1: select external phy */
45 #define	NCR_WAKEEN	0x40U	/* 1: wake up event enable */
46 #define	NCR_FCOL	0x10U	/* force collision mode for test */
47 #define	NCR_FDX		0x08U	/* 1: full duplex mode (for external phy) */
48 #define	NCR_LBK		0x06U
49 #define		NCR_LBK_SHIFT		1
50 #define		NCR_LBK_NORMAL	(0U << NCR_LBK_SHIFT)
51 #define		NCR_LBK_MAC	(1U << NCR_LBK_SHIFT)
52 #define		NCR_LBK_PHY_D	(2U << NCR_LBK_SHIFT)
53 #define		NCR_LBK_PHY_A	(3U << NCR_LBK_SHIFT)
54 #define	NCR_RST		0x01U	/* 1: reset, auto clear */
55 
56 #define	NCR_BITS	\
57 	"\020"	\
58 	"\010EXT_PHY"	\
59 	"\007WAKEEN"	\
60 	"\005FCOL"	\
61 	"\004FDX"	\
62 	"\001RST"
63 
64 /* network status register */
65 #define	NSR_SPEED	0x80U	/* 1:10M 0:100M */
66 #define	NSR_LINKST	0x40U	/* 1:ok 0:fail */
67 #define	NSR_WAKEST	0x20U	/* 1:enabled */
68 #define	NSR_TXFULL	0x10U	/* 1:tx fifo full */
69 #define	NSR_TX2END	0x08U	/* tx packet2 complete status */
70 #define	NSR_TX1END	0x04U	/* tx packet1 complete status */
71 #define	NSR_RXOV	0x02U	/* rx fifo overflow */
72 #define	NSR_RXRDY	0x01U	/* rx packet ready */
73 
74 #define	NSR_BITS	\
75 	"\020"	\
76 	"\010SPEED_10"	\
77 	"\007LINKST_UP"	\
78 	"\006WAKEST"	\
79 	"\005TXFULL"	\
80 	"\004TX2END"	\
81 	"\003TX1END"	\
82 	"\002RXOV"	\
83 	"\001RXRDY"
84 
85 /* tx control register */
86 #define	TCR_TJDIS	0x40U	/* tx jitter control */
87 #define	TCR_EXCEDM	0x20U	/* excessive collision mode */
88 #define	TCR_PAD_DIS2	0x10U	/* PAD appends disable for pkt2 */
89 #define	TCR_CRC_DIS2	0x08U	/* CRC appends disable for pkt2 */
90 #define	TCR_PAD_DIS1	0x04U	/* PAD appends disable for pkt1 */
91 #define	TCR_CRC_DIS1	0x02U	/* CRC appends disable for pkt1 */
92 
93 #define	TCR_BITS	\
94 	"\020"	\
95 	"\007TJDIS"	\
96 	"\006EXCEDM"	\
97 	"\005PAD_DIS2"	\
98 	"\004CRC_DIS2"	\
99 	"\003PAD_DIS1"	\
100 	"\002CRC_DIS1"
101 
102 /* tx status register (ro) */
103 #define	TSR_TJTO	0x80U	/* tx jabber time out */
104 #define	TSR_LC		0x40U	/* loss of carrier */
105 #define	TSR_NC		0x20U	/* no carrier */
106 #define	TSR_LATEC	0x10U	/* late collision */
107 #define	TSR_COL		0x08U	/* late collision */
108 #define	TSR_EL		0x04U	/* excessive collision */
109 
110 #define	TSR_BITS	\
111 	"\020"		\
112 	"\010TJTO"	\
113 	"\007LC"	\
114 	"\006NC"	\
115 	"\005LATEC"	\
116 	"\004COL"	\
117 	"\003EL"
118 
119 /* rx control register */
120 #define	RCR_WTDIS	0x40U	/* watch dog timer disable */
121 #define	RCR_DIS_LONG	0x20U	/* discard longer packets than 1522 */
122 #define	RCR_DIS_CRC	0x10U	/* discard crc error packets */
123 #define	RCR_ALL		0x08U	/* pass all multicast */
124 #define	RCR_RUNT	0x04U	/* pass runt packets */
125 #define	RCR_PRMSC	0x02U	/* promiscuous mode */
126 #define	RCR_RXEN	0x01U	/* rx enable */
127 
128 #define	RCR_BITS	\
129 	"\020"		\
130 	"\007WTDIS"	\
131 	"\006DIS_LONG"	\
132 	"\005DIS_CRC"	\
133 	"\004ALL"	\
134 	"\003RUNT"	\
135 	"\002PRMSC"	\
136 	"\001RXEN"
137 
138 /* rx status register */
139 #define	RSR_RF		0x80U	/* runt frame */
140 #define	RSR_MF		0x40U	/* multicast frame */
141 #define	RSR_LCS		0x20U	/* late collision seen */
142 #define	RSR_RWTO	0x10U	/* receive watchdog timeout */
143 #define	RSR_PLE		0x08U	/* physical layer error */
144 #define	RSR_AE		0x04U	/* alignment error */
145 #define	RSR_CE		0x02U	/* crc error */
146 #define	RSR_FOE		0x01U	/* fifo overflow error */
147 
148 #define	RSR_BITS	\
149 	"\020"		\
150 	"\010RF"	\
151 	"\007MF"	\
152 	"\006LCS"	\
153 	"\005RWTO"	\
154 	"\004PLE"	\
155 	"\003AE"	\
156 	"\002CE"	\
157 	"\001FOE"
158 
159 /* receive overflow counter register */
160 #define	ROCR_RXFU	0x80U	/* receive overflow counter overflow */
161 #define	ROCR_ROC	0x7fU	/* receive overflow counter */
162 
163 #define	ROCR_BITS	\
164 	"\020"		\
165 	"\010RXFU"
166 
167 /* back pressure threshold register */
168 #define	BPTR_BPHW	0xf0U	/* high water overflow threshold */
169 #define		BPTR_BPHW_SHIFT	4
170 #define		BPTR_BPHW_UNIT	1024U
171 #define		BPTR_BPHW_DEFAULT	(3 << BPTR_BPHW_SHIFT)	/* 3k */
172 #define	BPTR_JPT	0x0fU	/* jam pattern time */
173 #define		BPTR_JPT_SHIFT	0
174 #define		BPTR_JPT_5us	(0U << BPTR_JPT_SHIFT)
175 #define		BPTR_JPT_10us	(1U << BPTR_JPT_SHIFT)
176 #define		BPTR_JPT_15us	(2U << BPTR_JPT_SHIFT)
177 #define		BPTR_JPT_25us	(3U << BPTR_JPT_SHIFT)
178 #define		BPTR_JPT_50us	(4U << BPTR_JPT_SHIFT)
179 #define		BPTR_JPT_100us	(5U << BPTR_JPT_SHIFT)
180 #define		BPTR_JPT_150us	(6U << BPTR_JPT_SHIFT)
181 #define		BPTR_JPT_200us	(7U << BPTR_JPT_SHIFT)
182 #define		BPTR_JPT_250us	(8U << BPTR_JPT_SHIFT)
183 #define		BPTR_JPT_300us	(9U << BPTR_JPT_SHIFT)
184 #define		BPTR_JPT_350us	(10U << BPTR_JPT_SHIFT)
185 #define		BPTR_JPT_400us	(11U << BPTR_JPT_SHIFT)
186 #define		BPTR_JPT_450us	(12U << BPTR_JPT_SHIFT)
187 #define		BPTR_JPT_500us	(13U << BPTR_JPT_SHIFT)
188 #define		BPTR_JPT_550us	(14U << BPTR_JPT_SHIFT)
189 #define		BPTR_JPT_600us	(15U << BPTR_JPT_SHIFT)
190 
191 /* flow control threshold register */
192 #define	FCTR_HWOT	0xf0U	/* rx fifo high water overflow threshold */
193 #define		FCTR_HWOT_SHIFT	4
194 #define		FCTR_HWOT_UNIT	1024U
195 #define	FCTR_LWOT	0x0fU	/* rx fifo low water overflow threshold */
196 #define		FCTR_LWOT_SHIFT	0
197 #define		FCTR_LWOT_UNIT	1024U
198 
199 /* rx/tx flow control register */
200 #define	FCR_TXPO	0x80U	/* tx pause packet */
201 #define	FCR_TXPF	0x40U	/* tx pause packet */
202 #define	FCR_TXPEN	0x20U	/* tx pause packet */
203 #define	FCR_BKPA	0x10U	/* back pressure mode */
204 #define	FCR_BKPM	0x08U	/* back pressure mode */
205 #define	FCR_BKPS	0x04U	/* rx pause packet current status (r/c) */
206 #define	FCR_RXPCS	0x02U	/* rx pause packet current status (ro) */
207 #define	FCR_FLCE	0x01U	/* flow control enbale */
208 
209 #define	FCR_BITS	\
210 	"\020"		\
211 	"\000TXPO"	\
212 	"\000TXPF"	\
213 	"\000TXPEN"	\
214 	"\000BKPA"	\
215 	"\000BKPM"	\
216 	"\000BKPS"	\
217 	"\000RXPCS"	\
218 	"\000FLCE"
219 
220 /* EEPROM & PHY control register (0x0b) */
221 #define	EPCR_REEP	0x20U	/* reload eeprom */
222 #define	EPCR_WEP	0x10U	/* write eeprom enable */
223 #define	EPCR_EPOS	0x08U	/* select device, 0:eeprom, 1:phy */
224 #define	EPCR_ERPRR	0x04U	/* read command */
225 #define	EPCR_ERPRW	0x02U	/* write command */
226 #define	EPCR_ERRE	0x01U	/* eeprom/phy access in progress (ro) */
227 
228 #define	EPCR_BITS	\
229 	"\020"		\
230 	"\005REEP"	\
231 	"\004WEP"	\
232 	"\003EPOS"	\
233 	"\002ERPRR"	\
234 	"\001ERPRW"	\
235 	"\000ERRE"
236 
237 /* EEPROM & PHY access register (0x0c) */
238 #define	EPAR_PHYADR	0xc0U	/* phy address, internal phy(1) or external */
239 #define		EPAR_PHYADR_SHIFT	6
240 #define	EPAR_EROA	0x3fU	/* eeprom word addr or phy register addr */
241 #define		EPAR_EROA_SHIFT	0
242 
243 /* EEPROM & PHY data register (0x0d(low)-0x0e(hi)) */
244 
245 /* wake up control register (0x0f) */
246 #define	WCR_LINKEN	0x20U	/* enable link status event */
247 #define	WCR_SAMPLEEN	0x10U	/* enable sample frame event */
248 #define	WCR_MAGICEN	0x08U	/* enable magic pkt event */
249 #define	WCR_LINKST	0x04U	/* link status change occur ro */
250 #define	WCR_SAMPLEST	0x02U	/* sample frame rx occur ro */
251 #define	WCR_MAGICST	0x01U	/* magic pkt rx occur ro */
252 
253 #define	WCR_BITS	\
254 	"\020"		\
255 	"\000LINKEN"	\
256 	"\000SAMPLEEN"	\
257 	"\000MAGICEN"	\
258 	"\000LINKST"	\
259 	"\000SAMPLEST"	\
260 	"\000MAGICST"
261 
262 /* physical address register (0x10-0x15) */
263 /* multicast address register (0x16-0x1c) */
264 /* general purpose control register (0x1e) */
265 #define	GPCR_GEPCTRL	0x7f
266 #define		GPCR_OUT(n)	(1U << (n))
267 
268 #define	GPCR_BITS	\
269 	"\020"		\
270 	"\006OUT5"	\
271 	"\005OUT4"	\
272 	"\004OUT3"	\
273 	"\003OUT2"	\
274 	"\002OUT1"	\
275 	"\001OUT0"
276 
277 /* general purpose register (0x1f) */
278 #define	GPR_GEPIO5	0x20U
279 #define	GPR_GEPIO4	0x10U
280 #define	GPR_GEPIO3	0x08U
281 #define	GPR_GEPIO2	0x04U
282 #define	GPR_GEPIO1	0x02U
283 #define	GPR_GEPIO0	0x01U
284 
285 #define	GPR_BITS	\
286 	"\020"		\
287 	"\006GEPIO5"	\
288 	"\005GEPIO4"	\
289 	"\004GEPIO3"	\
290 	"\003GEPIO2"	\
291 	"\002GEPIO1"	\
292 	"\001GEPIO0"
293 
294 /* vendor id register (0x28-0x29) */
295 /* product id register (0x2a-0x2b) */
296 /* chip revision register (0x2c) */
297 
298 /* usb device address register (0xf0) */
299 #define	USBDA_USBFA	0x3fU	/* usb device address */
300 #define		USBDA_USBFA_SHIFT	0
301 
302 /* receive packet counter register (0xf1) */
303 
304 /* transmitpacket counter/usb status register (0xf2) */
305 #define	TUSR_RXFAULT	0x80U	/* indicate rx has unexpected condition */
306 #define	TUSR_SUSFLAG	0x40U	/* indicate device has suspended condition */
307 #define	TUSR_EP1RDY	0x20U	/* ready for read from ep1 pipe */
308 #define	TUSR_SRAM	0x18U	/* sram size 0:32K, 1:48K, 2:16K, 3:64K */
309 #define		TUSR_SRAM_SHIFT	3
310 #define		TUSR_SRAM_32K	(0U << TUSR_SRAM_SHIFT)
311 #define		TUSR_SRAM_48K	(1U << TUSR_SRAM_SHIFT)
312 #define		TUSR_SRAM_16K	(2U << TUSR_SRAM_SHIFT)
313 #define		TUSR_SRAM_64K	(3U << TUSR_SRAM_SHIFT)
314 #define	TUSR_TXC2	0x04U	/* two or more packets in tx buffer */
315 #define	TUSR_TXC1	0x02U	/* one packet in tx buffer */
316 #define	TUSR_TXC0	0x01U	/* no packet in tx buffer */
317 
318 #define	TUSR_BITS	\
319 	"\020"		\
320 	"\010RXFAULT"	\
321 	"\007SUSFLAG"	\
322 	"\006EP1RDY"	\
323 	"\003TXC2"	\
324 	"\002TXC1"	\
325 	"\001TXC0"
326 
327 /* usb control register (0xf4) */
328 #define	USBC_EP3ACK	0x20U	/* ep3 will alway return 8byte data if NAK=0 */
329 #define	USBC_EP3NACK	0x10U	/* ep3 will alway return NAK */
330 #define	USBC_MEMTST	0x01U
331 
332 /* bulk message format */
333 #define	TX_HEADER_SIZE	2
334 #define	RX_HEADER_SIZE	3
335 
336 /* interrupt msg format */
337 struct intr_msg {
338 	uint8_t	im_nsr;
339 	uint8_t	im_tsr1;
340 	uint8_t	im_tsr2;
341 	uint8_t	im_rsr;
342 	uint8_t	im_rocr;
343 	uint8_t	im_rxc;
344 	uint8_t	im_txc;
345 	uint8_t	im_gpr;
346 };
347 #endif /* __DM9601_H__ */
348