1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_SDCARD_SDHOST_H
27 #define	_SYS_SDCARD_SDHOST_H
28 
29 /*
30  * The entire contents of this file are private the SD Host driver
31  * implementation.
32  */
33 
34 #include <sys/types.h>
35 #include <sys/ksynch.h>
36 #include <sys/param.h>
37 #include <sys/kmem.h>
38 #include <sys/inttypes.h>
39 #include <sys/cmn_err.h>
40 #include <sys/conf.h>
41 #include <sys/modctl.h>
42 #include <sys/sdcard/sda.h>
43 #include <sys/pci.h>
44 #include <sys/kstat.h>
45 #include <sys/ddi.h>
46 #include <sys/sunddi.h>
47 
48 #define	BIT(x)	(1 << (x))
49 
50 /*
51  * SD Host Spec says that a controller can support up to 6 different
52  * slots, each with its own register set.
53  */
54 #define	SDHOST_MAXSLOTS	6
55 
56 /*
57  * SD Host specific PCI configuration register.
58  */
59 #define	SLOTINFO		0x40
60 #define	SLOTINFO_NSLOT_SHFT	4
61 #define	SLOTINFO_NSLOT_MSK	(0x3 << SLOTINFO_NSLOT_SHFT)
62 #define	SLOTINFO_BAR_SHFT	0
63 #define	SLOTINFO_BAR_MSK	(0x3 << SLOTINFO_BAR_SHFT)
64 
65 #define	SLOTINFO_NSLOT(x)		\
66 	((((x) & SLOTINFO_NSLOT_MSK) >> SLOTINFO_NSLOT_SHFT) + 1)
67 
68 #define	SLOTINFO_BAR(x)		\
69 	(((x) & SLOTINFO_BAR_MSK) >> SLOTINFO_BAR_SHFT)
70 
71 /*
72  * Slot-specific CSRs
73  */
74 #define	REG_SDMA_ADDR			0x0000	/* 32 bits */
75 #define	REG_BLKSZ			0x0004	/* 16 bits */
76 #define	REG_BLOCK_COUNT			0x0006	/* 16 bits */
77 #define	REG_ARGUMENT			0x0008	/* 32 bits */
78 #define	REG_XFR_MODE			0x000C	/* 16 bits */
79 #define	REG_COMMAND			0x000E	/* 16 bits */
80 #define	REG_RESP1			0x0010	/* 32 bits */
81 #define	REG_RESP2			0x0014	/* 32 bits */
82 #define	REG_RESP3			0x0018	/* 32 bits */
83 #define	REG_RESP4			0x001C	/* 32 bits */
84 #define	REG_DATA			0x0020	/* 32 bits */
85 #define	REG_PRS				0x0024	/* 32 bits */
86 #define	REG_HOST_CONTROL		0x0028	/* 8 bits */
87 #define	REG_POWER_CONTROL		0x0029	/* 8 bits */
88 #define	REG_BLOCK_GAP_CONTROL		0x002A	/* 8 bits */
89 #define	REG_WAKEUP_CONTROL		0x002B	/* 8 bits */
90 #define	REG_CLOCK_CONTROL		0x002C	/* 16 bits */
91 #define	REG_TIMEOUT_CONTROL		0x002E	/* 8 bits */
92 #define	REG_SOFT_RESET			0x002F	/* 8 bits */
93 #define	REG_INT_STAT			0x0030	/* 16 bits */
94 #define	REG_ERR_STAT			0x0032	/* 16 bits */
95 #define	REG_INT_EN			0x0034	/* 16 bits */
96 #define	REG_ERR_EN			0x0036	/* 16 bits */
97 #define	REG_INT_MASK			0x0038	/* 16 bits */
98 #define	REG_ERR_MASK			0x003A	/* 16 bits */
99 #define	REG_ACMD12_ERROR		0x003C	/* 16 bits */
100 #define	REG_CAPAB			0x0040	/* 64 bits */
101 #define	REG_MAX_CURRENT			0x0048	/* 64 bits */
102 #define	REG_SLOT_INT_STAT		0x00FC	/* 16 bits */
103 #define	REG_VERSION			0x00FE	/* 16 bits */
104 #define	REG_ERR_FORCE			0x0052	/* 16 bits */
105 #define	REG_ACMD12_ERROR_FORCE		0x0050	/* 16 bits */
106 #define	REG_ADMA_ERROR			0x0054	/* 8 bits */
107 #define	REG_ADMA_ADDR			0x0058	/* 64 bits */
108 
109 /* REG_BLKSZ bits */
110 #define	BLKSZ_XFR_BLK_SIZE_MASK		(0x0fff)
111 #define	BLKSZ_BOUNDARY_4K		(0 << 12)
112 #define	BLKSZ_BOUNDARY_8K		(1 << 12)
113 #define	BLKSZ_BOUNDARY_16K		(2 << 12)
114 #define	BLKSZ_BOUNDARY_32K		(3 << 12)
115 #define	BLKSZ_BOUNDARY_64K		(4 << 12)
116 #define	BLKSZ_BOUNDARY_128K		(5 << 12)
117 #define	BLKSZ_BOUNDARY_256K		(6 << 12)
118 #define	BLKSZ_BOUNDARY_512K		(7 << 12)
119 #define	BLKSZ_BOUNDARY_MASK		(0x7 << 12)
120 
121 /* REG_XFR_MODE bits */
122 #define	XFR_MODE_DMA_EN			BIT(0)
123 #define	XFR_MODE_COUNT			BIT(1)
124 #define	XFR_MODE_AUTO_CMD12		BIT(2)
125 #define	XFR_MODE_READ			BIT(4)	/* 1 = read, 0 = write */
126 #define	XFR_MODE_MULTI			BIT(5)	/* 1 = multi, 0 = single */
127 
128 /* REG_COMMAND bits */
129 #define	COMMAND_CRC_CHECK_EN		BIT(3)
130 #define	COMMAND_INDEX_CHECK_EN		BIT(4)
131 #define	COMMAND_DATA_PRESENT		BIT(5)
132 #define	COMMAND_TYPE
133 #define	COMMAND_TYPE_NORM		(0 << 6)
134 #define	COMMAND_TYPE_SUSPEND		(1 << 6)
135 #define	COMMAND_TYPE_RESUME		(2 << 6)
136 #define	COMMAND_TYPE_ABORT		(3 << 6)
137 #define	COMMAND_TYPE_MASK		(0x3 << 6)
138 #define	COMMAND_RESP_NONE		0
139 #define	COMMAND_RESP_136		1	/* R2 */
140 #define	COMMAND_RESP_48			2	/* R1, R3, R6, R7 */
141 #define	COMMAND_RESP_48_BUSY		3	/* R1b */
142 
143 /* REG_PRS bits */
144 #define	PRS_CMD_INHIBIT			BIT(0)
145 #define	PRS_DAT_INHIBIT			BIT(1)
146 #define	PRS_DAT_ACTIVE			BIT(2)
147 #define	PRS_WRITE_ACTIVE		BIT(8)
148 #define	PRS_READ_ACTIVE			BIT(9)
149 #define	PRS_BUF_WR_EN			BIT(10)
150 #define	PRS_BUF_RD_EN			BIT(11)
151 #define	PRS_CARD_INSERTED		BIT(16)
152 #define	PRS_CARD_STABLE			BIT(17)
153 #define	PRS_CARD_DETECT			BIT(18)
154 #define	PRS_WRITE_ENABLE		BIT(19)
155 #define	PRS_DAT0_SIG			BIT(20)
156 #define	PRS_DAT1_SIG			BIT(21)
157 #define	PRS_DAT2_SIG			BIT(22)
158 #define	PRS_DAT3_SIG			BIT(23)
159 
160 #define	PRS_INHIBIT    \
161 	(PRS_CMD_INHIBIT | PRS_DAT_INHIBIT)
162 #define	PRS_DAT_SIG	\
163 	(PRS_DAT0_SIG | PRS_DAT1_SIG | PRS_DAT2_SIG | PRS_DAT3_SIG)
164 
165 /* REG_HOST_CONTROL bits */
166 #define	HOST_CONTROL_LED_ON		BIT(0)
167 #define	HOST_CONTROL_DATA_WIDTH		BIT(1)
168 #define	HOST_CONTROL_HIGH_SPEED_EN	BIT(2)
169 #define	HOST_CONTROL_DMA_SDMA		(0 << 3)
170 #define	HOST_CONTROL_DMA_ADMA32		(2 << 3)
171 #define	HOST_CONTROL_DMA_ADMA64		(3 << 3)
172 #define	HOST_CONTROL_DMA_MASK		(0x3 << 3)
173 #define	HOST_CONTROL_CARD_DETECT_TEST	BIT(6)
174 #define	HOST_CONTROL_CARD_DETECT_SEL	BIT(7)
175 
176 /* REG_POWER_CONTROL bits */
177 #define	POWER_CONTROL_BUS_POWER		BIT(0)
178 #define	POWER_CONTROL_33V		(7 << 1)
179 #define	POWER_CONTROL_30V		(6 << 1)
180 #define	POWER_CONTROL_18V		(5 << 1)
181 
182 /* REG_BLOCK_GAP_CONTROL bits */
183 #define	BLOCK_GAP_CONTROL_STOP		BIT(0)
184 #define	BLOCK_GAP_CONTROL_CONTINUE	BIT(1)
185 #define	BLOCK_GAP_CONTROL_READ_WAIT	BIT(2)
186 #define	BLOCK_GAP_CONTROL_INTERRUPT	BIT(3)
187 
188 /* REG_WAKEUP_CONTROL bits */
189 #define	WAKEUP_CONTROL_INTERRUPT	BIT(0)
190 #define	WAKEUP_CONTROL_INSERT		BIT(1)
191 #define	WAKEUP_CONTROL_REMOVE		BIT(2)
192 
193 /* REG_CLOCK_CONTROL bits */
194 #define	CLOCK_CONTROL_INT_CLOCK_EN	BIT(0)
195 #define	CLOCK_CONTROL_INT_CLOCK_STABLE	BIT(1)
196 #define	CLOCK_CONTROL_SD_CLOCK_EN	BIT(2)
197 #define	CLOCK_CONTROL_FREQ_MASK		(0xff << 8)
198 #define	CLOCK_CONTROL_FREQ_SHIFT	8
199 
200 /* REG_TIMEOUT_CONTROL bits */
201 #define	TIMEOUT_TIMECLK_2_27		(0xe)
202 /* not listing them all here... but it goes on */
203 #define	TIMEOUT_TIMECLK_2_13		(0x0)
204 
205 /* REG_SOFT_RESET bits */
206 #define	SOFT_RESET_ALL			BIT(0)
207 #define	SOFT_RESET_CMD			BIT(1)
208 #define	SOFT_RESET_DAT			BIT(2)
209 
210 /* REG_INT_{STAT,EN,MASK} bits */
211 #define	INT_CMD				BIT(0)
212 #define	INT_XFR				BIT(1)
213 #define	INT_BG				BIT(2)
214 #define	INT_DMA				BIT(3)
215 #define	INT_WR				BIT(4)
216 #define	INT_RD				BIT(5)
217 #define	INT_INS				BIT(6)
218 #define	INT_REM				BIT(7)
219 #define	INT_CARD			BIT(8)
220 #define	INT_ERR				BIT(15)
221 
222 #define	INT_PIO		(INT_RD | INT_WR)
223 #define	INT_HOTPLUG	(INT_INS | INT_REM)
224 
225 #define	INT_MASK	(INT_XFR | INT_DMA | INT_PIO | INT_HOTPLUG)
226 #define	INT_ENAB	(INT_MASK | INT_CMD)
227 
228 /* REG_ERR_{STAT,EN,MASK} bits */
229 #define	ERR_VENDOR			(0xf << 12)
230 #define	ERR_ADMA			BIT(9)
231 #define	ERR_ACMD12			BIT(8)
232 #define	ERR_CURRENT			BIT(7)
233 #define	ERR_DAT_END			BIT(6)
234 #define	ERR_DAT_CRC			BIT(5)
235 #define	ERR_DAT_TMO			BIT(4)
236 #define	ERR_CMD_IDX			BIT(3)
237 #define	ERR_CMD_END			BIT(2)
238 #define	ERR_CMD_CRC			BIT(1)
239 #define	ERR_CMD_TMO			BIT(0)
240 
241 #define	ERR_CMD		(ERR_CMD_IDX | ERR_CMD_END | ERR_CMD_CRC | ERR_CMD_TMO)
242 #define	ERR_CMD_CFL	(ERR_CMD_CRC | ERR_CMD_TMO)
243 
244 #define	ERR_DAT		(ERR_DAT_END | ERR_DAT_CRC | ERR_DAT_TMO)
245 
246 #define	ERR_MASK	(ERR_ACMD12 | ERR_DAT)
247 #define	ERR_ENAB	(ERR_MASK | ERR_CMD)
248 
249 /* REG_ACMD12_ERROR bits */
250 #define	ACMD12_ERROR_NOT_EXECUTED	BIT(0)
251 #define	ACMD12_ERROR_TIMEOUT		BIT(1)
252 #define	ACMD12_ERROR_CRC		BIT(2)
253 #define	ACMD12_ERROR_END_BIT		BIT(3)
254 #define	ACMD12_ERROR_INDEX		BIT(4)
255 #define	ACMD12_ERROR_NOT_ISSUED		BIT(7)
256 
257 /* REG_CAPAB bits */
258 #define	CAPAB_TIMEOUT_FREQ_SHIFT	0
259 #define	CAPAB_TIMEOUT_FREQ_MASK		(0x3f << 0)
260 #define	CAPAB_TIMEOUT_UNITS		BIT(7)		/* 1 == MHz, 0 = kHz */
261 #define	CAPAB_BASE_FREQ_SHIFT		8
262 #define	CAPAB_BASE_FREQ_MASK		(0x3f << 8)
263 #define	CAPAB_MAXBLK_512		(0 << 16)
264 #define	CAPAB_MAXBLK_1K			(1 << 16)
265 #define	CAPAB_MAXBLK_2K			(2 << 16)
266 #define	CAPAB_MAXBLK_MASK		(0x3 << 16)
267 #define	CAPAB_ADMA2			BIT(19)
268 #define	CAPAB_ADMA1			BIT(20)
269 #define	CAPAB_HIGH_SPEED		BIT(21)
270 #define	CAPAB_SDMA			BIT(22)
271 #define	CAPAB_SUSPEND			BIT(23)
272 #define	CAPAB_33V			BIT(24)
273 #define	CAPAB_30V			BIT(25)
274 #define	CAPAB_18V			BIT(26)
275 #define	CAPAB_VOLTS			(CAPAB_33V | CAPAB_30V | CAPAB_18V)
276 #define	CAPAB_64BIT			BIT(28)
277 
278 /* REG_MAX_CURRENT bits */
279 #define	MAX_CURRENT_33V_SHIFT		0
280 #define	MAX_CURRENT_33V_MASK		(0xff << 0)
281 #define	MAX_CURRENT_30V_SHIFT		8
282 #define	MAX_CURRENT_30V_MASK		(0xff << 8)
283 #define	MAX_CURRENT_18V_SHIFT		16
284 #define	MAX_CURRENT_18V_MASK		(0xff << 16)
285 
286 /* REG_VERSION bits */
287 #define	VERSION_VENDOR_SHIFT		8
288 #define	VERSION_VENDOR_MASK		(0xff << 8)
289 #define	VERSION_SDHOST_MASK		0xff
290 #define	VERSION_SDHOST_1		0
291 #define	VERSION_SDHOST_2		1
292 
293 /* REG_ADMA_ERROR bits */
294 #define	ADMA_ERROR_STATE_ST_STOP	0
295 #define	ADMA_ERROR_STATE_ST_FDS		1
296 #define	ADMA_ERROR_STATE_ST_TFR		3
297 #define	ADMA_ERROR_STATE_MASK		0x3
298 #define	ADMA_ERROR_LEN_MISMATCH		BIT(2)
299 
300 /*
301  * Properties.
302  */
303 #define	SDHOST_PROP_ENABLE_MSI		"enable-msi"
304 #define	SDHOST_PROP_ENABLE_MSIX		"enable-msix"
305 #define	SDHOST_PROP_FORCE_PIO		"force-pio"
306 #define	SDHOST_PROP_FORCE_DMA		"force-dma"
307 
308 #endif	/* _SYS_SDCARD_SDHOST_H */
309