xref: /illumos-gate/usr/src/uts/sun4u/sys/pci/pci_var.h (revision 26947304)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef _SYS_PCI_VAR_H
27 #define	_SYS_PCI_VAR_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 /*
34  * The following typedef is used to represent a
35  * 1275 "reg" property of a PCI nexus.
36  */
37 typedef struct pci_nexus_regspec {
38 	uint64_t phys_addr;
39 	uint64_t size;
40 } pci_nexus_regspec_t;
41 
42 typedef enum { PSYCHO, SCHIZO } pci_bridge_t;
43 typedef enum { A, B } pci_side_t;
44 typedef enum { PCI_NEW, PCI_ATTACHED, PCI_DETACHED, PCI_SUSPENDED } pci_state_t;
45 typedef enum { PCI_PBM_OBJ, PCI_ECC_OBJ, PCI_CB_OBJ } pci_obj_t;
46 typedef enum { PCI_OBJ_INTR_ADD, PCI_OBJ_INTR_REMOVE } pci_obj_op_t;
47 
48 #define	PCI_ATTACH_RETCODE(obj, op, err) \
49 	((err) ? (obj) << 8 | (op) << 4 | (err) & 0xf : DDI_SUCCESS)
50 
51 #define	PCI_OTHER_SIDE(side) ((side) ^ 1)
52 
53 /*
54  * the sequence of the chip_type appearance is significant. There are code
55  * depending on it: CHIP_TYPE(pci_p) < PCI_CHIP_SCHIZO.
56  */
57 typedef enum {
58 	PCI_CHIP_UNIDENTIFIED = 0,
59 
60 	PCI_CHIP_PSYCHO = 1,
61 	PCI_CHIP_SABRE,
62 	PCI_CHIP_HUMMINGBIRD,
63 
64 	PCI_CHIP_SCHIZO = 0x11,
65 	PCI_CHIP_XMITS,
66 	PCI_CHIP_TOMATILLO
67 } pci_chip_id_t;
68 
69 /*
70  * [msb]				[lsb]
71  * 0x00 <chip_type> <version#> <module-revision#>
72  */
73 #define	CHIP_ID(t, v, m) 	(((t) << 16) | ((v) << 8) | (m))
74 #define	ID_CHIP_TYPE(id) 	((id) >> 16)
75 #define	PCI_CHIP_ID(pci_p) 	((pci_p)->pci_common_p->pci_chip_id)
76 #define	CHIP_TYPE(pci_p) 	ID_CHIP_TYPE(PCI_CHIP_ID(pci_p))
77 #define	CHIP_REV(pci_p)		(PCI_CHIP_ID(pci_p) & 0xFF)
78 #define	CHIP_VER(pci_p)		((PCI_CHIP_ID(pci_p) >> 8) & 0xFF)
79 #define	CB_CHIP_TYPE(cb_p) 	((cb_p)->cb_pci_cmn_p->pci_chip_id >> 16)
80 
81 /*
82  * pci common soft state structure:
83  *
84  * Each psycho or schizo is represented by a pair of pci nodes in the
85  * device tree.  A single pci common soft state is allocated for each
86  * pair.  The UPA (Safari) bus id of the psycho (schizo) is used for
87  * the instance number.  The attach routine uses the existance of a
88  * pci common soft state structure to determine if one node from the
89  * pair has been attached.
90  */
91 struct pci_common {
92 	uint_t pci_common_id;
93 
94 	/* pointers & counters to facilitate attach/detach & suspend/resume */
95 	ushort_t pci_common_refcnt;	/* # of sides suspended + attached */
96 	ushort_t pci_common_attachcnt;	/* # of sides attached */
97 	uint16_t pci_common_tsb_cookie;	/* IOMMU TSB allocation */
98 	pci_t *pci_p[2];		/* pci soft states of both sides */
99 
100 	uint32_t pci_chip_id;		/* Bus bridge chip identification */
101 
102 	/* Links to functional blocks potentially shared between pci nodes */
103 	iommu_t *pci_common_iommu_p;
104 	cb_t *pci_common_cb_p;
105 	ib_t *pci_common_ib_p;
106 	ecc_t *pci_common_ecc_p;
107 
108 	/*
109 	 * Performance counters kstat.
110 	 */
111 	pci_cntr_pa_t	pci_cmn_uks_pa;
112 	kstat_t	*pci_common_uksp;	/* ptr to upstream kstat */
113 	kmutex_t pci_fm_mutex;		/* per chip error handling mutex */
114 };
115 
116 /*
117  * pci soft state structure:
118  *
119  * Each pci node has a pci soft state structure.
120  */
121 struct pci {
122 	/*
123 	 * State flags and mutex:
124 	 */
125 	pci_state_t pci_state;
126 	uint_t pci_soft_state;
127 	uint16_t pci_tsb_cookie;	/* IOMMU TSB allocation */
128 	kmutex_t pci_mutex;
129 
130 	/*
131 	 * Links to other state structures:
132 	 */
133 	pci_common_t *pci_common_p;	/* pointer common soft state */
134 	dev_info_t *pci_dip;		/* devinfo structure */
135 	ib_t *pci_ib_p;			/* interrupt block */
136 	cb_t *pci_cb_p;			/* control block */
137 	pbm_t *pci_pbm_p;		/* PBM block */
138 	iommu_t	*pci_iommu_p;		/* IOMMU block */
139 	sc_t *pci_sc_p;			/* streaming cache block */
140 	ecc_t *pci_ecc_p;		/* ECC error block */
141 
142 	/*
143 	 * other state info:
144 	 */
145 	uint_t pci_id;			/* UPA (or Safari) device id */
146 	pci_side_t pci_side;
147 
148 	/*
149 	 * pci device node properties:
150 	 */
151 	pci_bus_range_t pci_bus_range;	/* "bus-range" */
152 	pci_ranges_t *pci_ranges;	/* "ranges" data & length */
153 	int pci_ranges_length;
154 	uint32_t *pci_inos;		/* inos from "interrupts" prop */
155 	int pci_inos_len;		/* "interrupts" length */
156 	int pci_numproxy;		/* upa interrupt proxies */
157 	int pci_thermal_interrupt;	/* node has thermal interrupt */
158 
159 	/*
160 	 * register mapping:
161 	 */
162 	caddr_t pci_address[4];
163 	ddi_acc_handle_t pci_ac[4];
164 
165 	/* Interrupt support */
166 	int intr_map_size;
167 	struct intr_map *intr_map;
168 	struct intr_map_mask *intr_map_mask;
169 
170 	/* performance counters */
171 	pci_cntr_addr_t	pci_ks_addr;
172 	kstat_t	*pci_ksp;
173 
174 	/* Hotplug information */
175 
176 	boolean_t	hotplug_capable;
177 
178 	/* Fault Management support */
179 	int pci_fm_cap;
180 	ddi_iblock_cookie_t pci_fm_ibc;
181 };
182 
183 /*
184  * PSYCHO and PBM soft state macros:
185  */
186 #define	get_pci_soft_state(i)	\
187 	((pci_t *)ddi_get_soft_state(per_pci_state, (i)))
188 
189 #define	alloc_pci_soft_state(i)	\
190 	ddi_soft_state_zalloc(per_pci_state, (i))
191 
192 #define	free_pci_soft_state(i)	\
193 	ddi_soft_state_free(per_pci_state, (i))
194 
195 #define	get_pci_common_soft_state(i)	\
196 	((pci_common_t *)ddi_get_soft_state(per_pci_common_state, (i)))
197 
198 #define	alloc_pci_common_soft_state(i)	\
199 	ddi_soft_state_zalloc(per_pci_common_state, (i))
200 
201 #define	free_pci_common_soft_state(i)	\
202 	ddi_soft_state_free(per_pci_common_state, (i))
203 
204 #define	DEV_TO_SOFTSTATE(dev)	((pci_t *)ddi_get_soft_state(per_pci_state, \
205 	PCIHP_AP_MINOR_NUM_TO_INSTANCE(getminor(dev))))
206 
207 extern void *per_pci_state;		/* per-pbm soft state pointer */
208 extern void *per_pci_common_state;	/* per-psycho soft state pointer */
209 extern kmutex_t pci_global_mutex;	/* attach/detach common struct lock */
210 extern kmutex_t dvma_active_list_mutex;
211 
212 /*
213  * function prototypes for bus ops routines:
214  */
215 extern int
216 pci_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp,
217 	off_t offset, off_t len, caddr_t *addrp);
218 extern int
219 pci_dma_setup(dev_info_t *dip, dev_info_t *rdip,
220 	ddi_dma_req_t *dmareq, ddi_dma_handle_t *handlep);
221 extern int
222 pci_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp,
223 	int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep);
224 extern int
225 pci_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip,
226 	ddi_dma_handle_t handle, ddi_dma_req_t *dmareq,
227 	ddi_dma_cookie_t *cookiep, uint_t *ccountp);
228 extern int
229 pci_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip,
230 	ddi_dma_handle_t handle);
231 extern int
232 pci_dma_flush(dev_info_t *dip, dev_info_t *rdip,
233 	ddi_dma_handle_t handle, off_t off, size_t len,
234 	uint_t cache_flags);
235 extern int
236 pci_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle,
237 	enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp,
238 	uint_t cache_flags);
239 extern int
240 pci_ctlops(dev_info_t *dip, dev_info_t *rdip,
241 	ddi_ctl_enum_t op, void *arg, void *result);
242 extern int
243 pci_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op,
244 	ddi_intr_handle_impl_t *handle, void *result);
245 
246 #ifdef	__cplusplus
247 }
248 #endif
249 
250 #endif	/* _SYS_PCI_VAR_H */
251