xref: /illumos-gate/usr/src/uts/sun4v/sys/mmu.h (revision 9d0d62ad)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_SYS_MMU_H
28 #define	_SYS_MMU_H
29 
30 #ifdef	__cplusplus
31 extern "C" {
32 #endif
33 
34 #ifndef _ASM
35 #include <sys/types.h>
36 #endif
37 #include <sys/hypervisor_api.h>
38 
39 /*
40  * Definitions for the SOFT MMU
41  */
42 
43 #define	FAST_IMMU_MISS_TT	0x64
44 #define	FAST_DMMU_MISS_TT	0x68
45 #define	FAST_PROT_TT		0x6c
46 
47 /*
48  * Constants defining alternate spaces
49  * and register layouts within them,
50  * and a few other interesting assembly constants.
51  */
52 
53 /*
54  * vaddr offsets of various registers
55  */
56 #define	MMU_PCONTEXT		0x08 /* primary context number */
57 #define	MMU_SCONTEXT		0x10 /* secondary context number */
58 
59 #define	MMU_PCONTEXT0		MMU_PCONTEXT	/* primary context# 0 */
60 #define	MMU_PCONTEXT1		0x108		/* primary context# 1 */
61 #define	MMU_SCONTEXT0		MMU_SCONTEXT	/* secondary context# 0 */
62 #define	MMU_SCONTEXT1		0x110		/* secondary context# 1 */
63 
64 /*
65  * Pseudo Synchronous Fault Status Register Layout
66  *
67  * IMMU and DMMU maintain their own pseudo SFSR Register
68  *
69  * +------------------------------------------------+
70  * |       Reserved       |   Context   |     FT    |
71  * +----------------------|-------------------------+
72  *  63                  32 31         16 15         0
73  *
74  */
75 #define	SFSR_FT		0x0000FFFF	/* fault type mask */
76 #define	SFSR_CTX	0xFFFF0000	/* fault context mask */
77 
78 /*
79  * Definition of FT (Fault Type) bit field of sfsr.
80  */
81 #define	FT_NONE		0x00
82 #define	FT_PRIV		MMFSA_F_PRIV	/* privilege violation */
83 #define	FT_SPEC_LD	MMFSA_F_SOPG	/* speculative ld to e page */
84 #define	FT_ATOMIC_NC	MMFSA_F_NCATM	/* atomic to nc page */
85 #define	FT_ILL_ALT	MMFSA_F_INVASI	/* illegal lda/sta */
86 #define	FT_NFO		MMFSA_F_NFO	/* normal access to nfo page */
87 #define	FT_RANGE	MMFSA_F_INVVA	/* dmmu or immu address out of range */
88 #define	FT_NEW_FMISS	MMFSA_F_FMISS	/* fast miss */
89 #define	FT_NEW_FPROT	MMFSA_F_FPROT	/* fast protection */
90 #define	FT_NEW_MISS	MMFSA_F_MISS	/* mmu miss */
91 #define	FT_NEW_INVRA	MMFSA_F_INVRA	/* invalid RA */
92 #define	FT_NEW_PROT	MMFSA_F_PROT	/* protection violation */
93 #define	FT_NEW_PRVACT	MMFSA_F_PRVACT	/* privileged action */
94 #define	FT_NEW_WPT	MMFSA_F_WPT	/* watchpoint hit */
95 #define	FT_NEW_UNALIGN	MMFSA_F_UNALIGN	/* unaligned access */
96 #define	FT_NEW_INVPGSZ	MMFSA_F_INVPGSZ	/* invalid page size */
97 
98 #define	SFSR_FT_SHIFT	0	/* amt. to shift right to get flt type */
99 #define	SFSR_CTX_SHIFT	16	/* to shift right to get context */
100 #define	X_FAULT_TYPE(x)	(((x) & SFSR_FT) >> SFSR_FT_SHIFT)
101 #define	X_FAULT_CTX(x)	(((x) & SFSR_CTX) >> SFSR_CTX_SHIFT)
102 
103 /*
104  * MMU TAG TARGET register Layout
105  *
106  * +---------------+------+-------------------------+
107  * |    context    |  --  | virtual address [63:22] |
108  * +---------------+------+-------------------------+
109  *  63           48 47  42 41                      0
110  *
111  * Some sun4v processors only use a 13-bit context ID, so bits 61-63 will be
112  * zero in that case.  This layout allows us to use the same code for any sun4v
113  * processors, whether they support 13 bit or 16 bit context IDs (or something
114  * in between).
115  */
116 #define	TTARGET_CTX_SHIFT	48
117 #define	TTARGET_VA_SHIFT	22
118 
119 /*
120  * Pseudo MMU TAG ACCESS register Layout
121  *
122  * +-------------------------+------------------+
123  * | virtual address [63:13] |     0     | type |
124  * +-------------------------+------------------+
125  *  63			  13	12      2 1    0
126  *
127  * 16-bit context IDs don't fit into the 13 bit field as they did on sun4u,
128  * so we use a context type, 0 = kernel context, 1 = invalid context,
129  * 2 = user context.
130  */
131 #define	TAGACC_CTX_MASK		0x1FFF
132 #define	TAGACC_SHIFT		13
133 #define	TAGACC_VADDR_MASK	(~TAGACC_CTX_MASK)
134 #define	TAGACC_CTX_LSHIFT	(64 - TAGACC_SHIFT)
135 
136 /*
137  * The kernel always runs in KCONTEXT, and no user mappings
138  * are ever valid in it (so any user access pagefaults).
139  */
140 #define	KCONTEXT	0
141 
142 /*
143  * FLUSH_ADDR is used in the flush instruction to guarantee stores to mmu
144  * registers complete.  It is selected so it won't miss in the tlb.
145  */
146 #define	FLUSH_ADDR	(KERNELBASE + 2 * MMU_PAGESIZE4M)
147 
148 #define	MAX_NCTXS_BITS			16	/* sun4v max. contexts bits */
149 #define	MIN_NCTXS_BITS			2
150 #define	MAX_NCTXS	(1ull << MAX_NCTXS_BITS)
151 
152 /*
153  * MIN_NSHCONTEXTS and MIN_NTSBS are the minimum number of shared contexts
154  * and tsbs necessary for shared context support.
155  */
156 #define	MIN_NSHCONTEXTS			1
157 #define	MIN_NTSBS			4
158 
159 #ifdef	__cplusplus
160 }
161 #endif
162 
163 #endif /* _SYS_MMU_H */
164