1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_AUDIOIXP_H_
27 #define	_AUDIOIXP_H_
28 
29 /*
30  * Header file for the audioixp device driver
31  */
32 
33 #define	IXP_DEV_CONFIG		"onboard1"
34 #define	IXP_DEV_VERSION		"a"
35 
36 /*
37  * Driver supported configuration information
38  */
39 #define	IXP_NAME		"audioixp"
40 #define	IXP_MOD_NAME		"ATI IXP audio driver"
41 #define	IXP_CONFIG_REGS		(0)	/* PCI configure register */
42 #define	IXP_IO_AM_REGS		(1)	/* PCI base register 0x10 */
43 
44 #define	IXP_PLAY		0
45 #define	IXP_REC			1
46 
47 #define	IXP_BD_NUMS			(8)
48 
49 /*
50  * PCI configuration registers and bits
51  */
52 #define	IXP_PCI_ID_200		(0x10024341U)
53 #define	IXP_PCI_ID_300		(0x10024361U)
54 #define	IXP_PCI_ID_400		(0x10024370U)
55 #define	IXP_PCI_ID_SB600	(0x10024382U)
56 
57 /*
58  * Audio controller registers and bits
59  */
60 #define	IXP_AUDIO_INT				(0x00)
61 #define	IXP_AUDIO_INT_IN_DMA_OVERFLOW		(1U<<0)
62 #define	IXP_AUDIO_INT_IN_DMA			(1U<<1)
63 #define	IXP_AUDIO_INT_OUT_DMA_UNDERFLOW		(1U<<2)
64 #define	IXP_AUDIO_INT_OUT_DMA			(1U<<3)
65 #define	IXP_AUDIO_INT_CODEC0_NOT_READY		(1U<<10)
66 #define	IXP_AUDIO_INT_CODEC1_NOT_READY		(1U<<11)
67 #define	IXP_AUDIO_INT_CODEC2_NOT_READY		(1U<<12)
68 #define	IXP_AUDIO_INT_NEW_FRAME			(1U<<13)
69 
70 #define	IXP_AUDIO_INT_EN			(0x04)
71 #define	IXP_AUDIO_INT_EN_IN_DMA_OVERFLOW	(1U<<0)
72 #define	IXP_AUDIO_INT_EN_STATUS			(1U<<1)
73 #define	IXP_AUDIO_INT_EN_OUT_DMA_UNDERFLOW	(1U<<2)
74 #define	IXP_AUDIO_INT_EN_CODEC0_NOT_READY	(1U<<10)
75 #define	IXP_AUDIO_INT_EN_CODEC1_NOT_READY	(1U<<11)
76 #define	IXP_AUDIO_INT_EN_CODEC2_NOT_READY	(1U<<12)
77 #define	IXP_AUDIO_INT_EN_NEW_FRAME		(1U<<13)
78 
79 #define	IXP_AUDIO_CMD				(0x08)
80 #define	IXP_AUDIO_CMD_POWER_DOWN		(1U<<0)
81 #define	IXP_AUDIO_CMD_EN_IN			(1U<<1)
82 #define	IXP_AUDIO_CMD_EN_OUT			(1U<<2)
83 #define	IXP_AUDIO_CMD_EN_IN_DMA			(1U<<8)
84 #define	IXP_AUDIO_CMD_EN_OUT_DMA		(1U<<9)
85 #define	IXP_AUDIO_CMD_INTER_IN			(1U<<21)
86 #define	IXP_AUDIO_CMD_INTER_OUT			(1U<<22)
87 #define	IXP_AUDIO_CMD_BURST_EN			(1U<<25)
88 #define	IXP_AUDIO_CMD_AC_ACTIVE			(1U<<28)
89 #define	IXP_AUDIO_CMD_AC_SOFT_RESET		(1U<<29)
90 #define	IXP_AUDIO_CMD_AC_SYNC			(1U<<30)
91 #define	IXP_AUDIO_CMD_AC_RESET			(1U<<31)
92 
93 #define	IXP_AUDIO_OUT_PHY_ADDR_DATA		(0x0c)
94 #define	IXP_AUDIO_OUT_PHY_PRIMARY_CODEC	(0u)
95 #define	IXP_AUDIO_OUT_PHY_SECOND_CODEC	(1u)
96 #define	IXP_AUDIO_OUT_PHY_THIRD_CODEC	(2u)
97 #define	IXP_AUDIO_OUT_PHY_READ		(1u<<2)
98 #define	IXP_AUDIO_OUT_PHY_WRITE		(0u)
99 #define	IXP_AUDIO_OUT_PHY_EN			(1u<<8)
100 #define	IXP_AUDIO_OUT_PHY_ADDR_SHIFT		(9)
101 #define	IXP_AUDIO_OUT_PHY_ADDR_MASK		(0x7fu<<9)
102 #define	IXP_AUDIO_OUT_PHY_DATA_SHIFT		(16)
103 #define	IXP_AUDIO_OUT_PHY_DATA_MASK		(0xffffu<<16)
104 
105 #define	IXP_AUDIO_IN_PHY_ADDR_DATA		(0x10)
106 #define	IXP_AUDIO_IN_PHY_READY			(1u<<8)
107 #define	IXP_AUDIO_IN_PHY_ADDR_SHIFT		(9)
108 #define	IXP_AUDIO_IN_PHY_ADDR_MASK		(0x7fu<<9)
109 #define	IXP_AUDIO_IN_PHY_DATA_SHIFT		(16)
110 #define	IXP_AUDIO_IN_PHY_DATA_MASK		(0xffffu<<16)
111 
112 #define	IXP_AUDIO_SLOTREQ			(0x14)
113 #define	IXP_AUDIO_COUNTER			(0x18)
114 #define	IXP_AUDIO_IN_FIFO_THRESHOLD		(0x1c)
115 #define	IXP_AUDIO_IN_DMA_LINK_P			(0x20)
116 #define	IXP_AUDIO_IN_DMA_LINK_P_EN		(1u<<0)
117 
118 #define	IXP_AUDIO_IN_DMA_DT_START		(0x24)
119 #define	IXP_AUDIO_IN_DMA_DT_NEXT		(0x28)
120 #define	IXP_AUDIO_IN_DMA_DT_CUR			(0x2c)
121 #define	IXP_AUDIO_IN_DT_SIZE_FIFO_INFO		(0x30)
122 
123 #define	IXP_AUDIO_OUT_DMA_SLOT_EN_THRESHOLD	(0x34)
124 #define	IXP_AUDIO_OUT_DMA_SLOT_3		(1U<<0)
125 #define	IXP_AUDIO_OUT_DMA_SLOT_4		(1U<<1)
126 #define	IXP_AUDIO_OUT_DMA_SLOT_5		(1U<<2)
127 #define	IXP_AUDIO_OUT_DMA_SLOT_6		(1U<<3)
128 #define	IXP_AUDIO_OUT_DMA_SLOT_7		(1U<<4)
129 #define	IXP_AUDIO_OUT_DMA_SLOT_8		(1U<<5)
130 #define	IXP_AUDIO_OUT_DMA_SLOT_9		(1U<<6)
131 #define	IXP_AUDIO_OUT_DMA_SLOT_10		(1U<<7)
132 #define	IXP_AUDIO_OUT_DMA_SLOT_11		(1U<<8)
133 #define	IXP_AUDIO_OUT_DMA_SLOT_12		(1U<<9)
134 #define	IXP_AUDIO_OUT_DMA_THRESHOLD_MASK	(0x7fU<<11)
135 #define	IXP_AUDIO_OUT_DMA_THRESHOLD_SHIFT	(11)
136 
137 #define	IXP_AUDIO_OUT_DMA_LINK_P		(0x38)
138 #define	IXP_AUDIO_OUT_DMA_LINK_P_EN		(1U<<0)
139 
140 #define	IXP_AUDIO_OUT_DMA_DT_START		(0x3c)
141 #define	IXP_AUDIO_OUT_DMA_DT_NEXT		(0x40)
142 #define	IXP_AUDIO_OUT_DMA_DT_CUR		(0x44)
143 #define	IXP_AUDIO_OUT_DT_SIZE_USED_FREE		(0x48)
144 #define	IXP_AUDIO_SPDIF_CMD			(0x4c)
145 #define	IXP_AUDIO_SPDIF_LINK_P			(0x50)
146 #define	IXP_AUDIO_SPDIF_DT_START		(0x54)
147 #define	IXP_AUDIO_SPDIF_DT_NEXT			(0x58)
148 #define	IXP_AUDIO_SPDIF_DT_CUR			(0x5c)
149 #define	IXP_AUDIO_SPDIF_DT_SIZE_FIFO_INFO	(0x60)
150 #define	IXP_AUDIO_MODEM_MIRROR			(0x7c)
151 #define	IXP_AUDIO_AUDIO_MIRROR			(0x80)
152 #define	IXP_AUDIO_6CH_RECORDER_EN		(0x84)
153 #define	IXP_AUDIO_FIFO_FLUSH		(0x88)
154 #define	IXP_AUDIO_FIFO_FLUSH_OUT		(1u<<0)
155 #define	IXP_AUDIO_FIFO_FLUSH_IN			(1u<<1)
156 
157 #define	IXP_AUDIO_OUT_FIFO_INFO		(0x8c)
158 #define	IXP_AUDIO_SPDIF_STATUS_BITS_REG1	(0x90)
159 #define	IXP_AUDIO_SPDIF_STATUS_BITS_REG2	(0x94)
160 #define	IXP_AUDIO_SPDIF_STATUS_BITS_REG3	(0x98)
161 #define	IXP_AUDIO_SPDIF_STATUS_BITS_REG4	(0x9c)
162 #define	IXP_AUDIO_SPDIF_STATUS_BITS_REG5	(0xa0)
163 #define	IXP_AUDIO_SPDIF_STATUS_BITS_REG6	(0xa4)
164 #define	IXP_AUDIO_PHY_SEMA			(0xa8)
165 
166 /*
167  * AC97 status and link control registers are located
168  * in PCI configuration space.
169  */
170 #define	IXP_REG_GSR				0x40
171 #define	IXP_REG_GCR				0x41
172 
173 /* AC link interface status register */
174 #define	IXP_GSR_PRI_READY			0x01
175 #define	IXP_GSR_SEC_READY			0x04
176 #define	IXP_GSR_TRI_READY			0x10
177 #define	IXP_GSR_FOUR_READY			0x20
178 
179 /* AC link interface control register */
180 #define	IXP_GCR_ENAC97				0x80
181 #define	IXP_GCR_RST				0x40
182 #define	IXP_GCR_RSYNCHI				0x20
183 #define	IXP_GCR_SDO				0x10
184 #define	IXP_GCR_VSR				0x08
185 #define	IXP_GCR_3D_AUDIO_CHANNEL		0x04
186 
187 /*
188  * Macro for AD1980 codec
189  */
190 #define	AD1980_VID1		0x4144
191 #define	AD1980_VID2		0x5370
192 #define	AD1985_VID2		0x5375
193 #define	CODEC_AD_REG_MISC	0x76	/* offset of ad1980 misc control reg */
194 #define	AD1980_MISC_LOSEL	0x0020	/* Line-out amplifier output selector */
195 #define	AD1980_MISC_HPSEL	0x0400	/* HP-out amplifier output selector */
196 
197 struct audioixp_port {
198 	int			num;
199 	struct audioixp_state	*statep;
200 	ddi_dma_handle_t	samp_dmah;
201 	ddi_acc_handle_t	samp_acch;
202 	size_t			samp_size;
203 	caddr_t			samp_kaddr;
204 	uint32_t		samp_paddr;
205 
206 	ddi_dma_handle_t	bdl_dmah;
207 	ddi_acc_handle_t	bdl_acch;
208 	size_t			bdl_size;
209 	caddr_t			bdl_kaddr;
210 	uint32_t		bdl_paddr;
211 
212 	unsigned		nframes;
213 	unsigned		fragfr;
214 	unsigned		fragsz;
215 	uint64_t		count;
216 	uint32_t		offset;
217 	uint8_t			nchan;
218 
219 	unsigned		sync_dir;
220 
221 	boolean_t		started;
222 
223 	audio_engine_t		*engine;
224 };
225 typedef struct audioixp_port audioixp_port_t;
226 
227 /*
228  * buffer descriptor list entry, see datasheet
229  */
230 struct audioixp_bd_entry {
231 	uint32_t	buf_base;	/* the address of the buffer */
232 	uint16_t	status;		/* status of the buffer */
233 	uint16_t	buf_len;	/* size of the buffer in DWORD */
234 	uint32_t	next;		/* physical addr of next bd_entry */
235 };
236 typedef struct	audioixp_bd_entry	audioixp_bd_entry_t;
237 
238 /*
239  * audioixp_state_t	-per instance state and operation data
240  */
241 struct audioixp_state {
242 	kmutex_t		inst_lock;	/* state protection lock */
243 	dev_info_t		*dip;
244 	audio_dev_t		*adev;		/* audio handle */
245 	ac97_t			*ac97;
246 	audioixp_port_t		*play_port;
247 	audioixp_port_t		*rec_port;
248 
249 	ddi_acc_handle_t	pcih;		/* pci configuration space */
250 	ddi_acc_handle_t	regsh;		/* for audio mixer register */
251 	caddr_t			regsp;		/* base of audio mixer regs */
252 
253 	boolean_t		suspended;
254 	boolean_t		swap_out;	/* swap line-out and sur-out */
255 
256 	uint32_t		ixp_codec_not_ready_bits; /* for codec detect */
257 };
258 typedef struct audioixp_state	 audioixp_state_t;
259 
260 /*
261  * Useful bit twiddlers
262  */
263 #define	GET32(reg)	\
264 	ddi_get32(statep->regsh, (void *)(statep->regsp + (reg)))
265 
266 #define	PUT32(reg, val)	\
267 	ddi_put32(statep->regsh, (void *)(statep->regsp + (reg)), (val))
268 
269 #define	SET32(reg, val)	PUT32(reg, GET32(reg) | ((uint32_t)(val)))
270 
271 #define	CLR32(reg, val)	PUT32(reg, GET32(reg) & ~((uint32_t)(val)))
272 
273 #define	IXP_INTS		(175)	/* default interrupt rate */
274 #define	IXP_MIN_INTS		(24)	/* minimum interrupt rate */
275 #define	IXP_MAX_INTS		(500)	/* maximum interrupt rate */
276 
277 #endif /* _AUDIOIXP_H_ */
278